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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-00203-3E
F2MC-16FX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
F2MC-16FX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
FUJITSU MICROELECTRONICS LIMITED
CONTENTS
■ Objectives and Intended Readership
The F2MC-16FX series products are original 16-bit one-chip microcontrollers that support
application specific ICs (ASICs). They are suitable for use in various types of industrial
equipment, office-automation equipment, on-vehicle equipment, and other equipment that is
required to operate at high speed in real-time mode.
■ Trademark
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■ Intended Readership
This manual is written for engineers involved in the development of products using the F2MC16FX series microcontrollers. It is designed specially for programmers working in assembly
language for use with F2MC-16FX series assemblers, and describes the various instructions
used with the F2MC-16FX series products. Be sure to read the entire manual carefully.
■ Configuration of this Manual
This manual contains the following 8 chapters and appendix.
CHAPTER 1 CPU
This chapter describes an overview of the F2MC-16FX CPU core and its sample
configuration.
CHAPTER 2 MEMORY SPACE
This chapter describes memory spaces in the F2MC-16FX CPU.
CHAPTER 3 DEDICATED REGISTER
This chapter describes the dedicated registers of the F2MC-16FX CPU.
CHAPTER 4 GENERAL-PURPOSE REGISTERS
This chapter describes the general-purpose registers of the F2MC-16FX CPU.
CHAPTER 5 PREFIX CODES
This chapter describes the prefix codes.
CHAPTER 6 INTERRUPTS
This chapter describes the interrupt functions and operations of the F2MC-16FX.
CHAPTER 7 ADDRESSING
This chapter describes the addressing mode for each instruction of the F2MC-16FX.
CHAPTER 8 DETAILED INSTRUCTIONS
This chapter describes each execution instruction used in the assembler in a reference
format. The execution instructions are presented in alphabetical order.
i
APPENDIX
The appendix section includes lists and maps of instructions for the F2MC-16FX.
■ References
The following manuals should be referred along with this manual:
• F2MC-16FX/16L/16/16H/16F Assembler Manual
• F2MC-16FX Model-Specific Hardware Manual
ii
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS
device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use
based on such information. When you develop equipment incorporating the device based on such information, you
must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS
assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be
construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or
any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS
warrant non-infringement of any third-party's intellectual property right or other right by using such information.
FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control
in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any
claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance
with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control
laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
Copyright ©2008-2010 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
iii
iv
CONTENTS
CHAPTER 1
1.1
1.2
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
PREFIX CODES ............................................................................. 37
38
40
41
42
INTERRUPTS ................................................................................. 45
Overview of Interrupts .......................................................................................................
Interrupt Vector ..................................................................................................................
Interrupt Control Registers (ICR) .......................................................................................
Non Maskable Interrupt (NMI) ...........................................................................................
Interrupt Flow .....................................................................................................................
Hardware Interrupts ...........................................................................................................
Software Interrupts ............................................................................................................
Multiple interrupts ..............................................................................................................
Exceptions .........................................................................................................................
CHAPTER 7
7.1
7.2
GENERAL-PURPOSE REGISTERS .............................................. 33
Bank Select Prefix .............................................................................................................
Common Register Bank Prefix (CMR) ...............................................................................
Flag Change Inhibit Prefix Code (NCC) ............................................................................
Constraints Related to the Prefix Codes ...........................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
18
20
22
24
29
30
31
Register Banks in RAM ..................................................................................................... 34
Calling General-purpose Registers in RAM ....................................................................... 36
CHAPTER 5
5.1
5.2
5.3
5.4
10
11
12
14
15
DEDICATED REGISTER ............................................................... 17
Structure of the Dedicated Registers .................................................................................
Accumulator (A) .................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) .............................................
Processor Status (PS) .......................................................................................................
Program Counter (PC) .......................................................................................................
Direct Page Register (DPR) ..............................................................................................
Bank register (PCB, DTB, ADB, USB, SSB) .....................................................................
CHAPTER 4
4.1
4.2
MEMORY SPACE ............................................................................ 9
CPU Memory Space ..........................................................................................................
Linear Addressing Mode ....................................................................................................
Bank Addressing Mode .....................................................................................................
Memory Space Divided into Banks and Value in Each Bank Register ..............................
Data Configuration of and Access to Multi-byte Data in Memory ......................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
CPU .................................................................................................. 1
Overview of CPU ................................................................................................................. 2
Sample Configuration .......................................................................................................... 4
46
48
51
53
55
57
61
63
66
ADDRESSING ................................................................................ 71
Effective Address Field ...................................................................................................... 72
Direct Addressing .............................................................................................................. 73
v
7.3
Indirect Addressing ............................................................................................................ 75
CHAPTER 8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8.23
8.24
8.25
8.26
8.27
8.28
8.29
8.30
8.31
8.32
8.33
8.34
8.35
8.36
8.37
8.38
8.39
8.40
8.41
8.42
8.43
8.44
8.45
DETAILED INSTRUCTIONS .......................................................... 79
Instruction Overview .......................................................................................................... 80
ADD (Add Byte Data of Destination and Source to Destination) ....................................... 83
ADDC (Add Byte Data of AL and AH with Carry to AL) ..................................................... 85
ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator) 86
ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)
........................................................................................................................................... 88
ADDDC (Add Decimal Data of AL and AH with Carry to AL) ............................................ 90
ADDL (Add Long Word Data of Destination and Source to Destination) ........................... 91
ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer) ............ 93
ADDW (Add Word Data of AL and AH to AL) .................................................................... 94
ADDW (Add Word Data of Destination and Source to Destination) .................................. 95
AND (And Byte Data of Destination and Source to Destination) ....................................... 97
AND (And Byte Data of Immediate Data and Condition Code Register) ........................... 99
ANDL (And Long Word Data of Destination and Source to Destination) ......................... 101
ANDW (And Word Data of AH and AL to AL) .................................................................. 103
ANDW (And Word Data of Destination and Source to Destination) ................................ 104
ASR (Arithmetic Shift Byte Data of Accumulator to Right) .............................................. 106
ASRL (Arithmetic Shift Long Word Data of Accumulator to Right) .................................. 108
ASRW (Arithmetic Shift Word Data of Accumulator to Right) .......................................... 110
ASRW (Arithmetic Shift Word Data of Accumulator to Right) .......................................... 112
BBcc (Branch if Bit Condition satisfied) ........................................................................... 114
Bcc (Branch relative if Condition satisfied) ...................................................................... 116
CALL (Call Subroutine) .................................................................................................... 118
CALLP (Call Physical Address) ....................................................................................... 120
CALLV (Call Vectored Subroutine) .................................................................................. 122
CBNE (Compare Byte Data and Branch if not Equal) ..................................................... 124
CLRB (Clear Bit) .............................................................................................................. 126
CMP (Compare Byte Data of Destination and Source) ................................................... 127
CMPL (Compare Long Word Data of Destination and Source) ....................................... 129
CMPW (Compare Word Data of Destination and Source) .............................................. 131
CWBNE (Compare Word Data and Branch if not Equal) ................................................ 133
DBNZ (Decrement Byte Data and Branch if not Zero) .................................................... 135
DEC (Decrement Byte Data) ........................................................................................... 137
DECL (Decrement Long Word Data) ............................................................................... 138
DECW (Decrement Word Data) ...................................................................................... 139
DIV (Divide Word Data by Byte Data) ............................................................................. 141
DIVW (Divide Long Word Data by Word Data) ................................................................ 143
DIVU (Divide unsigned Word Data by unsigned Byte Data) ............................................ 145
DIVUW (Divide unsigned Long Word Data by unsigned Word Data) .............................. 147
DWBNZ (Decrement Word Data and Branch if not Zero) ................................................ 149
EXT (Sign Extend from Byte Data to Word Data) ............................................................ 151
EXTW (Sign Extend from Word Data to Long Word Data) .............................................. 152
FILS, FILSI (Fill String Byte) ............................................................................................ 153
FILSW, FILSWI (Fill String Word) .................................................................................... 155
INC (Increment Byte Data (Address Specification)) ........................................................ 157
INCL (Increment Long Word Data) .................................................................................. 158
vi
8.46
8.47
8.48
8.49
8.50
8.51
8.52
8.53
8.54
8.55
8.56
8.57
8.58
8.59
8.60
8.61
8.62
8.63
8.64
8.65
8.66
8.67
8.68
8.69
8.70
8.71
8.72
8.73
8.74
8.75
8.76
8.77
8.78
8.79
8.80
8.81
8.82
8.83
8.84
8.85
8.86
8.87
8.88
8.89
8.90
8.91
8.92
8.93
8.94
INCW (Increment Word Data) .........................................................................................
INT (Software Interrupt) ...................................................................................................
INT (Software Interrupt (Vector Specification)) ................................................................
INT9 (Software Interrupt) .................................................................................................
INTP (Software Interrupt) ................................................................................................
JCTX (Jump Context) ......................................................................................................
JMP (Jump Destination Address) ....................................................................................
JMPP (Jump Destination Physical Address) ...................................................................
LINK (Link and Create New Stack Frame) ......................................................................
LSL (Logical Shift Byte Data of Accumulator to Left) ......................................................
LSLL (Logical Shift Long Word Data of Accumulator to Left) ..........................................
LSLW (Logical Shift Word Data of Accumulator to Left) ..................................................
LSLW (Logical Shift Word Data of Accumulator to Left) ..................................................
LSR (Logical Shift Byte Data of Accumulator to Right) ...................................................
LSRL (Logical Shift Long Word Data of Accumulator to Right) .......................................
LSRW (Logical Shift Word Data of Accumulator to Right) ...............................................
LSRW (Logical Shift Word Data of Accumulator to Right) ...............................................
MOV (Move Byte Data from Source to Accumulator) ......................................................
MOV (Move Byte Data from Accumulator to Destination) ...............................................
MOV (Move Byte Immediate Data to Destination) ...........................................................
MOV (Move Byte Data from Source to Destination) ........................................................
MOV (Move Byte Data from AH to Memory) ...................................................................
MOVB (Move Bit Data from Bit Address to Accumulator) ...............................................
MOVB (Move Bit Data from Accumulator to Bit Address) ...............................................
MOVEA (Move Effective Address to Destination) ...........................................................
MOVL (Move Long Word Data from Source to Accumulator) .........................................
MOVL (Move Long Word Data from Accumulator to Destination) ...................................
MOVN (Move Immediate Nibble Data to Accumulator) ...................................................
MOVS, MOVSI (Move String Byte with Increment) .........................................................
MOVSD (Move String Byte with Decrement) ...................................................................
MOVSW, MOVSWI (Move String Word with Increment) .................................................
MOVSWD (Move String Word with Decrement) ..............................................................
MOVW (Move Word Data from Source to Accumulator) .................................................
MOVW (Move Word Data from Accumulator to Destination) ...........................................
MOVW (Move Immediate Word Data to Destination) ......................................................
MOVW (Move Word Data from Source to Destination) ...................................................
MOVW (Move Immediate Word Data to io) .....................................................................
MOVW (Move Word Data from AH to Memory) ..............................................................
MOVX (Move Byte Data with Sign Extension from Source to Accumulator) ...................
MUL (Multiply Byte Data of Accumulator) ........................................................................
MUL (Multiply Byte Data of Accumulator and Effective Address) ....................................
MULW (Multiply Word Data of Accumulator) ...................................................................
MULW (Multiply Word Data of Accumulator and Effective Address) ...............................
MULU (Multiply Unsigned Byte Data of Accumulator) .....................................................
MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address) .................
MULUW (Multiply Unsigned Word Data of Accumulator) ................................................
MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address) ............
NEG (Negate Byte Data of Destination) ..........................................................................
NEGW (Negate Word Data of Destination) .....................................................................
vii
159
161
163
165
167
169
171
172
173
174
176
178
179
181
183
185
187
189
191
193
195
197
198
200
202
204
206
208
209
211
212
214
215
217
219
221
223
224
225
227
228
229
230
231
232
233
234
235
236
8.95
8.96
8.97
8.98
8.99
8.100
8.101
8.102
8.103
8.104
8.105
8.106
8.107
8.108
8.109
8.110
8.111
8.112
8.113
8.114
8.115
8.116
8.117
8.118
8.119
8.120
8.121
8.122
8.123
8.124
8.125
8.126
8.127
8.128
8.129
8.130
8.131
8.132
8.133
8.134
8.135
8.136
8.137
8.138
8.139
8.140
NOP (No Operation) ........................................................................................................ 237
NOT (Not Byte Data of Destination) ................................................................................ 238
NOTW (Not Word Data of Destination) ........................................................................... 240
NRML (NORMALIZE Long Word) ................................................................................... 241
OR (Or Byte Data of Destination and Source to Destination) .......................................... 242
OR (Or Byte Data of Immediate Data and Condition Code Register to
Condition Code Register) ................................................................................................ 244
ORL (Or Long Word Data of Destination and Source to Destination) ............................. 246
ORW (Or Word Data of AH and AL to AL) ...................................................................... 248
ORW (Or Word Data of Destination and Source to Destination) ..................................... 249
POPW (Pop Word Data of Accumulator from Stack Memory) ......................................... 251
POPW (Pop Word Data of AH from Stack Memory) ....................................................... 253
POPW (Pop Word Data of Program Status from Stack Memory) .................................... 254
POPW (Pop Registers from Stack Memory) ................................................................... 256
PUSHW (Push Word Data of Inherent Register to Stack Memory) ................................. 258
PUSHW (Push Registers to Stack Memory) ................................................................... 260
RET (Return from Subroutine) ......................................................................................... 262
RETI (Return from Interrupt) ............................................................................................ 263
RETP (Return from Physical Address) ............................................................................ 265
ROLC (Rotate Byte Data of Accumulator with Carry to Left) ........................................... 267
RORC (Rotate Byte Data of Accumulator with Carry to Right) ........................................ 269
SBBS (Set Bit and Branch if Bit Set) ............................................................................... 271
SCEQ, SCEQI (Scan String Byte until equal with Increment) ......................................... 272
SCEQD (Scan String Byte until equal with Decrement) .................................................. 274
SCWEQ, SCWEQI (Scan String Word until equal with Increment) ................................. 276
SCWEQD (Scan String Word until Equal with Decrement) ............................................. 278
SETB (Set Bit) ................................................................................................................. 280
SUB (Subtract Byte Data of Source from Destination to Destination) ............................. 281
SUBC (Subtract Byte Data of AL from AH with Carry to AL) ........................................... 283
SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)
......................................................................................................................................... 284
SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to
Accumulator) ................................................................................................................... 286
SUBDC (Subtract Decimal Data of AL from AH with Carry to AL) ................................... 288
SUBL (Subtract Long Word Data of Source from Destination to Destination) ................. 289
SUBW (Subtract Word Data of Source from Destination to Destination) ........................ 291
SUBW (Subtract Word Data of AL from AH to AL) .......................................................... 293
SWAP (Swap Byte Data of Accumulator) ........................................................................ 294
SWAPW (Swap Word Data of Accumulator) ................................................................... 295
UNLINK (Unlink and Create New Stack Frame) .............................................................. 296
WBTc (Wait until Bit Condition Satisfied) ........................................................................ 297
XCH (Exchange Byte Data of Source to Destination) ..................................................... 299
XCHW (Exchange Word Data of Source to Destination) ................................................. 301
XOR (Exclusive Or Byte Data of Destination and Source to Destination) ....................... 303
XORL (Exclusive Or Long Word Data of Destination and Source to Destination) ........... 305
XORW (Exclusive Or Word Data of AH and AL to AL) .................................................... 307
XORW (Exclusive Or Word Data of Destination and Source to Destination) .................. 308
ZEXT (Zero Extend from Byte Data to Word Data) ......................................................... 310
ZEXTW (Zero Extend from Word Data to Long Word Data) ........................................... 311
viii
APPENDIX ............................................................................................................. 313
APPENDIX A Explanation of Instruction Lists .............................................................................
A.1 Items Used in Instruction Lists ........................................................................................
A.2 Symbols Used in Instruction Lists ...................................................................................
A.3 Effective Address Field ...................................................................................................
APPENDIX B Instruction Lists (351 Instructions) ........................................................................
APPENDIX C Instruction Maps ....................................................................................................
C.1 Structure of the Instruction Map ......................................................................................
C.2 Basic Page Map ..............................................................................................................
C.3 Bit Operation Instruction Map ..........................................................................................
C.4 Character String Operation Instruction Map ....................................................................
C.5 2-byte Instruction Map .....................................................................................................
C.6 ea-type Instruction Map ...................................................................................................
C.7 MOVEA RWi, ea Instruction Map ....................................................................................
C.8 MOV Ri, ea Instruction Map ............................................................................................
C.9 MOVW RWi, ea Instruction Map .....................................................................................
C.10 MOV ea, Ri Instruction Map ............................................................................................
C.11 MOVW ea, RWi Instruction Map .....................................................................................
C.12 XCH Ri, ea Instruction Map .............................................................................................
C.13 XCHW RWi, ea Instruction Map ......................................................................................
314
315
317
319
320
336
337
339
341
343
345
347
357
359
361
363
365
367
369
INDEX ......................................................................................................................371
ix
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
20
CHAPTER 3
DEDICATED REGISTER
3.2 Accumulator (A)
■ Accumulator (A)
Changed the register name.
A register →Accumulator (A)
39
CHAPTER 5 PREFIX CODES
5.1 Bank Select Prefix
■ Bank Select Prefix
Added LINK, UNLINK instructions to Other types of
control instructions (stack manipulation).
41
5.3 Flag Change Inhibit Prefix
Code (NCC)
■ Flag Change Inhibit Prefix Code
(NCC)
Corrected the instruction.
FISW →FILSW
Deleted the MOVE and MOVSW instructions.
Corrected an explanation.
49
CHAPTER 6 INTERRUPTS
6.2 Interrupt Vector
■ Interrupt Vector
● Interrupt Vector Table
Corrected the instructions.
CALLV 14 →CALLV 14/15
51
6.3 Interrupt Control Registers
(ICR)
■ Interrupt Control Register
(ICR)
Corrected the initial value of IX.
"0" →0CH
69
6.9 Exceptions
■ Hardware Exceptions (Non
Maskable Interrupts)
● Instruction break (VEIB, system
reserved, only available with
DSU)
Corrected an explanation.
before execution →after instruction execution
73
CHAPTER 7 ADDRESSING
7.2 Direct Addressing
■ Direct Addressing
● Direct branch address (addr16)
Corrected the register name.
program bank register (PCB) →
program counter bank register (PCB)
76
7.3 Indirect Addressing
■ Indirect Addressing
● Program counter indirect with
displacement (@PC+disp16)
Corrected the register name.
program bank register (PCB) →
program counter bank register (PCB)
● Program counter relative branch
address (rel)
-
81
CHAPTER 8 DETAILED
INSTRUCTIONS
Changed the flag name in "CHAPTER 8 DETAILED
INSTRUCTIONS".
Carry bit (C) →Carry flag (C)
8.1 Instruction Overview
■ Symbols (Abbreviations) Used
in Detailed Instructions
Table 8.1-1
Added brg3.
xi
Page
Changes (For details, refer to main body.)
83
8.2 ADD (Add Byte Data of
Destination and Source to
Destination)
Corrected the explanation.
bit 8 to 15 of A →upper byte of AL
86
8.4 ADDC (Add Byte Data of
Accumulator and Effective
Address with Carry to
Accumulator)
Corrected an explanation.
bit 8 to 15 of A →upper byte of AL
● Operation:
Corrected an explanation.
(ea) →(second operand)
88
8.5 ADDCW (Add Word Data of
Accumulator and Effective
Address with Carry to
Accumulator)
● Operation:
Corrected an explanation.
(ea) →(second operand)
114
8.20 BBcc (Branch if Bit
Condition satisfied)
● Assembler format:
Corrected explanations.
<First operand> →addr16:bp
<First operand> →dir:bp
<First operand> →io:bp
119
8.22 CALL (Call Subroutine)
● Example:
Changed an instruction.
CALL @RW0 →CALL @@RW0
141
8.35 DIV (Divide Word Data by
Byte Data)
Corrected the explanation when the overflow is occur.
AL are destroyed →AL are undefined
142
● Example:
Changed Figure of Example.
EC D8 →00 C7
143
8.36 DIV (Divide Long Word Data
by Word Data)
Corrected the explanation when the overflow is occur.
AL are destroyed →AL are undefined
152
8.41 EXTW (Sign Extend from
Word Data to Long Word
Data)
● Operation:
Corrected an explanation.
bits 16 to 31 of A →AH
178
8.57 LSLW (Logical Shift Word
Data of Accumulator to Left)
Added the following explanations.
The least significant bit of the accumulator (A) is set to
"0".
198
8.68 MOVB (Move Bit Data from
Bit Address to Accumulator)
Added the following descriptions summary sentence.
The value in AL is transferred to AH.
202
8.70 MOVEA (Move Effective
Address to Destination)
● Assembler format:
Corrected operands.
<destination> →A
<destination> →RWi
214
8.77 MOVSWD (Move String
Word with Decrement)
Corrected the instructions name.
MOVSWI →MOVSWD
● Assembler format:
225
8.84 MOVX (Move Byte Data
with Sign Extension from
Source to Accumulator)
● Byte count and cycle count:
Corrected the byte count of "MOVX A,Ri" instruction.
2 →1
xii
Page
Changes (For details, refer to main body.)
235
8.93 NEG (Negate Byte Data of
Destination)
Corrected a summary sentence.
bits 8 to 15 of A →upper byte of AL
252
8.104 POPW (Pop Word Data of
Accumulator from Stack
Memory)
Corrected summary sentences.
bits 16 to 31 for the accumulator (A) →AH
bits 0 to 15 for the accumulator (A) →AL
273
8.116 SCEQ, SCEQI (Scan String
Byte until equal with
Increment)
● Assembler format:
Deleted the following explanation.
(When the address is incremented)
275
8.117 SCEQD (Scan String Byte
until equal with Decrement)
Deleted the following explanation.
(When the address is decremented)
282
8.121 SUB (Subtract Byte Data of
Source from Destination to
Destination)
Corrected a summary sentence.
bits 8 to 15 of A →upper byte of AL
284
8.122 SUBC (Subtract Byte Data
of AL from AH with Carry
to AL)
Corrected a summary sentence.
bits 8 to 15 of the accumulator (A). →upper byte of AL
285
8.123 SUBC (Subtract Byte Data
of Effective Address from
Accumulator with Carry to
Accumulator)
Corrected a summary sentence.
bits 8 to 15 of A →upper byte of AL
289
8.125 SUBDC (Subtract Decimal
Data of AL from AH with
Carry to AL)
Corrected a summary sentence.
bits 8 to 15 of A →upper byte of AL
295
8.129 SWAP (Swap Byte Data of
Accumulator)
● Operation:
Changed an explanation.
296
8.130 SWAPW (Swap Word Data
of Accumulator)
● Operation:
Changed an explanation.
300
8.133 XCH (Exchange Byte Data
of Source to Destination)
● Operation:
Changed an explanation.
302
8.134 XCHW (Exchange Word
Data of Source to
Destination)
Changed an explanation.
311
8.139 ZEXT (Zero Extend from
Byte Data to Word Data)
Corrected a summary sentence.
bits 8 to 15 of the accumulator (A) →upper byte of AL
● Operation:
Corrected an explanation.
Bits 8 to 15 of A →AL[15:8]
8.140 ZEXTW (Zero Extend from
Word Data to Long Word
Data)
Corrected a summary sentence.
bits 16 to 31 of the accumulator (A) →AH
● Operation:
Corrected an explanation.
Bits 16 to 31 of A →AH
312
xiii
Page
Changes (For details, refer to main body.)
320
APPENDIX
APPENDIX B Instruction Lists
(351 Instructions)
Table B-1
Corrected the byte count (#) of "MOVX A,Ri"
instruction.
2 →1
333
Table B-14
Corrected the operand of MOVB instruction.
MOVB addr16:bp →MOVB addr16:bp, A
The vertical lines marked in the left side of the page show the changes.
xiv
CHAPTER 1
CPU
This chapter describes an overview of the
F2MC-16FX CPU core and its sample
configuration.
1.1 Overview of CPU
1.2 Sample Configuration
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CHAPTER 1 CPU
1.1 Overview of CPU
1.1
F2MC-16FX Family
Overview of CPU
The F2MC-16FX CPU core is a 16-bit CPU designed for applications that require
high-speed real-time processing, such as home-use or vehicle-mounted
electronic appliances. The F2MC-16FX instruction set is designed for controller
applications, and is capable of high-speed, highly efficient control processing.
■ Overview of CPU
In addition to 16-bit data, the F2MC-16FX CPU core can process 32-bit data by using an
internal 32-bit accumulator. 32-bit data can be processed with some instructions. Up to 16
MBytes of memory space can be used, which can be accessed by either the linear pointer or
bank method. The instruction set is compatible to F2MC-16LX. The instruction set is
compatible with high-level languages, has a rich set of addressing modes, multiplication and
division instructions, and bit processing. The features of the F2MC-16FX CPU are explained
below.
● Fast execution speed
• Minimum instruction execution time: 16 ns (when operating at an internal frequency of 64
MHz)
• Basic instructions are executed in one cycle
• High speed processing using a 5 stage pipeline
• 8 byte instruction queue
● General purpose registers: 32 banks x 8 words x 16 bits
● Memory space: 16 MBytes, accessed in linear or bank method
● Instruction set optimized for controller applications
• High code efficiency
• Rich data types: Bit, byte, word, long word
• Extended addressing modes: 23 types
• High-precision operation (32-bit length) based on 32-bit accumulator
• Signed and unsigned multiplication and division instructions
● Powerful interrupt functions
• Fast response speed (about 10 clock cycles CLKB)
• Eight priority levels (programmable)
• Non maskable interrupt (NMI)
• DMA transfer can serve interrupt requests (16 channels max.) without involving CPU
2
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F MC-16FX Family
CHAPTER 1 CPU
1.1 Overview of CPU
● Instruction set compatible with high-level language (C)/multitasking
• System stack pointer
• Instruction set symmetry
• Barrel shift instructions
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CHAPTER 1 CPU
1.2 Sample Configuration
1.2
F2MC-16FX Family
Sample Configuration
A sample configuration of the F2MC-16FX CPU and that of the MCU device are
shown.
■ Hardware Configuration of the F2MC-16FX CPU
● Figure 1.2-1 shows the block diagram of the F2MC-16FX CPU.
Figure 1.2-1 Block diagram of F2MC-16FX CPU
Instruction
Fetch stage
Queue
F2MC-16FX CPU
Decode Address
Decode stage 1
Operation
Decode Stage 2
Decode Data
Program Counter
Operation
PCB, PC
Execution stage
ALU
Write Back stage
Processor Status
Accumulator
PS
AH, AL
Stack Pointer
USP, SSP
GeneralPurpose
Register
Ri, RWi, RLi
Bank Register
Direct Page Register
USB, SSB, DTB, ADB
DPR
● CPU Pipeline Operation
To execute most instructions in one clock cycle, the CPU uses a five-stage instruction pipeline.
The pipeline consists of the following stages:
• Instruction fetch (IF): Fetches the instruction from instruction queue.
• Instruction decode 1 (D1): Decodes the instruction and controls address operation.
• Instruction decode 2 (D2): Decodes the instruction and selects operands and data operation.
• Execution (EX): Executes the operation.
• Write back (WB): Writes the operation result to a register or memory location.
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1.2 Sample Configuration
2
F MC-16FX Family
Figure 1.2-2 Instruction Pipeline
CLK
Instruction 1
WB
Instruction 2
EX
WB
Instruction 3
D2
EX
WB
Instruction 4
D1
D2
EX
WB
Instruction 5
IF
D1
D2
EX
WB
IF
D1
D2
EX
Instruction 6
WB
Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead
of instruction B, instruction A always reaches write back stage before instruction B.
The standard instruction execution speed is one instruction per cycle. However, transfer
instructions that involve memory wait, branch instructions and multi-cycle instructions require
more than one cycle to execute. The instruction execution speed also drops if the delivery of
instructions during code fetch is slow.
● Instruction Queue
The CPU has an instruction queue of 8 byte.
The instruction queue is filled by the fetch unit. Prefetch is used on consecutive addresses for
code fetch. The prefetch mechanism removes drawbacks due to the latency of the pipelined
implementation of the CPU and the system bus of the 16FX core.
● Program counter
The program counter bank (PCB, upper 8 bits of the program address) and the program counter
(PC, lower 16 bits of the program address) are controlled by the decode stage 1.
The instruction that is executed next is specified by a 24-bit address {PCB, PC} where the
program counter bank (PCB) and the program counter (PC) are concatenated.
● ALU
The ALU is controlled by decode stage 2. The operation mode of the ALU is selected and the
operands are loaded. The execution of the operation is performed in the next cycle.
The ALU is used for logical and arithmetical operations. Multiplication and division are
included.
● CPU registers and memory access
In the write back stage, the result of the operation is written to CPU registers and/or to a
memory location. All CPU registers except the program counter are assigned to the last
pipeline stage.
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CHAPTER 1 CPU
1.2 Sample Configuration
F2MC-16FX Family
■ Sample Hardware configuration of F2MC-16FX Family MCU
Figure 1.2-3 shows a sample hardware configuration of the MCU device based on the F2MC16FX CPU.
Figure 1.2-3 MCU Device based on the F2MC-16FX Core
User Ports
F2MC-16FX
Boot ROM
CPU
Interrupt
ROM
Controller
(program area)
RAM
(data area)
16FX Core Bus
DMA
Controller
Clock and
Timer
Serial
ADC
Peripheral
Mode Control
Bus Bridge
Peripheral Bus 1
CAN
External Bus
Peripheral
Interface
Bus Bridge
Peripheral Bus 2
F2MC-16FX Core
MCU Device
● Interrupt Controller
The interrupt controller evaluates the priority of incoming interrupt requests (IRQ) and selects
the interrupt number with the highest priority. If accepted, the selected interrupt service is
processed by the CPU. Each hardware IRQ has its own interrupt level register to control its
priority.
● DMA Controller
The DMA controller can also serve IRQs, but without interrupting the actual program
execution of the CPU. This can be used to automate data transfer between peripherals and
memory.
Depending on the device, up to 16 DMA channels are usable. Each DMA channel can select an
IRQ number to be served.
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F MC-16FX Family
CHAPTER 1 CPU
1.2 Sample Configuration
● Clock and Mode Control
This unit has control over the operation mode and monitors correct operation of the device. It
supplies all units with their appropriate clock, depending on the operation mode.
● External Bus Interface
The external bus interface is an optional component. Its availability depends on the
configuration of the specific device.
● Boot ROM
After device initialization by reset, the program counter points to the boot ROM. Then, the
CPU starts the execution of the boot ROM program. After further device initialization the reset
vector is fetched and the boot ROM code branches to user program execution starting at the
reset vector.
● Peripheral Bus Bridge
The peripheral bus bridge acts as an interface between the system bus of the F2MC-16FX core
and the peripheral bus connecting to all other MCU internal peripheral resources.
The peripheral bus bridge synchronizes between core clock and peripheral clock domains.
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CHAPTER 1 CPU
1.2 Sample Configuration
8
F2MC-16FX Family
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CHAPTER 2
MEMORY SPACE
This chapter describes memory spaces in the
F2MC-16FX CPU.
2.1 CPU Memory Space
2.2 Linear Addressing Mode
2.3 Bank Addressing Mode
2.4 Memory Space Divided into Banks and Value in Each
Bank Register
2.5 Data Configuration of and Access to Multi-byte Data in
Memory
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CHAPTER 2 MEMORY SPACE
2.1 CPU Memory Space
2.1
F2MC-16FX Family
CPU Memory Space
All data, programs, and I/O areas managed in the CPU are allocated in its 16Mbyte memory space. The CPU can access these resources using an address
on the 24-bit address bus (see Figure 2.1-1 ).
The F2MC-16FX addressing mode can be classified either as a linear or bank
mode. The linear mode specifies an entire 24-bit address using a instruction.
The bank mode specifies the upper 8 bits of each address using a bank
register, and the remaining 16-bit address using an instruction.
■ CPU Memory Space
Figure 2.1-1 Example of Relationship between the F2MC-16FX System and Memory Map
Program
⎧ FFFFFFH
⎨
⎩
Program area
⎧ 810000H
⎪
⎪
⎨
⎪
⎪
⎩ 800000
Data area
FF8000H
F2MC-16FX
CPU
Data
Interrupt
H
Peripheral
circuit
General-purpose
port
[Device]
10
⎧ 0000C0H
⎨
⎩
⎧ 0000B0H
⎨
⎩
000020H
⎧
⎨
⎩ 000000
Interrupt controller
Peripheral circuit
General-purpose port
H
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CHAPTER 2 MEMORY SPACE
2.2 Linear Addressing Mode
2
F MC-16FX Family
2.2
Linear Addressing Mode
The linear addressing mode of the F2MC-16FX specifies an entire 24-bit
address using an instruction.
■ Linear Addressing Mode
The linear addressing mode of the F2MC-16FX specifies an entire 24-bit address using an
instruction. The address mode of the F2MC-16FX is determined according to the specification
of the effective address or instruction code (implied) of an instruction.
The linear addressing mode can operate in two different ways. In the first way, an operand of
an instruction directly specifies an entire 24-bit address. In the second way, the lower 24-bit of
a 32-bit general-purpose register is referred as an address (see Figure 2.2-1 ).
Figure 2.2-1 Examples of Generating an Address in the Linear Addressing Mode
Example 1: 24-bit Operand Specification in the Linear Addressing Mode
JMPP 123456H
17452DH
Previous content of
program counter plus
program bank
17
452D
Latest content of
program counter plus 12
program bank
3456
JMPP 123456H
123456H
Next instruction
Example 2: Indirect Addressing Based on 32-bit Register in the Linear Addressing Mode
MOV A @RL1+7
Previous content
of the AL
XXXX
090700H
3A
+7
240906F9
RL1
(Upper 8 bits are ignored.)
Latest content
of the AL
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CHAPTER 2 MEMORY SPACE
2.3 Bank Addressing Mode
2.3
F2MC-16FX Family
Bank Addressing Mode
The bank addressing mode of the F2MC-16FX specifies the upper 8 bits of an
address using a bank register for use, and the remaining 16 bits using an
instruction.
■ Bank Addressing Mode
In the bank addressing mode, the 16-Mbyte memory space is divided into 256 banks of 64Kbyte, and the corresponding bank to each space is specified by the following 4 bank registers.
● Program counter bank register (PCB)
A 64-Kbyte bank specified using the PCB register is called a program (PC) space. It is used to
hold mainly instruction codes, vector tables, and immediate data.
● Data bank register (DTB)
A 64-Kbyte bank specified using the DTB register is called a data (DT) space. It is used to
hold mainly readable/writable data and control/data registers for internal and external
resources.
● User stack bank register (USB) and system stack bank register (SSB)
A 64-Kbyte bank specified using the USB or SSB register is called a stack (SP) space. It is
accessed when the execution of a push or pop instruction or interrupt handling is performed to
save register contents and a stack access occurs. And which to be used, the USB or SSB
register, is determined according to the stack flag (S) in the condition code register (CCR).
● Additional data bank register (ADB)
A 64-Kbyte bank specified using the ADB register is called an additional (AD) space. It is
used to hold mainly data overflowing from the DT space.
Each instruction is assigned with one of the default spaces by each addressing listed in Table
2.3-1 to improve instruction code efficiency.
Table 2.3-1 Default Spaces
Default space
12
Addressing
Program space
PC-indirect, program access, branch type
Data space
@A, addr16, dir, or addressing using @RW0, @RW1, @RW4, or @RW5
Stack space
Addressing using PUSHW, POPW, @RW3, @RW7, or @SP
Additional space
Addressing using @RW2 or @RW6
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2.3 Bank Addressing Mode
2
F MC-16FX Family
If a space other than a default space is used, an arbitrary bank space corresponding to a prefix
code can be accessed by specifying the prefix code before the instruction.
Table 2.3-2 lists bank select prefixes and the memory space selected using each prefix.
Table 2.3-2 Bank Selection Prefix
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
System or user stack space depending on the contents of the selected
stack flag (S)
The DTB, USB, SSB, and ADB registers are initialized to 00H at a reset. The PCB register is
initialized to FFH at a reset. After a reset, the data, stack, and additional spaces are allocated in
bank 00H (000000H to 00FFFFH), and the program space is allocated in bank FFH (FF0000H to
FFFFFFH).
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CHAPTER 2 MEMORY SPACE
2.4 Memory Space Divided into Banks and Value in Each Bank
Register
F2MC-16FX Family
Memory Space Divided into Banks and Value in
Each Bank Register
2.4
Figure 2.4-1 shows an example of a memory space divided into banks and a
value in each register bank.
■ Memory Space Divided into Banks and Values in Each Register Bank
Figure 2.4-1 Example of the Physical Addresses of Each Space
FFFFFFH
Program space
FF0000H
FFH
: PCB (program counter bank register)
B3H
: ADB (additional data bank register)
B3FFFFH
Additional space
Physical Address
B30000H
92FFFFH
User stack space
920000H
92H
: USB (user stack bank register)
68H
: DTB (data bank register)
4BH
: SSB (system stack bank register)
68FFFFH
Data space
680000H
4BFFFFH
System stack space
4B0000H
000000H
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CHAPTER 2 MEMORY SPACE
2.5 Data Configuration of and Access to Multi-byte Data in
Memory
2
F MC-16FX Family
2.5
Data Configuration of and Access to Multi-byte Data
in Memory
Multi-byte data is written to memory starting at the lowest address. If the multibyte data is 32-bit long, the lower 16 bits are written to memory first and then
upper 16 bits.
■ Multi-byte Data Layout in a Memory Space
Multi-byte data is written to memory starting at the lowest address. If the multi-byte data is
32-bit length, the lower 16 bits are written to memory first and then upper 16 bits.
If a reset signal is input immediately after the low-order data is written to memory, the highorder data may not be written. To keep the data in integrity, it is necessary to input a reset
signal after the high-order data is written.
Figure 2.5-1 shows the layout of multi-byte data in memory. The lower 8 bits are placed at
address n, the next lower 8 bits are placed at address n + 1, and the next lower 8 bits are placed
at address n + 2, and so on.
Figure 2.5-1 Multi-byte Data Layout in Memory
MSB
01010101
H
LSB
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
L
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CHAPTER 2 MEMORY SPACE
2.5 Data Configuration of and Access to Multi-byte Data in
Memory
F2MC-16FX Family
■ Access to Multi-byte Data
When multi-byte data is accessed, it is assumed that all parts of the multi-byte data are within a
single bank. To put it another way, an instruction accessing multi-byte data assumes that an
address that follows address FFFFH is 0000H in the same bank as for FFFFH.
Figure 2.5-2 shows an execution example of an instruction accessing multi-byte data.
Figure 2.5-2 Execution Example of an Instruction (MOVW A, 080FFFFH)
Accessing Multi-byte Data
Higher address
80FFFFH
AL before execution
??
??
AL after execution
23H 01H
01H
·
·
·
800000H
23H
Lower address
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CHAPTER 3
DEDICATED REGISTER
The F2MC-16FX CPU registers are classified
into two types: dedicated registers and generalpurpose registers. This chapter describes the
dedicated registers of the F2MC-16FX CPU. The
dedicated registers are dedicated internal
hardware of the CPU, and they have specific
use defined by the CPU architecture. These
registers can be accessed without using an
address. The register operations are defined by
specific instructions.
3.1 Structure of the Dedicated Registers
3.2 Accumulator (A)
3.3 User Stack Pointer (USP) and System Stack Pointer
(SSP)
3.4 Processor Status (PS)
3.5 Program Counter (PC)
3.6 Direct Page Register (DPR)
3.7 Bank register (PCB, DTB, ADB, USB, SSB)
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CHAPTER 3 DEDICATED REGISTER
3.1 Structure of the Dedicated Registers
3.1
F2MC-16FX Family
Structure of the Dedicated Registers
The F2MC-16FX CPU has the following dedicated registers:
• Accumulator (A=AH:AL):
Two 16-bit accumulators (can be used as a single 32-bit accumulator)
• User stack pointer (USP):
16-bit user stack pointer
• System stack pointer (SSP):
16-bit system stack pointer
• Processor status (PS):
16-bit register indicating the system status
• Program counter (PC):
16-bit register holding the address of the next instruction to be executed
• Program counter bank register (PCB):
8-bit register indicating the program counter bank
• Data bank register (DTB):
8-bit register indicating the data bank
• User stack bank register (USB):
8-bit register indicating the user stack bank
• System stack bank register (SSB):
8-bit register indicating the system stack bank
• Additional data bank register (ADB):
8-bit register indicating the additional data bank
• Direct page register (DPR):
8-bit register indicating the page for direct access
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CHAPTER 3 DEDICATED REGISTER
3.1 Structure of the Dedicated Registers
2
F MC-16FX Family
Figure 3.1-1 shows a diagram of the dedicated registers.
Figure 3.1-1 Dedicated registers
AL
AH
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program counter bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
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CHAPTER 3 DEDICATED REGISTER
3.2 Accumulator (A)
3.2
F2MC-16FX Family
Accumulator (A)
The accumulator (A) consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer
data.
■ Accumulator (A)
The Accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL). The
Accumulator (A) is used as a temporary storage for operation results and transfer data. During
32-bit data processing, AH and AL are used together. Only AL is used for word processing in
16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure
3.2-1 and Figure 3.2-2).
The data stored in the Accumulator (A) can be operated upon with the data in memory or
registers (Ri, Rwi, or RLi). In the same manner as with the F2MC-16LX, when a word or
shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH
(data preservation function). The data preservation function and operation between AL and AH
help to improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zeroextended and stored as a 16-bit data item in AL. The data in AL can be handled either as word
or byte.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order
eight bits of AL before the operation are ignored. After the operation the high-order eight bits
become zero.
The Accumulator (A) is not initialized by a reset. The Accumulator (A) holds an undefined
value immediately after a reset.
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CHAPTER 3 DEDICATED REGISTER
3.2 Accumulator (A)
2
F MC-16FX Family
Figure 3.2-1 Example of a 32-bit data transfer
MSB
MOVL A, @RW1+6
Previous content
of the A register
XXXXH
XXXXH
DTB
A6H
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
Latest content
of the A register
8F74H
2B52H
AH
AL
Figure 3.2-2 Example of AL-AH transfer by means of data preservation
MSB
MOVW A, @RW1+6
Previous content
of the A register
XXXXH
1234H
DTB
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
A6H
+6
Latest content
of the A register
CM44-00203-3E
1234H
2B52H
AH
AL
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CHAPTER 3 DEDICATED REGISTER
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
3.3
F2MC-16FX Family
User Stack Pointer (USP) and System Stack Pointer
(SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for
saving and restoring data when a push/pop instruction or subroutine is
executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring
data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers
are used by stack instructions.
The USP register is enabled when the stack flag (S) in the processor status (PS) is “0”, and the
SSP register is enabled when the S flag is “1” (see Figure 3.3-1). Since the S flag is set when
an interrupt is accepted, register values are always saved in the memory area indicated by the
SSP register during interrupt processing. The SSP register is used for stack processing in an
interrupt routine, while the USP register is used for stack processing outside an interrupt
routine. If the stack space is not divided, use only the SSP register.
During stack processing, the high-order eight bits of an address are indicated by system stack
bank register (SSB) for the SSP register or user stack bank register (USB) for the USP register.
The USP and SSP registers are not initialized by a reset. Instead, the values of these registers
are undefined.
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F MC-16FX Family
CHAPTER 3 DEDICATED REGISTER
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
Figure 3.3-1 Stack manipulation instruction and stack pointer
MSB
Example 1 PUSHW A when the S flag is "0"
Before execution
AL
S flag
After execution
AL
C6F326 H
LSB
A624 H
USB
C6 H
USP
F328 H
0
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F326 H
0
SSB
56 H
SSP
1234 H
C6F326 H
A6 H
24 H
A624 H
USB
C6 H
USP
F328 H
561232 H
XX
XX
1
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F328 H
561232 H
A6 H
24 H
1
SSB
56 H
SSP
1232 H
XX
XX
User stack is used because
the S flag is "0".
Example 2 PUSHW A when the S flag is "1"
AL
AL
System stack is used because
the S flag is "1".
Note:
Specify an even-numbered address in the stack pointer whenever possible. An oddnumbered address will be cause of drawback in stack performance.
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CHAPTER 3 DEDICATED REGISTER
3.4 Processor Status (PS)
3.4
F2MC-16FX Family
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 3.4-1, the high-order byte of the PS register consists of a register bank
pointer (RP) and an interrupt level mask (ILM). The RP indicates the start address of a register
bank. The low-order byte of the PS register is a condition code register (CCR), containing the
flags to be set or reset depending on the results of instruction execution or interrupt
occurrences.
Figure 3.4-1 Processor status (PS) structure
bit 15
PS
24
13 12
ILM
8 7
RP
0
CCR
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CHAPTER 3 DEDICATED REGISTER
3.4 Processor Status (PS)
2
F MC-16FX Family
■ Condition Code Register (CCR)
Figure 3.4-2 shows the diagram of the condition code register (CCR) configuration.
Figure 3.4-2 Condition code register (CCR) configuration
bit
7
6
5
4
3
2
1
0
P
I
S
T
N
Z
V
C
PS: CCR
0
0
1
0
0
0
0
0
initial value after reset
1
0
1
X
X
X
X
X
value after Boot ROM execution
● P: Privileged mode flag
The privileged mode flag (P) indicates user or system mode of CPU status.
When the P flag is "1", CPU is in the user mode.
When the P flag is "0", CPU is in the privileged mode.
The P flag is cleared by a reset. However, the P flag will be set during execution of the Boot
ROM code.
Only NMI, HW-INT9 (EDSU) and DSU interrupts will clear the P flag and disable all other
hardware interrupts. If the P flag is cleared, the interrupt level mask (ILM) defines system
interrupt levels of the privileged mode (P0 to P7). These interrupt levels have higher priority
than any ILM register setting in user mode (U0 to U7).
The P flag can be set by dedicated instructions (OR CCR, #imm8 / POPW PS) or by restoring
the processor status (RETI / JCTX @A). Restoring in the privileged mode (P=0) is not
accepted, if the P flag has been "1" before.
● I: Interrupt enable flag
Interrupts other than software interrupts are enabled when the I flag is "1" and are disabled
when the I flag is "0". The I flag is cleared by a reset.
● S: Stack flag
When the S flag is "0", USP is enabled as the stack pointer. When the S flag is "1", SSP is
enabled as the stack pointer. The S flag is set by an interrupt reception or a reset.
● T: Sticky bit flag
A value of "1" is set in the T flag when there is at least one "1" in the data shifted out from the
carry after execution of a logical right/arithmetic right shift instruction, otherwise, "0" is set in
the T flag. In addition, "0" is set in the T flag when the shift amount is zero.
● N: Negative flag
The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.
● Z: Zero flag
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
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CHAPTER 3 DEDICATED REGISTER
3.4 Processor Status (PS)
F2MC-16FX Family
● V: Overflow flag
The V flag is set when an overflow of a signed value occurs as a result of operation execution
and is otherwise cleared.
● C: Carry flag
The C flag is set when a carry-up or carry-down from the MSB or LSB occurs as a result of
operation execution, and is otherwise cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers and the
internal RAM addresses. Specifically, the RP register indicates the first memory address of the
currently used register bank in the following conversion expression: [00180H + (RP) × 10H].
The RP register consists of five bits, and can take a value between 00H and 1FH. Register banks
can be allocated at addresses from 000180H to 00037FH in memory.
Figure 3.4-3 Register bank pointer (RP)
bit
15
14
13
12
11
10
9
8
B4
B3
B2
B1
B0
0
0
0
0
0
RP
initial value
The RP register is initialized to all zeroes by a reset. An instruction may transfer an eight-bit
immediate value to the RP register; however, only the low-order five bits of that data are used.
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CHAPTER 3 DEDICATED REGISTER
3.4 Processor Status (PS)
2
F MC-16FX Family
■ Interrupt Level Mask (ILM)
The Interrupt Level Mask (ILM) consists of three bits, indicating the CPU interrupt masking
level. An interrupt request is accepted only when the priority of the interrupt is higher than that
indicated by the ILM register and the privileged mode flag (P).
Highest priority interrupt is level P0 and lowest priority is level U7. Therefore, for an interrupt
to be accepted, its level value must be smaller than the current ILM register value (see Figure
3.4-4 ). In addition, the P flag has to be considered. When an interrupt is accepted, the level
value of that interrupt is set in the P flag and ILM register. Thus, an interrupt of the same or
lower priority cannot be accepted subsequently.
Figure 3.4-4 Interrupt level (ILM)
bit
15
14
13
12
11
10
9
8
ILM2
ILM1
ILM0
1
0
0
initial value after reset
0
0
0
value after Boot ROM execution
PS: ILM
ILM is initialized to 100B by a reset. However, during execution of the Boot ROM program
ILM is set to 000B.
An instruction may transfer an eight-bit immediate value to the ILM register, but only the loworder three bits of that data are used (MOV ILM, #imm8 / POPW PS / RETI / JCTX @A). If
CPU is in user mode (P=1), any ILM register change is possible. If CPU is privileged mode
(P=0), an ILM register change is only accepted, if the new value defines a user level U0 to U7
(with P=1) or if the privileged level (P0 to P7) is increased. The lower levels of the privileged
mode P0 to P7 can not be reached by execution of an instruction from a higher level. Writing
"0" to the P flag and reducing the level with P=0 is only possible by NMI, HW-INT9 or a DSU
interrupt.
Note:
The P flag can be understood as bit extension of the ILM register. Then it defines the
most significant bit of the interrupt level mask {P, ILM}.
After initialization with reset the CPU is in level P4. This disables all interrupts, including
NMI, except for the DSU. After execution of the Boot ROM program the CPU is in level U0.
Peripheral interrupts are disabled.
All privileged mode levels P0 to P7 are locked against entering or decreasing the level by an
instruction. The levels P0 to P7 can only be increased. This protects the operation of HWINT9, NMI and DSU operation. Only DSU can interrupt the NMI or mask its acceptance
during a debug session.
The user levels U0 to U7 are backward compatible to F2MC-16LX interrupt levels 0 to 7. The
P flag is not writable in a user level.
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CHAPTER 3 DEDICATED REGISTER
3.4 Processor Status (PS)
F2MC-16FX Family
Table 3.4-1 Levels indicated by the privileged mode flag (P) and interrupt level mask (ILM)
Level
P flag
ILM value
Acceptable interrupt level
P0
0
0
none
Interrupts disabled
P1
0
1
Level < P1
Interrupts disabled
P2
0
2
Level < P2
Interrupts disabled
P3
0
3
Level < P3
DSU
P4
0
4
Level < P4
DSU
P5
0
5
Level < P5
NMI, DSU
P6
0
6
Level < P6
NMI, DSU
P7
0
7
Level < P7
HW-INT9, NMI, DSU
U0
1
0
Level < U0
User Interrupts disabled
U1
1
1
Level < U1
User level 0
U2
1
2
Level < U2
User level 0, 1
U3
1
3
Level < U3
User level 0 to 2
U4
1
4
Level < U4
User level 0 to 3
U5
1
5
Level < U5
User level 0 to 4
U6
1
6
Level < U6
User level 0 to 5
U7
1
7
Level < U7
User level 0 to 6
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HW-INT9,
NMI, DSU
CM44-00203-3E
CHAPTER 3 DEDICATED REGISTER
3.5 Program Counter (PC)
2
F MC-16FX Family
3.5
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the
memory address of an instruction code to be executed by the CPU.
■ Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address
of an instruction code to be executed by the CPU. The high-order eight bits of the address are
indicated by the program counter bank register (PCB).
The PC register is updated by a branch instruction, subroutine call instruction, interrupt or
reset. Within a linear program segment, the PC is incremented by the number of bytes of the
last instruction.
The PC register can also be used as a base pointer for operand access.
Figure 3.5-1"Program counter" shows the program counter.
Figure 3.5-1 Program counter
PCB
FE H
PC
ABCD H
Next instruction to be executed
FEABCD H
The reset address is fixed to the Boot ROM program start address of 0F:FC00H. At reset, the
PC register is initialized to FC00H and the PCB register is initialized to 0FH.
In external vector mode a value specified by the reset vector on address FF:FFDCH is loaded
when leaving the Boot ROM code execution. In internal vector mode the PCB and PC registers
are loaded with fixed values defined by the product.
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CHAPTER 3 DEDICATED REGISTER
3.6 Direct Page Register (DPR)
3.6
F2MC-16FX Family
Direct Page Register (DPR)
The direct page register (DPR) specifies bits 8 to 15 of the operand address for
direct addressing instructions.
■ Direct Page Register (DPR)
The DPR register specifies bits 8 to 15 of the instruction operands in direct addressing mode as
shown in Figure 3.6-1.
Figure 3.6-1 Generating a physical address in direct addressing mode
DTB register
DPR register
Direct address during instruction
αααααααα
ββββββββ
γγγγγγγγ
LSB
MSB
24-bit physical
address
ααααααααββββββββγγγγγγγγ
The DPR register is eight bits long, and is initialized to 01H by a reset. The DPR register can be
read or written to by an instruction.
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CHAPTER 3 DEDICATED REGISTER
3.7 Bank register (PCB, DTB, ADB, USB, SSB)
2
F MC-16FX Family
3.7
Bank register (PCB, DTB, ADB, USB, SSB)
Each bank register indicates a memory bank where a program space, data
space, user stack space or additional data space is allocated.
■ Bank Register
All bank registers are one byte long. Each bank register (PCB, DTB, USP, SSP, ADB)
indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated.
Bank registers other than PCB can be read and written to. PCB can be read but cannot be
written to. The PCB register is updated upon the JMPP or CALLP instruction, branching to the
entire 16 MByte space, upon the RETP or RETI instruction or upon an interrupt.
For details of the operation of bank registers, see section "2.3 Bank Addressing Mode".
● Program counter bank register (PCB)
Initial value: 0FH after reset, and later a value from reset vector at user program start.
● Data bank register (DTB)
Initial value: 00H.
● User stack bank register (USB)
Initial value: 00H.
● System stack bank register (SSB)
Initial value: 00H.
● Additional data bank register (ADB)
Initial value: 00H.
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CHAPTER 3 DEDICATED REGISTER
3.7 Bank register (PCB, DTB, ADB, USB, SSB)
32
F2MC-16FX Family
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CM44-00203-3E
CHAPTER 4
GENERAL-PURPOSE
REGISTERS
The registers of the F2MC-16FX can be grouped
into two major categories: dedicated registers
in the CPU and general-purpose registers
allocated in memory.
This chapter describes the F2MC-16FX generalpurpose registers. These registers are
allocated in a RAM in address space of the
CPU. Similarly to the dedicated registers, the
general-purpose registers can be accessed
without specifying their address. However, the
user can specify the purpose for which they are
used in the same manner as for ordinary
memory.
4.1 Register Banks in RAM
4.2 Calling General-purpose Registers in RAM
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CHAPTER 4 GENERAL-PURPOSE REGISTERS
4.1 Register Banks in RAM
4.1
F2MC-16FX Family
Register Banks in RAM
Each register bank consists of 8 words (16 bytes). They can be used as
general-purpose registers (byte registers R0 to R7, word registers RW0 to RW7,
and long word registers RL0 to RL3) for performing various types of operations
and specifying pointers. RL0 to RL3 can be used also as a linear pointer to
gain direct access to all spaces in memory.
■ Register Banks in RAM
Table 4.1-1 lists the function of each register, and Table 4.1-2 shows relationships between the
registers.
Table 4.1-1 Functions of Each Register
34
Register name
Function
R0 to R7
Used to hold an operand in various types of instructions.
Note: R0 is also used as a barrel shift counter and a counter of normalize
instruction.
RW0 to RW7
Used to hold a pointer.
Used to hold an operand in various types of instructions.
Note: RW0 is used also as a string instruction counter.
RL0 to RL3
Used to hold a long pointer.
Used to hold an operand in various types of instructions.
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CHAPTER 4 GENERAL-PURPOSE REGISTERS
4.1 Register Banks in RAM
2
F MC-16FX Family
Table 4.1-2 Relationship between Registers
Address
Byte register
Word register
Long word register
000180H + RP × 10H + 0
RW0
000180H + RP × 10H + 1
RL0
000180H + RP × 10H + 2
RW1
000180H + RP × 10H + 3
000180H + RP × 10H + 4
RW2
000180H + RP × 10H + 5
RL1
000180H + RP × 10H + 6
RW3
000180H + RP × 10H + 7
000180H + RP × 10H + 8
R0
000180H + RP × 10H + 9
R1
000180H + RP × 10H + 10
R2
000180H + RP × 10H + 11
R3
000180H + RP × 10H + 12
R4
000180H + RP × 10H + 13
R5
000180H + RP × 10H + 14
R6
000180H + RP × 10H + 15
R7
CM44-00203-3E
RW4
RL2
RW5
RW6
RL3
RW7
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CHAPTER 4 GENERAL-PURPOSE REGISTERS
4.2 Calling General-purpose Registers in RAM
4.2
F2MC-16FX Family
Calling General-purpose Registers in RAM
For general-purpose registers, the register bank pointer (RP) is used to specify
where in internal RAM between 000180H and 00037FH the register bank
currently in use is allocated.
■ Calling General-purpose Registers in RAM
The general-purpose registers are allocated in internal RAM between 000180H and 00037FH
(in maximum configuration). The register bank pointer (RP) is used to indicate where in
internal RAM between 000180H and 00037FH the register bank currently in use is allocated.
Each bank contains the following 3 different registers. These registers are not independent of
one another. Instead, they have the relationships shown in Figure 4.2-1 .
• R0 to R7: 8-bit general-purpose registers
• RW0 to RW7:16-bit general-purpose registers
• RL0 to RL3: 32-bit general-purpose registers
Figure 4.2-1 General-purpose Registers
000180H + RP × 10H
Start address of a
general-purpose
register
16 bits
RW0
RW1
RW2
RW3
Lower order
Higher order
LSB
R1
R3
R5
R7
R0
R2
R4
R6
RW4
RW5
RW6
RW7
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
MSB
RL0
RL1
RL2
RL3
The relationships among the high- and low-order bytes in word registers (RW4 to RW7) and
byte registers (R0 to R7) are represented using the following expression:
RW (i + 4) = R (i × 2 + 1) × 256 + R (i × 2) [where i = 0 to 3]
The relationships among the high- and low-order bytes in long registers (RL0 to RL3) and
word registers (RW0 to RW7) are represented using the following expression:
RL (i) = RW (i × 2 + 1) × 65536 + RW (i × 2) [where i = 0 to 3]
For example, if the data in R1 and the data in R0 are arranged as high- and low-order bytes,
respectively, the resulting data equals the data (2 bytes) in RW4.
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CHAPTER 5
PREFIX CODES
The operation of an instruction can be modified
by prefixing it with prefix code. The following 3
types of prefix codes are available.
• Bank select prefix
• Common register bank prefix
• Flag change inhibit prefix code
This chapter describes these prefixes.
5.1 Bank Select Prefix
5.2 Common Register Bank Prefix (CMR)
5.3 Flag Change Inhibit Prefix Code (NCC)
5.4 Constraints Related to the Prefix Codes
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CHAPTER 5 PREFIX CODES
5.1 Bank Select Prefix
5.1
F2MC-16FX Family
Bank Select Prefix
Placing a bank select prefix before an instruction enables selecting the
memory space accessed by the instruction regardless of what the current
addressing mode is.
■ Bank Select Prefix
The memory space of data to be accessed is determined according to the addressing mode.
Placing a bank select prefix before an instruction enables to select the memory space accessed
by the instruction regardless of what the current addressing mode is. Table 5.1-1 lists the bank
select prefixes and the memory space selected according to each bank select prefix.
Table 5.1-1 Bank Select Prefixes
Bank select prefix
Memory space to be selected
PCB
Program counter space
DTB
Data space
ADB
Additional space
SPB
System or user stack space depending on the state of the stack flag
The effect of the prefix codes is different for the following instructions.
• Transfer instructions (I/O access)
MOV A,io
MOVW io,A
MOV io, A
MOV io,#imm8
MOVX A,io
MOVW A,io
MOVW io,#imm16
These instructions access the I/O space regardless of whether there is a prefix before them.
• Branch instruction
RETI
The system stack bank register (SSB) is used regardless of whether there is a prefix before
the branch instruction.
• Bit manipulation instructions (I/O access)
MOVB A,io:bp
MOVB io:bp,A
SETB io:bp
CLRB io:bp
BBC io:bp,rel
BBS io:bp,rel
WBTC
WBTS
The I/O space is accessed regardless of whether there is a prefix before those instructions.
• String manipulation instructions
MOVS
FILS
MOVSW
FILSW
SCEQ
SCWEQ
A bank register specified in the operand is used regardless of whether there is a prefix before
these instructions.
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CHAPTER 5 PREFIX CODES
5.1 Bank Select Prefix
2
F MC-16FX Family
• Other types of control instructions (stack manipulation)
PUSHW
POPW
POPW PS
LINK
UNLINK
The system stack bank register (SSB) or user stack bank register (USB) is used depending on
the state of the stack flag (S), regardless of whether there is a prefix before these instructions.
In the following cases, the prefix of an instruction affects not only that instruction but also an
instruction that follows it.
• Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
The operations of these instructions are performed normally. The prefix of each of these
instructions affects not only the instructions but also an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects
not only that instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES
5.2 Common Register Bank Prefix (CMR)
5.2
F2MC-16FX Family
Common Register Bank Prefix (CMR)
Placing a common register bank prefix (CMR) before an instruction accessing a
register bank enables to change that the instruction is to access only the
registers in a common bank (register bank selected when RP = 0) allocated
between 000180H and 00018FH, regardless of what the current value of the
register bank pointer (RP) is.
■ Common Register Bank Prefix (CMR)
To make data exchange among tasks easier, it is necessary to use a method that can access a
certain specified register bank relatively easily no matter what value the register bank pointer
(RP) holds. To meet this requirement, the F2MC-16FX has a register bank that can be used by
all tasks in common. It is called a common bank. The common bank is allocated in memory
between address 000180H and 00018FH. It is selected when the RP register contains a value of
"0".
Placing the common register bank prefix (CMR) before an instruction accessing a register bank
enables to change that the instruction is to access only the registers in a common bank
regardless of what the current value of the RP register is.
The effect of the prefix codes is different for the following instructions.
• String instructions
MOVS
FILSW
NOVSW
SCEQ
FILS
If an interrupt is requested during execution of a string manipulation instruction attached
with a prefix code, the prefix becomes ineffective for the string manipulation instruction after
a return is made from the interrupt handling routine, possibly resulting in a malfunction. Do
not place the CMR prefix before these string manipulation instructions.
• Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
POPW PS
The operations of these instructions are performed normally. The prefix of each of these
instructions affects not only the instructions but also an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM, #imm8
The operation of the instruction is performed normally. The prefix of the instruction affects
not only that instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES
5.3 Flag Change Inhibit Prefix Code (NCC)
2
F MC-16FX Family
5.3
Flag Change Inhibit Prefix Code (NCC)
Placing the flag change inhibit prefix code (NCC) before an instruction inhibits
flags from changing during execution of the instruction.
■ Flag Change Inhibit Prefix Code (NCC)
The flag change inhibit prefix code (NCC) is used to suppress undesired changes to flags.
Placing the NCC prefix before an instruction inhibits flags from changing during execution of
the instruction.
The effect of the prefix codes is different for the following instructions.
• Branch instructions
INT #vct8
INT9
INTP addr24
RETI
INT addr16
These instructions change the flags in the condition code register (CCR) regardless of
whether there is a prefix before them.
• String instructions
SCEQ
SCWEQ
FILS
FILSW
Placing a NCC prefix before the string instructions listed above is ignored. Flags in the
condition code register (CCR) are changing according to the instruction specifications,
regardless of a NCC prefix is specified or not.
• Another type of control instruction (task switching)
JCTX @A
This instruction changes the flags in the condition code register (CCR) regardless of whether
there is a prefix before it.
• Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
POPW PS
These instructions change the flags in the CCR register regardless of whether there is a prefix
before them. The prefix of each of these instructions affects not only the instructions but
also an instruction that follows them.
• Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects
not only that instruction but also an instruction that follows it.
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CHAPTER 5 PREFIX CODES
5.4 Constraints Related to the Prefix Codes
5.4
F2MC-16FX Family
Constraints Related to the Prefix Codes
If a prefix code is placed before an instruction where interrupt and hold
requests are inhibited, the effect of the prefix code lasts until an instruction
where neither an interrupt nor hold request is inhibited appears for the first
time.
If a prefix is followed by conflicting prefix codes, the last one is valid.
■ Relationships between Instructions Rejecting Interrupt Requests and Prefix
Codes
The following 10 instructions/prefix codes reject interrupt and hold requests.
• MOV ILM,#imm8
• AND CCR,#imm8
• OR CCR,#imm8
• POPW PS
• PCB
• ADB
• NCC
• DTB
• SPB
• CMR
If an interrupt or hold request is issued during execution of any of the above instructions, the
request is accepted only after any instruction not listed above appears for the first time after
that instruction and is executed, as shown in Figure 5.4-1 .
Figure 5.4-1 Instructions Rejecting Interrupt and Hold Requests
Instructions rejecting interrupt and hold requests
••••••••
Interrupt request issued
(a)
•••
(a): Ordinary instruction
Interrupt accepted
If a prefix code is placed before an instruction rejecting interrupt and hold requests, its effect
lasts until an instruction other than instructions rejecting interrupt and hold requests appears for
the first time after the prefix code and is executed, as shown in Figure 5.4-2 .
Figure 5.4-2 Instructions Rejecting Interrupt and Hold Requests and Prefix Code
Instructions rejecting interrupt and hold requests
MOV A,FFH
NCC
CCR: XXX10XX
MOV ILM,#imm8
••••
ADD A,01H
CCR: XXX10XX
The NCC protects the
CCR from changing.
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CHAPTER 5 PREFIX CODES
5.4 Constraints Related to the Prefix Codes
2
F MC-16FX Family
■ If Two or More Prefix Codes Appear in Succession
If a prefix is followed by conflicting prefix codes, the last one is valid (see Figure 5.4-3 ).
Figure 5.4-3 Consecutive Prefix Codes
Prefix codes
•••••
ADB
DTB
PCB
ADD A,01H
••••
The PCB prefix code is valid for this instruction.
The term "conflicting prefix codes" indicates PCB, ADB, DTB, and SPB in the above figure.
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CHAPTER 5 PREFIX CODES
5.4 Constraints Related to the Prefix Codes
44
F2MC-16FX Family
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 6
INTERRUPTS
This chapter describes the interrupt functions
and operations.
6.1 Overview of Interrupts
6.2 Interrupt Vector
6.3 Interrupt Control Registers (ICR)
6.4 Non Maskable Interrupt (NMI)
6.5 Interrupt Flow
6.6 Hardware Interrupts
6.7 Software Interrupts
6.8 Multiple interrupts
6.9 Exceptions
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CHAPTER 6 INTERRUPTS
6.1 Overview of Interrupts
6.1
F2MC-16FX Family
Overview of Interrupts
The F2MC-16FX has interrupt functions that terminate the currently executed
program and transfer control to another specified program when a specific
event occurs. There are four types of interrupt functions:
• Hardware interrupt: Interrupt processing due to an internal resource event
• Software interrupt: Interrupt processing due to a software event (instruction)
• Exception: Handling of an operation exception
• DMA: Data transfer without CPU interaction due to an internal resource event.
■ Hardware Interrupts
A hardware interrupt is activated by an interrupt request from an internal resource. A hardware
interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an
internal resource are set.
● Specifying an interrupt level
An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use
the level setting bits (IL0, IL1, and IL2) in the interrupt control register (ICR).
For each hardware interrupt its own interrupt level (IL) can be specified. Access to a dedicated
IL can be done by setting the index IX. Both IX and IL are accessible through the interrupt
control register (ICR).
● Masking a hardware interrupt request
A hardware interrupt request can be masked by using the interrupt enable flag (I) and the
interrupt level mask (ILM). The interrupt is executed only, when the I flag is set and the value
of the interrupt level (IL) is smaller than the interrupt level mask (ILM). In addition the
privileged mode flag (P) has to be set for hardware interrupt acceptance. The P flag, I flag and
ILM register are parts of the processor status (PS) of the CPU.
When an unmasked interrupt request occurs, the CPU saves 12 bytes of data that consists of
registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area indicated by the system
stack bank register (SSB) and system stack pointer (SSP).
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CM44-00203-3E
2
F MC-16FX Family
CHAPTER 6 INTERRUPTS
6.1 Overview of Interrupts
■ Software Interrupts
Interrupts requested by executing the INT instruction are software interrupts. An interrupt
request by the INT instruction does not have an interrupt request or enable flag. An interrupt
request is issued always by executing the INT instruction.
No interrupt level is assigned to the INT instruction. Therefore, the ILM register is not updated
when the INT instruction is used. Instead, the interrupt enable flag (I) is cleared and the
continuing interrupt requests are suspended.
■ Exceptions
Following software exceptions can be processed:
• Undefined instruction
• INT9
• INTE (only available on the EVA device)
Following hardware exceptions can be processed:
• NMI
• HW-INT9 (embedded debug support)
• DSU break factors (only available on the EVA device)
Exception processing is basically the same as interrupt processing. When an exception is
detected during instruction execution, exception processing is performed. In general, exception
processing occurs as a result of an unexpected operation. Therefore, use exception processing
only for debugging programs or for activating recovery software in an emergency case.
■ Direct Memory Access (DMA)
● DMA Function
F2MC-16FX offers a DMA function to automatically transfer data between peripheral
resources and memory upon an interrupt. The number of DMA channels is device dependent.
When a DMA data transfer of a specified count is completed, an interrupt processing program
is automatically executed on the original IRQ channel. The handling of such an interrupt by
DMA completion is same as for standard type of hardware interrupts.
For a detailed description of DMA, refer to the hardware manual for each device.
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CHAPTER 6 INTERRUPTS
6.2 Interrupt Vector
6.2
F2MC-16FX Family
Interrupt Vector
Hardware and software interrupts use the same vector table. The execution of
interrupt service routines can be triggered by asserting the specific IRQ line or
by executing the INT instruction and specifying the number of the interrupt
vector. Interrupt vectors are allocated between addresses as shown in Table
6.2-2 . The location of the Interrupt vector table can be selected by the Table
base register.
■ Interrupt Vector
● Interrupt Vector Table Base Register (TBR)
Figure 6.2-1 Interrupt vector Table base register (TBR)
15
bit
Address:
3A3H, 3A2H
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TB23 TB22 TB21 TB20 TB19 TB18 TB17 TB16
TB15 TB14 TB13 TB12 TB11 TB10
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Initial Value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
R:
R/W:
TBRH, TBRL
readable
readable and writable
The Table Base Register (TBR) allows to relocate the interrupt vector table to any memory
location in steps of 1 kbytes.
The value of the TBR register defines the high-order 14 bits TB[23:10] of the 24 bit start
address of the interrupt vector table. The low-order bits of TB[9:0] are fixed to "0".
The table base register (TBR) is initialized with FFFCH at reset, which results in an initial table
base TB[23:0] = FFFC00H.
The interrupt vector table has a size of 1 Kbyte (256 vector entries).
Table 6.2-1 Examples for TBR
TBR value
start address of
Interrupt vector table
(table base)
end of Interrupt
vector table
Comment
FFFCH
FF:FC00H
FF:FFFFH
as F2MC-16FX (default)
FB00H
FB:0000H
FB:03FFH
start of ROM bank FB
00FCH
00:FC00H
00:FFFFH
end of bank 00 (can be external memory)
0010H
00:1000H
00:13FFH
inside of RAM-area
0000H
00:0000H
00:03FFH
do not use, because of IO-area
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CHAPTER 6 INTERRUPTS
6.2 Interrupt Vector
2
F MC-16FX Family
● Interrupt Vector Table
The interrupt vector table referenced during interrupt processing is assigned to addresses "256 ×
TBR to 256 × TBR + 3FFH" in memory. The reset defaults are from FFFC00H to FFFFFFH for
the location of the vector table. If the vector table should not be located at top of ROM memory,
another TBR value has to be configured.
Hardware interrupts, exceptions and software interrupts share the same vector table. Hence the
interrupt service routine can either be called by a hardware interrupt or by the corresponding
software interrupt.
The three bytes of each start address of the interrupt service routines have to be written to the
appropriate interrupt vectors (VecAddr = 4 × (255-INT#) + 256 × TBR).
Table 6.2-2 Interrupt vector table (1 / 2)
Interrupt / Vector number
Vector address
Index of level
register in ICR
Hardware IRQ / Interrupt cause
INT 0
CALLV 0/1 *
(TBR × 256)+3FCH --
--
INT 1
CALLV 2/3 *
(TBR × 256)+3F8H
--
--
INT 2
CALLV 4/5 *
(TBR × 256)+3F4H
--
--
INT 3
CALLV 6/7 *
(TBR × 256)+3F0H
--
--
INT 4
CALLV 8/9 *
(TBR × 256)+3ECH --
--
INT 5
CALLV 10/11 *
(TBR × 256)+3E8H
--
--
INT 6
CALLV 12/13 *
(TBR × 256)+3E4H
--
--
INT 7
CALLV 14/15 *
(TBR × 256)+3E0H
--
--
INT 8
MODE Byte
(TBR × 256)+3DCH --
Reset
INT 9
(TBR × 256)+3D8H --
INT9 instruction
INT 10
(TBR × 256)+3D4H --
Undefined Instruction Exception
INT 11
(TBR × 256)+3D0H --
NMI
INT 12
(TBR × 256)+3CCH IL12
Delayed Interrupt
INT 13
(TBR × 256)+3C8H IL13
RC clock Timer
INT 14
(TBR × 256)+3C4H IL14
Main Clock Timer
INT 15
(TBR × 256)+3C0H IL15
Sub Clock Timer
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CHAPTER 6 INTERRUPTS
6.2 Interrupt Vector
F2MC-16FX Family
Table 6.2-2 Interrupt vector table (2 / 2)
Interrupt / Vector number
Vector address
Index of level
register in ICR
Hardware IRQ / Interrupt cause
INT 16
(TBR × 256)+3BCH IL16
INT 17
(TBR × 256)+3B8H IL17
INT 18
(TBR × 256)+3B4H IL18
INT 19
(TBR × 256)+3B0H IL19
...
...
...
INT 254
(TBR × 256)+004H
--
--
INT 255
(TBR × 256)+000H
--
--
<reserved for PLL Unlock>
Device specific peripheral.
*: When the program counter bank register (PCB) is same as TBR:TB[23:16] and TBR:TB[15:10] is equal to
111111B, the CALLV instruction vector area overlaps the vector table of the "INT #0" to "INT #7"
instruction. Ensure that the CALLV instruction does not use the same address as that of the "INT #0" to "INT
#7" instruction, or do not use "INT #0" to "INT #7" instruction.
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CHAPTER 6 INTERRUPTS
6.3 Interrupt Control Registers (ICR)
2
F MC-16FX Family
6.3
Interrupt Control Registers (ICR)
For each peripheral resource that has an interrupt function, there is an
interrupt control register (ICR). The interrupt control register (ICR) sets the
interrupt level (IL) for the peripheral resource it is assigned to.
■ Interrupt Control Register (ICR)
Figure 6.3-1 shows a diagram of the bit configuration of the interrupt control register (ICR).
Figure 6.3-1 Interrupt control register (ICR)
15
14
13
12
11
10
9
8
Address:
3A1H
IX7
IX6
IX5
IX4
IX3
IX2
IX1
IX0
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value:
0
0
0
0
1
1
0
0
7
6
5
4
3
2
1
0
IL2
IL1
IL0
R/W
R/W
R/W
bit
bit
Address:
3A0H
Read/Write:
Initial Value:
:
R/W:
X
X
X
X
X
1
1
ICR: IX
ICR: IL
1
no access
readable and writable
[bit15 to bit8] IX[7:0] : Index of the interrupt level (IL) to be accessed
These bits are readable and writable, and specify the index of the interrupt level of the
corresponding internal resource. It selects the number of the interrupt level to be accessed.
IL[n] belongs to the peripheral interrupt request number IRQ[n], which both are related to
the interrupt INT[n].
The system interrupts INT0 to INT11 have a fixed priority and thus have no interrupt levels.
Writing to interrupt levels below the index of 12 has no effect, reading returns an undefined
value. The same restriction applies for not available hardware interrupts above a device
dependent maximum interrupt number.
The IX[7:0] bits is initialized to 0CH at reset.
Figure 6.3-2 illustrates the access to level registers by the IX pointer. The dashed line around
IX and the selected IL shows the actual contents of the ICR.
Level configuration is written to or read from IL, where IX points to. To write the level
configuration to a dedicated IL, specify the according index by writing IX before or
simultaneously by word access. To read from a dedicated IL, IX must be written before
reading IL.
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CHAPTER 6 INTERRUPTS
6.3 Interrupt Control Registers (ICR)
F2MC-16FX Family
Caution for the use of concurrent tasks:
In the case of concurrent tasks accessing the interrupt level information, be careful at the
handling of the indexed access:
- Use word access to write information to ICR:IX and ICR:IL simultaneously.
- At read access, set the index ICR:IX and read the whole ICR register using word access.
Check the ICR:IX value to match the intended index to be read for validation of the
correct ICR:IL entry.
[bit7 to bit3]: Unused bits
Read access returns an undefined value. Write always 0 to these bits.
[bit2 to bit0] IL[2:0] : Interrupt level setting bits
These bits are readable and writable, and specify the interrupt level of the corresponding
internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 6.3-1
describes the relationship between the interrupt level setting bits and interrupt levels.
Table 6.3-1 Interrupt level setting bits and interrupt levels
IL2
IL1
IL0
Level
0
0
0
0 (Strongest)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (Weakest)
1
1
1
7 (No interrupt)
Figure 6.3-2 Relationship between index (IX), level (IL) and IRQ number, example for IX = 20
ICR
52
IX=20
IL16
IRQ16
IL17
IRQ17
IL18
IRQ18
IL19
IRQ19
IL20
IRQ20
IL21
IRQ21
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CHAPTER 6 INTERRUPTS
6.4 Non Maskable Interrupt (NMI)
2
F MC-16FX Family
6.4
Non Maskable Interrupt (NMI)
The F2MC-16FX CPU has a non maskable interrupt. The feature of the external
NMI pin can be enabled, it’s level can be defined and a register to quit the NMI
request is provided.
■ NMI Control Status Register (NMI)
Figure 6.4-1 is a diagram of the bit configuration of the NMI control status register.
Figure 6.4-1 NMI control status register (NMI)
bit
3
2
1
0
Address:
3A5H
FIX9
LEV
EN
FLAG
Read/Write:
R/W
R/W
Initial Value:
0
1
:
R/W:
R/W1:
R/W0:
7
6
5
4
NMI
R/W1 R/W0
0
X
no access
readable and writable
readable, bit can be set only
readable, bit can be cleared only
[bit7 to bit4]: Unused bits
Read access returns an undefined value. Write always 0 to these bits.
[bit3] FIX9 : Fix the location of the INT9 vector
The FIX9 bit changes to an alternative location of the interrupt vector of INT9. If it is set to
"1", the interrupt vector is obtained from address 0F:FFD8H. If it is set to "0" the INT9
vector location is defined by the TBR+3D8H. At reset the FIX9 bit is initialized to "0".
The function is used by the firmware executed at device startup. Making the interrupt vector
of INT9 independent from the table base register (TBR) improves the reliability of the
embedded debug support unit (EDSU).
[bit2] LEV : Signal activity level of the NMI pin
The LEV bit defines the signal activity level of the NMI pin. A value of "1" defines logic
high active input, a value of "0" define logic low active input of the NMI pin.
If the EN bit is not set, the LEV bit is readable and writable. If the EN bit is set, the state of
LEV is locked. In that case LEV can only be read, writing to LEV with EN=1 has no effect.
At reset the LEV bit is initialized to "1", thus the NMI pin is active high by default.
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CHAPTER 6 INTERRUPTS
6.4 Non Maskable Interrupt (NMI)
F2MC-16FX Family
[bit1] EN : Non Maskable Interrupt feature enable bit
The EN bit enables the feature to have a dedicated NMI pin. If the EN bit is set to "0" the
device has no NMI. The CPU will not react on signal level change at the NMI input. The pin
can be used for an other function or general purpose. If the EN bit is set to "1", the NMI pin
is enabled. The CPU branches to the NMI exception processing, if an active signal level is
detected at the NMI pin (defined by the LEV bit).
If the EN bit is set to "1", both the LEV and EN bits are locked for writing. Neither the signal
level can be changed nor the NMI can be disabled after the NMI feature was enabled once.
Only a device reset can change the EN bit back to "0".
At reset the EN bit is initialized to "0", thus the NMI feature is not enabled by default.
The LEV and EN bits must not be activated at same time (changed using the same access).
The EN bit must be enabled individually at last. Otherwise, an NMI can be caused due to
relaxation time of the spike filter.
[bit0] FLAG : Non Maskable Interrupt Flag
The FLAG bit stores an asynchronous event of the NMI occurrence at the NMI pin.
A spike filter is used to filter out short pulses for spike suppression. The polarity of the
pulses depends on the definition in the LEV bit.
The FLAG bit is set by the hardware event (NMI occurrence) and can be cleared by software
to quit the interrupt. An interrupt is only caused, if both the EN and FLAG bits are set.
The FLAG bit can be read and cleared. Writing "1" to the FLAG bit is ignored. Read
operation of read modify write (RMW) instructions returns always "1" for the FLAG bit.
The FLAG bit is undefined after reset. Before enabling the NMI, the FLAG bit should be
cleared.
Figure 6.4-2 Operation of the NMI control/status register
EN
NMI:LEV
lock function
[10]
16FX Bus
EN
[8] [9]
NMI:EN
NMI to CPU
CLKB
Synchronization
NMI pin
level selection
and spike filter
ASET
SCLR
NMI:FLAG
0
Wakeup
1
ASET: asynchronous set
SCLR: synchronous clear
54
SLEEP || STOP || TIMER
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CHAPTER 6 INTERRUPTS
6.5 Interrupt Flow
2
F MC-16FX Family
6.5
Interrupt Flow
Figure 6.5-2 shows the interrupt flow.
■ Interrupt Flow
The interrupt processing flow is entered at occurrence of hardware interrupts, software
interrupts or exceptions. For a detailed interrupt flow chart see Figure 6.5-2 .
The CPU special registers are saved on the stack before the interrupt is processed (see Figure
6.5-1 ).
Figure 6.5-1 Register saving during interrupt processing
MSB
LSB
Word (16 bits)
H
SSP (value before interrupt)
AH
AL
DPR
ADB
DTB
PCB
SSP
PC
PS
SSP (value after interrupt)
L
At the end of the interrupt processing, the context of the CPU registers is restored while
executing the RETI instruction. The CPU returns to normal program execution.
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CHAPTER 6 INTERRUPTS
6.5 Interrupt Flow
F2MC-16FX Family
Figure 6.5-2 Interrupt flow
I, ILM: Interrupt flag and interrupt level mask in the program status (PS)
IF, IE: Internal resource interrupt request flag and enable
DER: DMA enable register of the related DMA channel
IL:
Level configuration of the IRQ channel by ICR/ILR
S:
System stack flag in the CCR/PS
DISEL: DMA intserrupt select register
START
IF & IE = 1
and DER = 1 and
DISEL = IRQ#
YES
NO
IF & IE = 1
and
I=1 & IL<ILM
YES
NO
Fetching and decoding
the next instruction
INT instruction
YES
NO
Executing an ordinary
instruction
NO
Saving PS, PC, PCB, DTB,
ADB, DPR and A into the
system stack (SSP) and
setting I = 0
Saving PS, PC, PCB, DTB,
ADB, DPR and A into the
system stack (SSP) and
setting ILM = IL
I/O service by
DMA processing
Completion of
string instruction
repetition
YES
Updating PC
56
S=1
Fetching the interrupt vector
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F MC-16FX Family
6.6
Hardware Interrupts
CHAPTER 6 INTERRUPTS
6.6 Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU
pauses current program execution and transfers control to the interrupt
processing program defined by the user.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two
operations:
• Comparison between the interrupt request level (IL) and the value in the interrupt level
mask (ILM) of program status (PS), and
• Hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU
to the system stack.
• The stack flag (S) is set.
• Sets ILM in the PS register. The currently requested interrupt level (IL) is automatically set.
• Fetches the corresponding interrupt vector and branches to the processing indicated by that
value.
If the device is in standby mode, a hardware interrupt with IL<7 generates a wake-up event to
the clock and mode control unit.
■ Structure of the Hardware Interrupt System
The interrupt status is indicated by internal resources, the ICR for the interrupt controller, and
the PS value of the CPU. To use a hardware interrupt, make the following set-up:
• Interrupt vector (in memory)
- Consider the TBR value for a non-default location of the vector table.
- The start address of the interrupt service routine has to be written to the appropriate
interrupt vector (VecAddr = 4 × (255-INT#) + 256 × TBR).
• Peripheral resource
- Use the Interrupt enable and request bits to control interrupt requests from peripheral
resources.
• Interrupt controller
- Assign interrupt levels (ICR:IL) for each interrupt, which can occur.
- If interrupts occur simultaneously, a higher priority is defined by lower interrupt levels.
IL=7 disables the interrupt.
- If multiple requests are at the same level, the interrupt controller selects the request with
the lowest interrupt number. In the case of same levels configured, the delayed interrupt
has the lowest priority, independent from its interrupt number.
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CHAPTER 6 INTERRUPTS
6.6 Hardware Interrupts
F2MC-16FX Family
- There is a fixed relationship between the interrupt requests and the ILs. A level can be
defined by IL[n] for each hardware interrupt request IRQ[n] (for n >= 12).
• CPU
- ILM and I in the PS register are used to compare the requested interrupt level (IL) with
the current interrupt level mask (ILM) and to identify the interrupt enable status (I). For
acceptance of hardware interrupts, the I flag has to be set and ILM has to be larger than
IL.
- During interrupt processing, the CPU saves 12 bytes to the memory area indicated by
SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.
- The CPU fetches three bytes of the interrupt vector and loads them onto PC and PCB.
The interrupt handler routine has to start at this location. As a result, the interrupt
processing program defined by the user is executed next. Normal operation is resumed at
execution of the RETI instruction.
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CHAPTER 6 INTERRUPTS
6.6 Hardware Interrupts
2
F MC-16FX Family
■ Hardware Interrupt Operation
Interrupt requests (IRQs) from peripheral resources are fed through the DMA controller before
connecting to the interrupt controller. The DMA controller decides depending on it’s channel
configuration (DMA interrupt request select register DISEL and DMA enable DER:ENx bit), if
the IRQ is handled by DMA transfer or passed to the interrupt controller. DMA transfers are
accepted regardless of the status of the I flag and the interrupt level. The DMA controller has a
fixed priority scheme, channel 0 has highest priority and channel 15 has lowest priority.
Figure 6.6-1 shows the processing flow from the occurrence of a hardware interrupt to the
release of the interrupt request in an interrupt processing program.
Figure 6.6-1 Occurrence and release of hardware interrupt
F2MC-16FX CPU
(9c)
(9b)
Stack
Op.
F2MC-16FX Bus
(9a)
(12)
PS
Register File
I
S
(8)
Check
Int (9)
Execution Pipeline
ILM
(7)
Comparator
INT Number
(6) INT Level
Peripherals with IRQ
Interrupt
Controller
Peripheral
(10)
Enable FF (IE)
IRQ
Source FF (I)
(2)
(3)
DMA
Controller
(4)
(5)
Level
Compa?
rator
Interrupt
Levels
IL
(1)
control of data transfer (3a) and IRQ clear (3b)
(1) An interrupt cause occurs in a peripheral.
(2) The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the
peripheral issues an interrupt request (IRQ).
(3) The DMA controller checks, if the IRQ should be handled by DMA. It evaluates for each
channel, if the interrupt number of the asserted IRQ is selected and if DMA is enabled.
- If the evaluation is true, the transfer is handled by DMA (3a). If the evaluation is false,
interrupt processing is done by the interrupt controller, proceeding with step (4).
- At the end of the DMA transfer, the interrupt bit is cleared in the peripheral (3b).
- If the final transfer count is reached, the DMA completion interrupt is processed by the
interrupt controller.
(4) The interrupt controller receives the interrupt request.
(5) The interrupt controller determines the priority levels of simultaneously requested
interrupts.
(6) The interrupt controller transfers the highest priority interrupt level and the corresponding
interrupt number to the CPU.
(7) The interrupt level requested by the interrupt controller is compared with the ILM value of
the processor status register.
(8) If the comparison shows that the requested level is higher than the current interrupt
processing level (IL<ILM), the I flag value of the same processor status register is
checked.
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CHAPTER 6 INTERRUPTS
6.6 Hardware Interrupts
F2MC-16FX Family
(9) If the check in step 5 shows, that the I flag indicates interrupt enable status, interrupt
processing is performed as soon as the currently executing instruction is completed.
- To save the CPU status, special CPU registers are transferred to the system stack (9a).
- The S bit is set to "1" (9b).
- The requested level is written to the ILM bits (9c).
- The interrupt vector is fetched.
- Then control is transferred to the interrupt processing routine (branch to the address read
as interrupt vector).
(10) When the interrupt cause of step (1) is cleared by software in the user interrupt processing
routine, the interrupt request is completed.
(11) The RETI instruction is used to return from the interrupt processing routine as its last
instruction.
(12) The CPU status is restored from system stack and normal program execution is resumed.
■ Hardware Interrupt Processing Time
The time required for the CPU to execute the interrupt processing (stack operation, interrupt
vector fetch, branch to the interrupt vector) is shown below. The value is valid if stack
operation and interrupt vector fetch are executed without any wait cycles.
• Interrupt start: 10 cycles + c
• Interrupt return: 9 cycles + c (RETI instruction)
Table 6.6-1 Compensation values (c) for interrupt processing cycle count
Address indicated by the stack pointer
Compensation value
Internal area, even-numbered address
0
Internal area, odd-numbered address
+2
In addition wait cycles for bus transfers have to be added, if any (e.g. access to vector table in
slower ROM memory or external area).
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F MC-16FX Family
6.7
Software Interrupts
CHAPTER 6 INTERRUPTS
6.7 Software Interrupts
In response to execution of a special instruction, control is transferred from
the program currently executed by the CPU to the interrupt processing
program defined by the user. This is called the software interrupt function. A
software interrupt occurs always when the software interrupt instruction is
executed.
■ Software Interrupts
A software interrupt request issued by the INT instruction has no interrupt request or enable
flag. A software interrupt request is always issued and accepted by executing the INT
instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not
update the interrupt level mask (ILM). The INT instruction clears the interrupt enable flag (I)
to suspend subsequent hardware interrupt requests.
The CPU performs the following processing when a software interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU
to the system stack.
• The S flag is set.
• Clears I flag in the PS register. Hardware interrupts are automatically disabled.
• Fetches the corresponding interrupt vector and branches to the processing indicated by that
value.
■ Structure of the Software Interrupt System
Software interrupts are fully handled within the CPU. To use a software interrupt, make the
following set-up:
• Interrupt vector (in memory)
- Consider the TBR value for a non-default location of the vector table.
- The start address of the interrupt service routine has to be written to the appropriate
interrupt vector (VecAddr = 4 × (255-INT#) + 256 × TBR).
• CPU
- During interrupt processing, the CPU saves 12 bytes to the memory area indicated by
SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.
- The CPU fetches three bytes of the interrupt vector and loads them onto PC and PCB.
The interrupt handler routine has to start at this location. As a result, the interrupt
processing program defined by the user is executed next. Normal operation is resumed at
execution of the RETI instruction.
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CHAPTER 6 INTERRUPTS
6.7 Software Interrupts
F2MC-16FX Family
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt
processing sequence is activated. The software interrupt processing sequence saves 12 bytes
(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The
sequence then fetches three bytes of interrupt vector and loads them into the program counter
(PC) and program counter bank register (PCB), clears the interrupt enable flag (I), and sets the
stack flag (S) flag. Then, the sequence performs branch processing. As a result, the interrupt
processing program defined by the user application program is executed next.
Figure 6.7-1 illustrates the flow from the occurrence of a software interrupt until the return
from the interrupt processing program.
Figure 6.7-1 Occurrence and release of software interrupt
F2MC-16FX Bus
(2b)
Stack
Op.
(2a)
PS
Register File
I
S
ILM
clear (2c)
Execution Pipeline
INT (1)
(5)
Instruction
Queue
F2MC-16FX CPU
RETI
Instruction (4)
Processing of the
Interrupt Service
Routine (3)
INT
Instruction (1)
(1) The software interrupt instruction is executed.
(2) Interrupt processing is performed by the CPU according to the software interrupt
instruction.
- To save the CPU status, special CPU registers are transferred to the system stack (2a).
- The S flag is set to "1" (2b).
- The I flag is cleared to disable hardware interrupts (2c).
- The interrupt vector is fetched.
- Then control is transferred to the interrupt processing routine (branch to the address read
as interrupt vector).
(3) The Interrupt service routine is processed by the CPU.
(4) The interrupt processing is completed with the RETI instruction in the user interrupt
processing routine.
(5) The CPU restores its context of special registers from system stack.
(6) The CPU proceeds program execution with the next instruction after the INT instruction.
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6.8
Multiple interrupts
CHAPTER 6 INTERRUPTS
6.8 Multiple interrupts
The F2MC-16FX CPU supports multiple interrupts (simultaneous occurring
interrupts and nested interrupt processing).
■ Multiple Hardware Interrupts
If an hardware interrupt of a higher priority (lower level value) occurs while another interrupt
is being processed, control is transferred to the higher priority interrupt after the currently
executing instruction is completed. After processing of the higher priority interrupt is
completed, the original interrupt processing is resumed.
An interrupt of the same or lower priority may be generated while another interrupt is being
processed. If this happens, the new interrupt request is suspended until the current interrupt
processing is completed, unless the interrupt level mask (ILM) value or interrupt enable flag (I)
is changed by an instruction.
A DMA transfer cannot be interrupted and activated from multiple sources. While a DMA
transfer is being processed, all other DMA requests are suspended. At simultaneous occurrence
of requests for the DMA controller, the lowest channel number is processed first.
For a detailed description of DMA, refer to the hardware manual for each device.
■ Multiple Software Interrupts
Software interrupts can not occur simultaneously. They are entered by executing the INT
instruction and are always accepted. However, if an INT instruction is placed within an
interrupt service routine, nested execution of software interrupts is possible.
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CHAPTER 6 INTERRUPTS
6.8 Multiple interrupts
F2MC-16FX Family
■ Interrupt Acceptance Priority
Following table lists all interrupts with conditions for their acceptance.
Table 6.8-1 Control of interrupt acceptance priority
Hardware event
Event
INT#
Instruction Break
(VEIB)
system reserved
-
Tool Break (VENMI)
system reserved
11
NMI
9
Address match
detection
(HW-INT9)
from
Peripheral IRQ
13 on
Acceptance condition
Action, if accepted
P2
Current instruction execution is
finished,
ILM>2 || P == 1
P=0
ILM = 2
P2
Current instruction execution is
finished, string instruction is
interrupted,
ILM>2 || P == 1
P=0
ILM = 2
P4
Current instruction execution is
finished, string instruction is
interrupted,
ILM>4 || P == 1
P=0
ILM = 4
P6
Current instruction execution is
finished, string instruction is
interrupted,
ILM>6 || P == 1
P=0
ILM = 6
Current instruction execution is
finished, string instruction is
interrupted,
ILM > IL
IL
P == 1
U0...U7
I == 1
For multiple requests with same
IL, smallest IRQ number is
accepted.
Current instruction execution is
finished, string instruction is
interrupted,
IL
ILM > IL
U0...U7 P == 1
I == 1
No peripheral IRQs pending with
same IL.
Delayed INT
-
Software Instruction
Break (INTE)
system reserved
9
INT9
-
10
Undefined instruction
exception
-
all
INT instruction
-
-
RETI instruction
-
IL and ILM:
I:
S:
P:
64
Level
-
12
Software event (Instruction)
Type
Save CPU
status to
system
stack
ILM = IL
S=1
Branch to
interrupt
vector
ILM = IL
P=0
ILM = 2
I=0
P2
I=0
always accepted
I=0
I=0
restore CPU status
(including P, I, S, ILM)
Interrupt level and Interrupt level mask
Interrupt enable flag (in CCR of PS)
Stack flag (in CCR of PS)
Privileged mode flag (in CCR of PS)
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CHAPTER 6 INTERRUPTS
6.8 Multiple interrupts
2
F MC-16FX Family
Following table defines the naming of the interrupt levels, its corresponding P flag and ILM
values. It also lists the interrupt cause, which can request the interrupt level.
Table 6.8-2 Interrupt levels
Name
Category
P flag
ILM value
Priority
Remarks
P0
Privileged mode
0
0
Highest
-
P1
0
1
-
P2
0
2
DSU
P3
0
3
-
P4
0
4
NMI
P5
0
5
-
P6
0
6
HW-INT9
P7
0
7
-
1
0
Peripherals
U1
1
1
U2
1
2
U3
1
3
U4
1
4
U5
1
5
U6
1
6
U7
1
7
U0
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Lowest
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CHAPTER 6 INTERRUPTS
6.9 Exceptions
6.9
F2MC-16FX Family
Exceptions
The F2MC-16FX performs exception processing at occurrence of various
software and hardware events.
■ Software Exceptions (Op-Code)
Software exceptions are always accepted. Same as software interrupts, software exceptions
disable any hardware interrupt acceptance. The software exceptions occur at code execution of
following specific op-codes:
● Execution of an undefined instruction
All codes that are not defined in the instruction map are handled as undefined instructions.
When an undefined instruction is executed, processing similar to the INT #10 software
interrupt instruction is performed. Specifically, the program counter (PC) value saved in the
stack is the address at which the undefined instruction is stored. Processing can be restored by
the RETI instruction, however it is of no use, because the same exception occurs again.
Operation:
SSP ←SSP-2, (SSP) ←AH
SSP ←SSP-2, (SSP) ←AL
SSP ←SSP-2, (SSP) ←DPR:ADB
SSP ←SSP-2, (SSP) ←DTB:PCB
SSP ←SSP-2, (SSP) ←PC
SSP ←SSP-2, (SSP) ←PS
S ←1, I ←0
PCB ←Vector #10 address (upper byte)
PC ←Vector #10 address (lower word)
● INT9
This instruction branches to the interrupt processing routine indicated by vector #9. Executing
the RETI instruction in the interrupt routine restores the processing subsequent to the INT9
instruction.
Operation:
SSP ←SSP-2, (SSP) ←AH
SSP ←SSP-2, (SSP) ←AL
SSP ←SSP-2, (SSP) ←DPR:ADB
SSP ←SSP-2, (SSP) ←DTB:PCB
SSP ←SSP-2, (SSP) ←PC+1
SSP ←SSP-2, (SSP) ←PS
S ←1, I ←0
PCB ←Vector #9 address (upper byte)
PC ←Vector #9 address (lower word)
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CHAPTER 6 INTERRUPTS
6.9 Exceptions
● INTE (System reserved, only available with DSU)
INTE is used to insert a software break point for the debug system, using the in circuit
emulator (ICE). At insertion of a software instruction break, the first byte of the original
instruction is replaced by INTE.
This instruction branches to the interrupt processing routine indicated by a fixed vector defined
by the DSU. The PC value saved in the stack is the address at which INTE is stored. Executing
the RETI instruction in the interrupt routine restores the processing at this location (INTE can
be replaced by the original instruction at removal of the software break point).
The privileged mode flag (P) is cleared and the ILM register is set to 2 (enters level P2). This
disables all hardware interrupts and exceptions. The P flag and ILM are restored at execution
of the RETI instruction.
Operation:
SSP ←SSP-2, (SSP) ←AH
SSP ←SSP-2, (SSP) ←AL
SSP ←SSP-2, (SSP) ←DPR:ADB
SSP ←SSP-2, (SSP) ←DTB:PCB
SSP ←SSP-2, (SSP) ←PC
SSP ←SSP-2, (SSP) ←PS
S ←1, I ←0, P ←0, ILM ←2
PCB ←Fixed vector from DSU (upper byte, 00H, address is ignored by DSU)
PC ←Fixed vector from DSU (lower word, 0400H, address is ignored by DSU)
Without the DSU, INTE is handled same as the undefined instruction exception. Interrupt
vector #10 is referenced. The P flag is not cleared and ILM is not updated.
■ Hardware Exceptions (Non Maskable Interrupts)
Hardware exceptions are external events, which are not maskable by any software instruction.
Hardware exceptions with a higher level number, than the actual processed one, are suspended
until execution of the RETI instruction restores the previous level. In addition, hardware
exceptions disable any hardware interrupt acceptance.
At occurrence of multiple hardware exceptions at the same time, they will be accepted with
following priority: VEIB > VENMI > NMI > HW-INT9. If the current interrupt level mask and
P flag setting allows it, hardware exceptions are accepted at the end of each instruction
execution and during execution of string instructions.
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CHAPTER 6 INTERRUPTS
6.9 Exceptions
F2MC-16FX Family
● HW-INT9
HW-INT9 is used by the address match detection function. With that function embedded debug
support (operand address break or data value break) or a simple memory protection can be
provided.
The privileged mode flag (P) is cleared and interrupt level mask (ILM) is set to 6 (enters level
P6). This disables all hardware interrupts from peripherals. The P flag and ILM are restored at
the execution of the RETI instruction.
Operation:
SSP ←SSP-2, (SSP) ←AH
SSP ←SSP-2, (SSP) ←AL
SSP ←SSP-2, (SSP) ←DPR:ADB
SSP ←SSP-2, (SSP) ←DTB:PCB
SSP ←SSP-2, (SSP) ←PC
SSP ←SSP-2, (SSP) ←PS
S ←1, P ←0, ILM ←6
PCB ←Vector #9 address (upper byte)
PC ←Vector #9 address (lower word)
● NMI
The non maskable interrupt (NMI) provides external hardware exception handling.
The privileged mode flag (P) is cleared and interrupt level mask (ILM) is set to 4 (enters level
P4). This disables all hardware interrupts from peripherals and the HW-INT9. The P flag and
ILM are restored at execution of the RETI instruction.
Operation:
SSP ←SSP-2, (SSP) ←AH
SSP ←SSP-2, (SSP) ←AL
SSP ←SSP-2, (SSP) ←DPR:ADB
SSP ←SSP-2, (SSP) ←DTB:PCB
SSP ←SSP-2, (SSP) ←PC
SSP ←SSP-2, (SSP) ←PS
S ←1, P ←0, ILM ←4
PCB ←Vector #11 address (upper byte)
PC ←Vector #11 address (lower word)
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CHAPTER 6 INTERRUPTS
6.9 Exceptions
● Tool break (VENMI, system reserved, only available with DSU)
VENMI is provided for debugging with DSU. It implements various break factors.
The privileged mode flag (P) is cleared and interrupt level mask (ILM) is set to 2 (enters level
P2). This disables all hardware interrupts and exceptions. The P flag and ILM are restored at
execution of the RETI instruction.
Operation:
SSP ←SSP-2, (SSP) ←AH
SSP ←SSP-2, (SSP) ←AL
SSP ←SSP-2, (SSP) ←DPR:ADB
SSP ←SSP-2, (SSP) ←DTB:PCB
SSP ←SSP-2, (SSP) ←PC
SSP ←SSP-2, (SSP) ←PS
S ←1, P ←0, ILM ←2
PCB ←Fixed vector from DSU (upper byte, 00H, address is ignored by DSU)
PC ←Fixed vector from DSU (lower word, 0400H, address is ignored by DSU)
● Instruction break (VEIB, system reserved, only available with DSU)
VEIB is provided for debugging with DSU. It implements the instruction break after
instruction execution. Opposed to other hardware exceptions, VEIB is not accepted during
execution of a string instruction.
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CHAPTER 6 INTERRUPTS
6.9 Exceptions
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CHAPTER 7
ADDRESSING
This chapter describes addressing for the
F2MC-16FX instructions.
Addressing specifies the data to be used and
an address.
In F2MC-16FX, effective addressing or an used
instruction code determines the address format
(absolute address or relative address). When the
address format is determined by the instruction
code itself, an address must be specified in
compliance with the used instruction code.
Some instructions enable several types of
addressing to be specified.
7.1 Effective Address Field
7.2 Direct Addressing
7.3 Indirect Addressing
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CHAPTER 7 ADDRESSING
7.1 Effective Address Field
7.1
F2MC-16FX Family
Effective Address Field
Table 7.1-1 lists the address formats that may be specified in the effective
address field.
■ Effective Address Field
Table 7.1-1 Effective Address Field
Code
00H
01H
02H
03H
04H
05H
06H
07H
72
Coding
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Default bank
Register direct
Note: The general purpose register name on the
left notation corresponds to
the byte,
word
and long-word types.
None
08H
09H
0AH
0BH
@RW0
@RW1
@RW2
@RW3
0CH
0DH
0EH
0FH
@RW0 +
@RW1 +
@RW2 +
@RW3 +
10H
11H
12H
13H
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
14H
15H
16H
17H
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
DTB
DTB
ADB
SPB
18H
19H
1AH
1BH
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit displacement
DTB
DTB
ADB
SPB
1CH
1DH
1EH
1FH
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
DTB
DTB
PCB
DTB
Register indirect
DTB
DTB
ADB
SPB
Register indirect with post-increment
DTB
DTB
ADB
SPB
DTB
DTB
ADB
SPB
Register indirect with 8-bit displacement
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CHAPTER 7 ADDRESSING
7.2 Direct Addressing
2
F MC-16FX Family
7.2
Direct Addressing
In direct addressing, a value, register, and address must be directly specified
for the operands.
■ Direct Addressing
● Immediate data (#imm)
Directly specify an operand value. There are four types of immediate data according to data
length as below:
• #imm4
• #imm8
• #imm16
• #imm32
● Register direct
Directly specify a register for the operand. Registers that can be specified are as below:
• General-purpose registers (Byte):
(Word):
R0, R1, R2, R3, R4, R5, R6, R7
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
(Long word):RL0, RL1, RL2, RL3
• Dedicated registers (Accumulator): A, AL
(Pointer):
SP *
(Bank):
PCB, DTB, USB, SSB, ADB
(Page):
DPR
(Control):
PS, CCR, RP, ILM
*: For SP, either user stack pointer (USP) or system stack pointer (SSP) is selected for use,
according to the value of the S flag in the condition code register (CCR). For branch
instructions, program counter (PC) is not described in the operand of the instruction, but
it is automatically specified.
● Direct branch address (addr16)
Directly specify an address to which the execution will branch by means of displacement. The
address length with displacement is 16 bits and the address indicates the destination of the
branch in the logical space. This addressing is applied to an unconditional branch instruction
and a subroutine call instruction. Bits 16 to 23 of the address are given by the program counter
bank register (PCB).
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CHAPTER 7 ADDRESSING
7.2 Direct Addressing
F2MC-16FX Family
● Physical direct branch address (addr24)
Directly specify a physical address to which the execution will branch by means of
displacement. The data length with displacement is 24 bits. This addressing is applied to an
unconditional branch instruction, a subroutine call instruction, and a software interrupt
instruction.
● I/O direct (io)
Directly specify a memory address in the operand by means of 8-bit displacement.
Independently of the respective values for data bank register (DTB) and direct page register
(DPR), the I/O space with physical addresses 000000H to 0000FFH is accessible. It is invalid
to describe the bank select prefix to specify a bank before an instruction using this addressing.
● Abbreviated direct address (dir)
Specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are
given by the direct page register (DPR). Bits 16 to 23 of the address are given by the data bank
register (DTB).
● Direct address (addr16)
Specify lower 16 bits of a memory address in the operand. Bits 16 to 23 of the address are
given by the data bank register (DTB).
● I/O direct bit address (io:bp)
Directly specify a bit within the range of physical addresses 000000H to 0000FFH. Bit position
is represented by :bp. The higher number is the most significant bit and the lower number is
the least significant bit.
● Abbreviated direct bit address (dir:bp)
Directly specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the
address are given by the direct page register (DPR). Bits 16 to 23 of the address are given by
the data bank register (DTB). Bit position is represented by :bp. The higher number is the
most significant bit and the lower number is the least significant bit.
● Direct bit address (addr16:bp)
Directly specify an arbitrary bit within 64 Kbytes. Bits 16 to 23 of the address are given by the
data bank register (DTB). Bit position is represented by :bp. The higher number is the most
significant bit and the lower number is the least significant bit.
● Vector address (#vct)
The address to which the execution will branch is determined by the content of the vector that
is specified herein. The vector number data length may be either four bits or eight bits. This
addressing is applied to a subroutine call instruction and a software interrupt instruction.
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7.3
Indirect Addressing
CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
In indirect addressing, the data indicated by the operand you coded indirectly
gives an address.
■ Indirect Addressing
● Register indirect (@RWj j = 0 to 3)
The register indirect addressing is used to access a memory location whose address is specified
by the content of general-purpose register RWj. Bits 16 to 23 of the address are given by the
data bank register (DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the
additional data bank register (ADB) if RW2 is used.
● Register indirect with post-increment (@RWj+ j = 0 to 3)
This addressing is also used to access a memory location whose address is specified by the
content of general-purpose register RWj. After the execution of the operand operation, RWj is
incremented by the operand data length (1 for byte, 2 for word, and 4 for long word). Bits 16
to 23 of the address are given by the data bank register (DTB) if RW0 and RW1 are used, by
the SPB if RW3 is used, and by the additional data bank register (ADB) if RW2 is used.
If the value resulting from post-increment indicates the address of the increment-specified
register itself, the value of this register is incremented when referred subsequently. Then, if a
data write instruction is issued to the register, the priority is given to the data write instruction,
so that the register value, which would otherwise be incremented, becomes the written data.
● Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)
This addressing is used to access a memory location whose address is specified by the
displacement added to the content of general-purpose register RWj. Displacement may be
either byte or word and is added as a signed value. Bits 16 to 23 of the address are given by
the data bank register (DTB) if RW0, RW1, RW4, and RW5 are used. Bits 16 to 23 are given
by the SPB if RW3 and RW7 and by the additional data bank register (ADB) if RW2 and RW6
are used.
● Long register indirect with displacement (@RLi+disp8 i = 0 to 3)
This addressing is used to access a memory location whose address is specified by the lower 24
bits that result from the displacement added to the content of general-purpose register RLi.
Displacement is eight bits and added as a signed value.
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CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
F2MC-16FX Family
● Program counter indirect with displacement (@PC+disp16)
This addressing is used to access a memory location whose address is specified by (address of
instruction + 4 + disp16). Displacement is a word length. Bits 16 to 23 of the address are
given by the program counter bank register (PCB).
Note that respective operand addresses of the instructions listed next are not regarded as being
(next instruction address + disp16):
• DBNZ
eam, rel
• DWBNQ eam, rel
• CBNE
eam, #imm8, rel
• CWBNE
eam, #imml16, rel
• MOV
eam, #imm8
• MOVM
eam, #imm16
● Register indirect with base index (@RW0+RW7, @RW1+RW7)
This addressing is used to access a memory location whose address is specified by a value
obtained by adding the content of RW0 or RW1 to the content of general-purpose register
RW7. Bits 16 to 23 of the address are given by the data bank register (DTB).
● Program counter relative branch address (rel)
The address to which the execution will branch is determined by a value obtained by adding
the 8-bit displacement to the value of the program counter (PC). If the result of the addition
exceeds 16 bits, the bank register is not incremented or decremented and the part of excess is
ignored. Consequently, the address falls within the closed bank of 64 Kbytes. This addressing
is applied to an unconditional or conditional branch instruction. Bits 16 to 23 of the address
are given by the program counter bank register (PCB).
● Register List (rlst)
This addressing specifies a register subjected to push/pop for the stack (see Figure 7.3-1 ).
Figure 7.3-1 Configuration of Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
When the bit is "1", the associated register is selected. When the bit is "0",
the associated register is not selected.
● Accumulator indirect (@A)
This addressing is used to access a memory location whose address is specified by the content
of the lower words of the accumulator (AL). Bits 16 to 23 of the address are given by the data
bank register (DTB).
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CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
● Accumulator indirect branch address (@A)
The address to which the execution will branch is determined by the content for the lower
words of the accumulator (AL). This address indicates the destination of the branch within the
bank space. Bits 16 to 23 of the address are given by the program bank register (PCB). In the
case of the jump context (JCTX) instruction, however, bits 16 to 23 of the address are given by
the data bank register (DTB). This addressing is applied to an unconditional branch instruction.
● Indirectly specified branch address (@ear)
The word data with the address specified by ear corresponds to the address to which the
execution will branch.
● Indirectly specified branch address (@eam)
The word data with the address specified by eam corresponds to the address to which the
execution will branch.
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CHAPTER 7 ADDRESSING
7.3 Indirect Addressing
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CHAPTER 8
DETAILED
INSTRUCTIONS
This chapter describes each execution
instruction used in the assembler in a reference
format. The execution instructions are
presented in alphabetical order.
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CHAPTER 8 DETAILED INSTRUCTIONS
8.1 Instruction Overview
8.1
F2MC-16FX Family
Instruction Overview
In "CHAPTER 8 DETAILED INSTRUCTIONS", the following items are described
for each instruction.
■ Instruction Overview
● Assembler format
The format for coding each instruction into an assembler source program is presented.
• Upper case letters and symbols:
Write them as they are into a source program.
• Lower case letters:
Rewrite them into a source program.
• Number after a lower case letter: Indicates a bit width in the instruction.
● Operation
The operation for registers and data by instruction execution is presented.
● CCR
The status of each flag (I, S, T, N, Z, V and C) of the condition code register (CCR) is
presented.
• *: Denotes that the flag changes with the instruction execution.
• –: Denotes that the flag does not change.
• S: Denotes that the flag is set with the instruction execution.
• R: Denotes that the flag is clear with the instruction execution.
● Byte count, cycle count
The byte count of an instruction, the cycle count at instruction execution time, and the cycle
count for correcting odd addresses are shown.
● Example
An example of each instruction is presented.
All numeric values of the data given in any example are hexadecimal numbers. Any numeric
value of the data given in the operand represents a hexadecimal number with suffix (H).
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CHAPTER 8 DETAILED INSTRUCTIONS
8.1 Instruction Overview
2
F MC-16FX Family
■ Symbols (Abbreviations) Used in Detailed Instructions
Table 8.1-1 lists the symbols used in the detailed instructions.
Table 8.1-1 Symbols (abbreviations) Used in Detailed Instructions (1 / 2)
Coding
A
32-bit accumulator
The length of used bits varies depending on the instruction.
Byte:
Lower 8 bits of AL
Word:
16 bits of AL
Long word:
32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
brg3
DTB, ADB, PCB, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
Rj
R0, R1, R2, R3
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
addr24
ad24 0-15
ad24 16-23
io
imm4
imm8
imm16
imm32
ext (imm8)
disp8
disp16
bp
CM44-00203-3E
Meaning
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data resulting from the signed extension of 8-bit immediate data
8-bit displacement
16-bit displacement
Bit offset value
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CHAPTER 8 DETAILED INSTRUCTIONS
8.1 Instruction Overview
F2MC-16FX Family
Table 8.1-1 Symbols (abbreviations) Used in Detailed Instructions (2 / 2)
Coding
vct4
vct8
(
)b
Meaning
Vector number (0 to 15)
Vector number (0 to 255)
Bit address
re1
Specifies a PC relative branch.
ear
eam
Effective addressing (codes 00H to 07H)
Effective addressing (codes 08H to 1FH)
r1st
Register list
■ Execution Cycles
The cycle count required for the execution of an instruction is obtained by adding up the "cycle
count" specific to each instruction, a value of "odd addresses correction", which is determined
according to the condition.
At the actual instruction execution time, the execution cycles may become larger than the
calculated value due to the instruction fetch delay, the data access conflict, etc. Especially,
when performing instruction fetch and data access from an external bus by using the external
bus interface, the execution cycles becomes larger than the calculated value.
■ Odd Address Correction
For some instructions, the execution cycles increases when performing data access to odd
addresses. The execution cycles that increases at data access time to odd addresses is shown
under the title of "odd address correction" in item B in the instruction list.
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.2 ADD (Add Byte Data of Destination and Source to
Destination)
2
F MC-16FX Family
8.2
ADD (Add Byte Data of Destination and Source to
Destination)
Add the byte data specified by the second operand to the byte data specified
by the first operand and store the result in the first operand.
If the first operand is the accumulator (A), 00H are transferred to upper byte of AL.
● Assembler format:
ADD A,#imm8
ADD A,dir
ADD A,ear
ADD A,eam
ADD ear,A
ADD eam,A
● Operation:
(First operand) ← (First operand)+(Second operand)
[Byte addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
A
ear
eam
Second operand
#imm8
dir
ear
eam
A
A
Byte count
2
2
2
2+
2
2+
Cycle count
1
2
1
2
1
3
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CHAPTER 8 DETAILED INSTRUCTIONS
8.2 ADD (Add Byte Data of Destination and Source to
Destination)
● Example:
F2MC-16FX Family
ADD A,0E021H
In this example, the byte data (ABH) at address E021H is added to the low-order byte data
(46H) of AL.
AH
A
AL
×× ××
CCR
A0 46
×××××
A
AH
AL
×× ××
00 F1
CCR
Memory
A B
1 0 0 0
Memory
E021
Before execution
84
×
T N Z V C
T N Z V C
A B
E021
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.3 ADDC (Add Byte Data of AL and AH with Carry to AL)
2
F MC-16FX Family
8.3
ADDC (Add Byte Data of AL and AH with Carry to
AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry flag (C)
together and restore the result in AL. 00H are transferred to the high-order byte
of AL.
● Assembler format:
ADDC A
● Operation:
(AL) ← (AH)+(AL)+(C)
[Byte addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
ADDC A
In this example, the low-order byte data (D4H) of AL and the C flag ("0") are added to the loworder byte data (05H) of AH.
A
AH
AL
05 05
00 D4
CCR
××××
A
0
AH
AL
05 05
00 D9
CCR
T N Z V C
Before execution
CM44-00203-3E
×
1 0 0 0
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.4 ADDC (Add Byte Data of Accumulator and Effective Address
with Carry to Accumulator)
8.4
F2MC-16FX Family
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)
Add the byte data and the carry flag (C) to the lowest-order byte data, and store
the result to the lowest-order byte of the accumulator (A). 00H are transferred to
upper byte of AL.
● Assembler format:
ADDC
A, ear
ADDC
A, eam
● Operation:
(A) ← (A)+(second operand)+(C)
[Byte addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
86
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
1
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.4 ADDC (Add Byte Data of Accumulator and Effective Address
with Carry to Accumulator)
2
F MC-16FX Family
● Example:
ADDC A, 0E035H
In this example, the word data (8952H) and C flag ("1") at the address (E024H) specified by
the second operand (@RW0+) are added to the word data (2068H) of AL.
A
AH
AL
×× ××
A0 46
CCR
××××
A
1
AH
AL
×× ××
00 2C
CCR
T N Z V C
Memory
D 5
0 0 0 1
T N Z V C
Memory
E035
Before execution
CM44-00203-3E
×
D 5
E035
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.5 ADDCW (Add Word Data of Accumulator and Effective
Address with Carry to Accumulator)
8.5
F2MC-16FX Family
ADDCW (Add Word Data of Accumulator and
Effective Address with Carry to Accumulator)
Add the low-order word data (AL) of the accumulator (A), word data specified
by the second operand, and carry flag (C) together and restore the result in the
low-order word of A.
● Assembler format:
ADDCW
A, ear
ADDCW
A, eam
● Operation:
(A) ← (A)+(second operand)+(C)
[Word addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
88
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
1
2
Odd address correction
0
1
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.5 ADDCW (Add Word Data of Accumulator and Effective
Address with Carry to Accumulator)
2
F MC-16FX Family
● Example:
ADDCW A,@RW0+
In this example, the word data (8952H) at the address (E024H) specified by the second operand
(@RW0+) and the C flag ("1") are added to the word data (2068H) of AL.
A
RW0
AH
AL
×× ××
20 68
CCR
E0 24
××××
A
1
RW0
AH
AL
×× ××
A9 BB
CCR
E0 26
T N Z V C
Memory
8
5
9
2
1 0 0 0
T N Z V C
Memory
E025
E024
Before execution
CM44-00203-3E
×
8
5
9
2
E025
E024
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.6 ADDDC (Add Decimal Data of AL and AH with Carry to AL)
8.6
F2MC-16FX Family
ADDDC (Add Decimal Data of AL and AH with Carry
to AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry flag (C)
together in decimal and restore the result in the low-order byte of AL. 00H are
transferred to the high-order byte of AL.
● Assembler format:
ADDDC A
● Operation:
(AL) ← (AH)+(AL)+(C)
[Decimal addition with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Undefined
C:
Set when a carry has occurred as a result of the decimal operation, cleared otherwise.
● Byte count and cycle count:
Byte count:
1
Cycle count:
2
● Example:
ADDDC A
In this example, the low-order byte data (58H) and the flag C ("0") are added to the low-order
byte (62H) of AL in decimal operation.
AH
A
××
AL
××
62
CCR
AH
58
××××
A
0
××
AL
62
CCR
T N Z V C
Before execution
90
00 20
×
0 0
×
1
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.7 ADDL (Add Long Word Data of Destination and Source to
Destination)
2
F MC-16FX Family
8.7
ADDL (Add Long Word Data of Destination and
Source to Destination)
Add the long word data specified by the second operand to the long word data
specified by the first operand and restore the result in the first operand.
● Assembler format:
ADDL A,#imm32
ADDL A,ear
ADDL A,eam
● Operation:
(First operand) ← (First operand)+(Second operand)
[Long word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
Second operand
#imm32
ear
eam
Byte count
5
2
2+
Cycle count
2
2
3
Odd address correction
0
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.7 ADDL (Add Long Word Data of Destination and Source to
Destination)
● Example:
F2MC-16FX Family
ADDL A,0E077H
In this example, the long word data (357F41ABH) at address E077H is added to the long word
data (85B7A073H) of the accumulator (A).
A
AH
AL
85 B7
A0 73
CCR
A
AH
AL
BB 36
E2 1E
×××××
CCR
5
F
1
B
E07A
E079
E078
E077
Before execution
92
1 0 0 0
Memory
Memory
3
7
4
A
×
T N Z V C
T N Z V C
3
7
4
A
5
F
1
B
E07A
E079
E078
E077
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.8 ADDSP (Add Word Data of Stack Pointer and Immediate
Data to Stack Pointer)
2
F MC-16FX Family
8.8
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer)
Add 16-bit immediate data or the value resulting from sign-extending 8-bit
immediate data to the word data pointed to by SP (stack pointer) and restore
the result in SP. If the addition result exceeds 16 bits, an underflow occurs.
CCR does not indicate whether an underflow has occurred.
● Assembler format:
(1) ADDSP #imm8
(2) ADDSP #imm16
● Operation:
(1) (SP) ← (SP)+Sign-extended imm8
[Word addition]
(2) (SP) ← (SP)+imm16
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Operand
#imm8 #imm16
Byte count
2
3
Cycle count
1
1
● Example:
ADDSP #89BAH
In this example, the 16-bit immediate data (89BAH) is added with a sign to SP. The addition
result exceeds 16 bits, causing an underflow.
SP
E2 A4
×0000
TNZVC
Before execution
CCR
CM44-00203-3E
SP
6C 5E
×0000
TNZVC
After execution
CCR
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CHAPTER 8 DETAILED INSTRUCTIONS
8.9 ADDW (Add Word Data of AL and AH to AL)
8.9
F2MC-16FX Family
ADDW (Add Word Data of AL and AH to AL)
Add the word data of AH and that of AL together and restore the result to AL.
● Assembler format:
ADDW A
● Operation:
(AL) ← (AH)+(AL)
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
ADDW A
In this example, the word data (83A2H) of AH is added to the word data (7F23H) of AL. An
overflow occurs, causing the C flag to be set.
A
AH
AL
83 A2
7F 23
CCR
×××××
A
AH
AL
83 A2
02 C5
CCR
Before execution
94
×
0 0 0 1
T N Z V C
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.10 ADDW (Add Word Data of Destination and Source to
Destination)
2
F MC-16FX Family
8.10
ADDW (Add Word Data of Destination and Source to
Destination)
Add the word data specified by the second operand to the word data specified
by the first operand and restore the result in the first operand.
● Assembler format:
ADDW A,#imm16
ADDW A,ear
ADDW A,eam
ADDW ear,A
ADDW eam,A
● Operation:
(First operand) ← (First operand)+(Second operand)
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Byte count
3
2
2+
2
2+
Cycle count
1
1
2
1
3
Odd address correction
0
0
1
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.10 ADDW (Add Word Data of Destination and Source to
Destination)
● Example:
F2MC-16FX Family
ADDW @RW0+1,A
In this example, the word data (CD04H) of AL is added to the word data (315DH) of the
address (E2A5H) specified by the first operand (@RW0+1).
A
RW0
AH
AL
×× ××
CD 04
CCR
E2 A4
×××××
A
RW0
AH
AL
×× ××
CD 04
E2 A4
CCR
3 1
5 D
X X
Memory
E2A6
E2A5
E2A4
Before execution
96
1 0 0 0
T N Z V C
T N Z V C
Memory
×
F E
6 1
× ×
E2A6
E2A5
E2A4
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.11 AND (And Byte Data of Destination and Source to
Destination)
2
F MC-16FX Family
8.11
AND (And Byte Data of Destination and Source to
Destination)
Take the logical AND operation of the byte data specified by the first operand
and the byte data specified by the second operand and restore the result in the
first operand.
● Assembler format:
AND A,#imm8
AND A,ear
AND A,eam
AND ear,A
AND eam,A
● Operation:
(First operand) ← (First operand) and (Second operand)
[Byte logical AND]
The logical AND operation of the byte data specified by the first operand and the byte data
specified by the second operand is taken on a bit-by-bit basis and the result is restored in the
first operand.
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
ear
eam
Second operand
#imm8
ear
eam
A
A
Byte count
2
2
2+
2
2+
Cycle count
1
1
2
1
3
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CHAPTER 8 DETAILED INSTRUCTIONS
8.11 AND (And Byte Data of Destination and Source to
Destination)
● Example:
F2MC-16FX Family
AND 0052H,A
In this example, the logical AND operation is taken between the byte data (FAH) at address
0052H and the low-order byte data (55H) of AL.
AH
A
AL
00 55
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
Memory
F A
×
0 0 0
×
T N Z V C
Memory
0052
Before execution
98
AL
00 55
5 0
0052
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.12 AND (And Byte Data of Immediate Data and Condition
Code Register)
2
F MC-16FX Family
8.12
AND (And Byte Data of Immediate Data and
Condition Code Register)
Take the logical AND operation of the byte data of the condition code register
(CCR) and 8-bit immediate data and restore the result in CCR.
In the logical AND operation, the most significant bit of the byte data is not taken into
consideration.
● Assembler format:
AND CCR,#imm8
● Operation:
(CCR) ← (CCR) and imm8
[Byte logical AND]
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I: Stores bit 6 of the operation result.
S: Stores bit 5 of the operation result.
T: Stores bit 4 of the operation result.
N: Stores bit 3 of the operation result.
Z: Stores bit 2 of the operation result.
V: Stores bit 1 of the operation result.
C: Stores bit 0 of the operation result.
●Byte count and cycle count:
Byte count:
2
Cycle count:
1
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.12 AND (And Byte Data of Immediate Data and Condition
Code Register)
● Example:
F2MC-16FX Family
AND CCR,#57H
In this example, the logical AND operation is taken between the CCR value (0110101B) and
the immediate data (57H).
AH
A
CCR
AL
×× ××
I
0
S
1
×× ××
T
1
N
0
Z
1
V
0
C
1
A
CCR
AH
AL
×× ××
×× ××
I
0
S
0
T
1
ILM2 ILM1 ILM0
× × ×
ILM
MSB
RP
Before execution
100
Z
1
V
0
C
1
ILM2 ILM1 ILM0
× × ×
ILM
LSB
× × × × ×
N
0
MSB
RP
LSB
× × × × ×
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.13 ANDL (And Long Word Data of Destination and Source to
Destination)
2
F MC-16FX Family
8.13
ANDL (And Long Word Data of Destination and
Source to Destination)
Take the logical AND operation for the long word data of the accumulator (A)
and that specified by the second operand in a bit-by-bit basis and restore the
result in A.
● Assembler format:
ANDL A,ear
ANDL A,eam
● Operation:
(A) ← (A) and (Second operand)
[Long word logical AND]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
2
3
Odd address correction
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.13 ANDL (And Long Word Data of Destination and Source to
Destination)
● Example:
F2MC-16FX Family
ANDL A,0FFF0H
In this example, the logical AND operation is taken between the long word data (8252FEACH)
of the accumulator (A) and the long word data (FF55AA00H) at address FFF0H.
AH
A
AL
82 52
FE AC
CCR
AH
A
AL
82 50
×××××
AA 00
CCR
T N Z V C
F
5
A
0
FFF3
FFF2
FFF1
FFF0
Before execution
102
1 0 0
×
T N Z V C
Memory
Memory
F
5
A
0
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.14 ANDW (And Word Data of AH and AL to AL)
2
F MC-16FX Family
8.14
ANDW (And Word Data of AH and AL to AL)
Take the logical AND operation of the word data of AH and that of AL and
restore the result in AL.
● Assembler format:
ANDW A
● Operation:
(AL) ← (AH) and (AL)
[Word logical AND]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
ANDW A
In this example, the logical AND operation is taken between the word data (AB98H) of AL and
the word data (0426H) of AH.
A
AH
04 26
AL
AB 98
CCR
×××××
A
AH
04 26
CCR
T N Z V C
Before execution
CM44-00203-3E
AL
00 00
×
0 1 0
×
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.15 ANDW (And Word Data of Destination and Source to
Destination)
8.15
F2MC-16FX Family
ANDW (And Word Data of Destination and Source to
Destination)
Take the logical AND operation of the word data specified by the first operand
and the word data specified by the second operand and restore the result in the
first operand.
● Assembler format:
ANDW A,#imm16
ANDW A,ear
ANDW A,eam
ANDW ear,A
ANDW eam,A
● Operation:
(First operand) ← (First operand) and (Second operand)
[Word logical AND]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
104
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Byte count
3
2
2+
2
2+
Cycle count
1
1
2
1
3
Odd address correction
0
0
1
0
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.15 ANDW (And Word Data of Destination and Source to
Destination)
2
F MC-16FX Family
● Example:
ANDW 0E001H,A
In this example, the logical AND operation is taken between the word data (8342H) at address
0E001H and the word data (5963H) of AL.
AH
A
AL
59 63
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
E002
E001
Before execution
CM44-00203-3E
×
0 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
AL
59 63
0 1
4 2
E002
E001
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.16 ASR (Arithmetic Shift Byte Data of Accumulator to Right)
8.16
F2MC-16FX Family
ASR (Arithmetic Shift Byte Data of Accumulator to
Right)
Shift the least significant byte data of the accumulator (A) arithmetically to the
right by the number of bits specified by the second operand. The most
significant bit of the least significant byte data for A is not changed.
The bit last shifted out from the least significant bit is stored in the carry flag (C) of the
condition code register (CCR).
● Assembler format:
ASR A,R0
● Operation:
MSB
C
LSB
T
1
AL
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
106
Byte count:
2
Cycle count:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.16 ASR (Arithmetic Shift Byte Data of Accumulator to Right)
2
F MC-16FX Family
● Example:
ASR A,R0
In this example, the low-order byte data (96H) of AL is shifted arithmetically to the right by the
number of bits (3 bits) specified by R0.
AH
A
AL
×× ××
R0
××
03
CCR
AH
96
×××××
T N Z V C
Before execution
CM44-00203-3E
A
AL
×× ××
R0
××
03
F2
CCR 1 1 0
×
1
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.17 ASRL (Arithmetic Shift Long Word Data of Accumulator to
Right)
8.17
F2MC-16FX Family
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right)
Shift the long word data of the accumulator (A) arithmetically to the right by the
number of bits specified by the second operand.
The most significant bit of A is not changed. The bit last shifted out from the least significant
bit is stored in the carry flag (C) of the condition code register (CCR).
● Assembler format:
ASRL A,R0
● Operation:
MSB
LSB
C
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
108
Byte count:
2
Cycle count:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.17 ASRL (Arithmetic Shift Long Word Data of Accumulator to
Right)
2
F MC-16FX Family
● Example:
ASRL A,R0
In this example, the long word data (12345678H) of the accumulator (A) is shifted
arithmetically to the right by the number of bits (2 bits) specified by R0.
AH
A
AL
12 34
AH
56 78
R0
CCR
0
2
× ×××0
T N Z V C
Before execution
CM44-00203-3E
A
AL
04 8D
15 9E
R0
0
2
CCR 1 0 0 × 0
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
8.18
F2MC-16FX Family
ASRW (Arithmetic Shift Word Data of Accumulator
to Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right
by one bit.
The most significant bit of the low-order word data for A is not changed. The bit shifted out
from the least significant bit is stored in the carry flag (C).
● Assembler format:
ASRW A
● Operation:
MSB
LSB
C
T
1
AL
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the old carry value is equal to "1" or the old T value is equal to "1", cleared
otherwise.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Byte count and cycle count:
110
Byte count:
1
Cycle count:
1
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.18 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
2
F MC-16FX Family
● Example:
ASRW A
In this example, the word data (A096H) of AL is shifted arithmetically to the right by one bit.
A
AH
AL
×× ××
A0 96
CCR 0
×××
A
1
AH
AL
×× ××
D0 4B
CCR 1 1 0
T N Z V C
Before execution
CM44-00203-3E
×
0
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.19 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
8.19
F2MC-16FX Family
ASRW (Arithmetic Shift Word Data of Accumulator
to Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right
by the number of bits specified by the second operand.
The most significant bit of the low-order word data for A is not changed. The bit last shifted
out from the least significant bit is stored in the carry flag (C) of the condition code register
(CCR).
● Assembler format:
ASRW A,R0
● Operation:
MSB
LSB
C
T
1
AL
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
112
Byte count:
2
Number of states:
1
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.19 ASRW (Arithmetic Shift Word Data of Accumulator to Right)
2
F MC-16FX Family
● Example:
ASRW A,R0
In this example, the word data (A096H) of AL is shifted arithmetically to the right by the
number of bits (2 bits) specified by R0.
AH
A
×× ××
R0 0 2
AL
A0 96
CCR
××××
AH
A
0
T N Z V C
Before execution
CM44-00203-3E
AL
E8 25
×× ××
R0 0 2
CCR 0 1 0
×
1
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.20 BBcc (Branch if Bit Condition satisfied)
8.20
F2MC-16FX Family
BBcc (Branch if Bit Condition satisfied)
Cause a branch if the bit data specified by the first operand satisfies the
condition.
Control is transferred to the address resulting from word-adding the sign-extended data,
specified by the second operand, to the address of the instruction following the BBcc
instruction.
● Assembler format:
BBC addr16:bp, rel
BBS addr16:bp, rel
BBC dir:bp, rel
BBS dir:bp, rel
BBC io:bp, rel
BBS io:bp, rel
● Operation:
If the condition is satisfied:
(PC) ← (PC) + <Byte count> + rel
[Word addition]
If the condition is not satisfied:
(PC) ← (PC)+<Byte count>
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N: Unchanged
Z:
Set when the bit data is "0"; cleared when "1".
V and C:
Unchanged
● Byte count and cycle count:
114
BBcc
BBC
BBS
Condition
Bit data = 0
Bit data = 1
First operand
addr16:bp
dir:bp
io:bp
addr16:bp
dir:bp
io:bp
Byte count
5
4
4
5
4
4
Cycle count
5
5
5
5
5
5
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.20 BBcc (Branch if Bit Condition satisfied)
2
F MC-16FX Family
● Example:
BBC 1234H:7,12H
In this example, a branch is caused if bit 7 in the byte data (7FH) at address 1234H is equal to
"0" (condition satisfied).
PC
+ (12 + number of bytes 5)
E100
PC
E117
Memory
Memory
× ×
× ×
7 F
1234
: bit7 = 0
7 F
1234
× ×
× ×
Before execution
After execution
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.21 Bcc (Branch relative if Condition satisfied)
8.21
F2MC-16FX Family
Bcc (Branch relative if Condition satisfied)
Each instruction causes a branch if the condition determined for that
instruction is satisfied.
Control is transferred to the address resulting from word-adding the sign-extended data,
specified by the operand, to the address of the instruction following the BBcc instruction.
● Assembler format:
BZ/BEQ
rel
BNZ/BNE
rel
BC/BLO
rel
BNC/BHS
rel
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+2+rel
[Word addition]
If the condition is not satisfied:
(PC) ← (PC)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
116
Byte count:
2
Cycle count:
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.21 Bcc (Branch relative if Condition satisfied)
2
F MC-16FX Family
● Branch instruction and condition:
Bcc
Condition
Bcc
Condition
BZ/ BNZ/ BC/ BNC/
BEQ BNE BLO BHS
BN
BP
BV
BNV
BT
BNT
BRA
Z=1
N=1
N=0
V=1
V=0
T=1
T=0
Always
satisfied
Z=0
BLT
C=1
C=0
BGE
V xor N = 1 V xor N = 0
BLE
BGT
(V xor N) or (V xor N) or
Z=1
Z=0
BLS
BHI
C or Z = 1
C or Z = 0
● Example:
BHI 50H
In this example, a branch is caused if the C or Z flag of the condition code register (CCR) is
equal to "0" (condition satisfied).
PC
E 2
0 0
CCR 0 1 0 1 0
+(2+50)
C or Z = 0, then
PC
E 2
5 2
CCR 0 1 0 1 0
T N Z V C
T N Z V C
Before execution
After execution
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.22 CALL (Call Subroutine)
8.22
F2MC-16FX Family
CALL (Call Subroutine)
Cause a branch to the address specified by the operand. By executing the RET
instruction in the subroutine to which control has been transferred, control
returns to the instruction following the CALL instruction.
● Assembler format:
CALL @ear
CALL @eam
CALL addr16
● Operation:
(SP) ← (SP)–2
[Word subtraction], ((SP)) ← (PC)+<Byte count>
(PC) ← <Operand>
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
118
Operand
@ear
@eam
addr16
Byte count
2
2+
3
Cycle count
3
5
3
Odd address correction
1
1+1
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.22 CALL (Call Subroutine)
2
F MC-16FX Family
● Example:
CALL @@RW0
In this example, a branch is caused to the address (DC08H) indicated by the word data at the
address (F340H) specified by the operand (@@RW0) after the address (E55AH) of the next
instruction has been pushed to the stack specified by SP.
PC
E5 58
RW0
F3 40
SP
01 24
PC
DC 08
RW0
F3 40
Memory
SP
01 22
Memory
D C
0 8
F341
F340
D C
0 8
F341
F340
× ×
× ×
× ×
0124
0123
0122
× ×
0124
0123
0122
Before execution
CM44-00203-3E
SP
SP
E 5
5 A
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.23 CALLP (Call Physical Address)
8.23
F2MC-16FX Family
CALLP (Call Physical Address)
Cause a branch to the physical address specified by the operand. By
executing the RETP instruction in the subroutine to which control has been
transferred, control returns to the instruction following the CALLP instruction.
The program counter bank register (PCB) stores the most significant byte of the data specified
by the operand.
● Assembler format:
CALLP @ear
CALLP @eam
CALLP addr24
● Operation:
(SP) ← (SP)–2
[Word subtraction], ((SP)) ← (PCB)
(SP) ← (SP)–2
[Word subtraction], ((SP)) ← (PC)+<Byte count>
[Zero extension]
(PCB) ← Physical address to branch to (High-order byte)
(PC) ← Physical address to branch to (Low-order word)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
120
Operand
@ear
@eam
addr24
Byte count
2
2+
4
Cycle count
5
7
4
Odd address correction
5
2+1
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.23 CALLP (Call Physical Address)
2
F MC-16FX Family
● Example:
CALLP 080711H
In this example, a branch is caused to address 080711H after PCB and the address (4349H) of
the next instruction have been pushed to the stack specified by USB and SP. The most
significant byte (08H) in the operand is set to PCB.
PC
43 45
PCB
SP
F9 00
AD
USB
CCR
×
0
15
PC
07 11
PCB
SP
08
×××××
CCR
Memory
×
×
×
×
×
×
×
×
×
×
×
0
15
×××××
Memory
15F900
15F8FF
15F8FE
15F8FD
15F8FC
Before execution
CM44-00203-3E
USB
I S T N Z V C
I S T N Z V C
SP
F8 FC
× ×
SP
0
A
4
4
0
D
3
9
15F900
15F8FF
15F8FE
15F8FD
15F8FC
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.24 CALLV (Call Vectored Subroutine)
8.24
F2MC-16FX Family
CALLV (Call Vectored Subroutine)
Cause a branch to the address pointed to by the interrupt vector specified by
the operand. By executing the RET instruction in the subroutine to which
control has been transferred, control returns to the instruction following the
CALLV instruction.
The RET instruction is the same as that used with the CALL instruction.
● Assembler format:
CALLV #vct4
● Operation:
(SP) ← (SP)–2
((SP)) ← (PC) + 1
[Word subtraction]
(PC) ← Vector address
Note:
When the value of the program counter bank register (PCB) is equal to upper 8 bits of the
interrupt vector table register (TBR:TB[23:16]) and lower 6 bits of the TBR (TBR:TB[15:0])
is 111111B, the vector area for "CALLV #vct4" instruction is also used as the vector area
for "INT #vct8" (#0 to #7) instruction. (See Table 8.24-1 .)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
122
Byte count:
1
Cycle count:
5
Odd address correction:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.24 CALLV (Call Vectored Subroutine)
2
F MC-16FX Family
● Example:
CALLV #15
In this example, a branch is caused to the address specified by the interrupt vector of #15 after
the address (F4A8H) of the next instruction has been pushed to the stack specified by SP.
PC
F4 A7
SP
01 02
PC
E1 54
Memory
SP
SP
01 00
Memory
E 1
5 4
FFE1
FFE0
E 1
5 4
FFE1
FFE0
× ×
× ×
× ×
0102
0101
0100
× ×
0102
0101
0100
Before execution
F 4
A 8
SP
After execution
Table 8.24-1 CALLV Vector List
Instruction
Vector address L*
Vector address H*
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
* : XX is replaced by the value of the program counter bank register (PCB).
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.25 CBNE (Compare Byte Data and Branch if not Equal)
8.25
F2MC-16FX Family
CBNE (Compare Byte Data and Branch if not Equal)
Perform byte comparison on the first and second operands (8-bit immediate
data) and cause a branch if the first and second operands are not equal. A
branch is not taken if the first and second operands are equal.
Control is transferred to the address equal to the address of the instruction following the CBNE
instruction plus the word value resulting from sign-extending the third operand.
Note that, when the first operand is @PC + disp16, the operand address is equal to the "address
of the location containing the machine instruction for the CBNE instruction + 4 + disp16", not
the "address of the location containing the machine instruction for the instruction following the
CBNE instruction 4 + disp16".
● Assembler format:
CBNE A,#imm8,rel
CBNE ear,#imm8,rel
CBNE eam,#imm8,rel
● Operation:
(First operand)≠imm8
[Byte comparison] : (PC) ← (PC)+<Byte count>+rel
(First operand)=imm8
[Byte comparison] : (PC) ← (PC)+<Byte count>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
124
N:
Set when the MSB of the compare operation result is "1", cleared otherwise.
Z:
Set when (First operand) = imm8, cleared otherwise.
V:
Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C:
Set when a borrow has occurred as a result of the compare operation, cleared
otherwise.
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
2
F MC-16FX Family
CHAPTER 8 DETAILED INSTRUCTIONS
8.25 CBNE (Compare Byte Data and Branch if not Equal)
● Byte count and cycle count:
First operand
A
ear
eam
Second operand
#imm8
#imm8
#imm8
Third operand
rel
rel
rel
Byte count
3
4
4+
Cycle count
5
4
5
● Example:
CBNE A, #0F4H,55H
In this example, the low-order byte data (F3H) of AL is compared with the 8-bit immediate
data (F4H). A branch is caused because the first and second operands are not equal.
A
AH
AL
×× ××
00 F3
PC
CCR
E3 10
F3H≠F4H
A
AH
AL
×× ××
00 F3
+(55H+Byte count: 3)
×××××
T N Z V C
Before execution
CM44-00203-3E
PC
CCR
E3 68
×
1 0 0 1
T N Z V C
After execution
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8.26 CLRB (Clear Bit)
8.26
F2MC-16FX Family
CLRB (Clear Bit)
Clear the bit specified by bp to "0", in the memory location specified by the
operand.
● Assembler format:
CLRB dir:bp
CLRB io:bp
CLRB addr16:bp
● Operation:
(Operand) b ← 0
[Bit transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Operand
dir:bp
io:bp
addr16:bp
Byte count
3
3
4
Cycle count
3
3
3
● Example:
CLRB 0AA55H:3
In this example, bit 3 in data (FFH) at address AA55H is set to "0".
Memory
Memory
× ×
× ×
F F
126
AA55
F 7
AA55
× ×
× ×
Before execution
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.27 CMP (Compare Byte Data of Destination and Source)
2
F MC-16FX Family
8.27
CMP (Compare Byte Data of Destination and
Source)
Compare the byte data specified by the first operand with that specified by the
second operand and set the flag changes in the condition code register (CCR).
The data specified by the first operand and that by the second operand are not changed.
If only the accumulator (A) is specified as an operand, AH and AL are compared.
● Assembler format:
(1)
CMP A,#imm8
CMP A,ear
(2)
CMP A,eam
CMP A
● Operation:
(1)
(First operand)–(Second operand)
[Byte comparison]
(2)
(AH)–(AL)
[Byte comparison]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
A
Second operand
#imm8
ear
eam
–
Byte count
2
2
2+
1
Cycle count
1
1
2
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.27 CMP (Compare Byte Data of Destination and Source)
F2MC-16FX Family
● Example:
CMP A,#7FH
In this example, the low-order byte data (22H) of AL is compared with the 8-bit immediate data
(7FH).
AH
A
AL
A0 22
×× ××
CCR
×××××
AH
A
×× ××
CCR
128
×
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
A0 22
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.28 CMPL (Compare Long Word Data of Destination and
Source)
2
F MC-16FX Family
8.28
CMPL (Compare Long Word Data of Destination and
Source)
Compare the long word data specified by the first operand with that specified
by the second operand and set the result in the condition code register (CCR).
The data specified by the first operand and that specified by the second are not changed.
● Assembler format:
CMPL A,#imm32
CMPL A,ear
CMPL A,eam
● Operation:
(First operand)–(Second operand)
[Long word comparison]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
Second operand
#imm32
ear
eam
Byte count
5
2
2+
Cycle count
2
2
3
Odd address correction
0
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.28 CMPL (Compare Long Word Data of Destination and
Source)
● Example:
F2MC-16FX Family
CMPL A,#12345678H
In this example, the long-word data (12345678H) of the accumulator (A) is compared with the
32-bit immediate data (12345678H).
A
AH
AL
12 34
56 78
CCR
×××××
A
AH
AL
12 34
56 78
CCR
130
0 1 0 0
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.29 CMPW (Compare Word Data of Destination and Source)
2
F MC-16FX Family
8.29
CMPW (Compare Word Data of Destination and
Source)
Compare the word data specified by the first operand with that specified by the
second operand and set the result in the condition code register (CCR).
The data specified by the first operand and that specified by the second operand are not
changed. If only A is specified as an operand, AH and AL are compared.
● Assembler format:
(1)
CMPW A,#imm16
CMPW A,ear
(2)
CMPW A,eam
CMPW A
● Operation:
(1)
(First operand)–(Second operand)
[Word comparison]
(2)
(AH)–(AL)
[Word comparison]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
A
Second operand
#imm16
ear
eam
–
Byte count
3
2
2+
1
Cycle count
1
1
2
1
Odd address correction
0
0
1
0
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CHAPTER 8 DETAILED INSTRUCTIONS
8.29 CMPW (Compare Word Data of Destination and Source)
F2MC-16FX Family
● Example:
CMPW A,RW0
In this example, the word data (ABCDH) of AL is compared with the word data (ABCCH) of
RW0.
A
AH
AL
×× ××
AB CD
RW0
CCR
AB CC
×××××
A
AH
AL
×× ××
AB CD
RW0
CCR
132
×
0 0 0 0
T N Z V C
T N Z V C
Before execution
AB CC
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.30 CWBNE (Compare Word Data and Branch if not Equal)
2
F MC-16FX Family
8.30
CWBNE (Compare Word Data and Branch if not
Equal)
Perform word comparison on the first and second operands (16-bit immediate
data) and cause a branch if the first and second operands are not equal. A
branch is not taken if the first and second operands are equal.
Control is transferred to the address equal to the address of the instruction following
CWBNE instruction plus the word data resulting from sign-extending the third operand.
When the first operand is @PC + disp16, the operand address is equal to the "address of
location containing the machine instruction for the CWBNE instruction + 4 + disp16", not
"address of the location containing the machine instruction for the instruction following
CWBNE instruction + disp16".
the
the
the
the
● Assembler format:
CWBNE A,#imm16,rel
CWBNE ear,#imm16,rel
CWBNE eam,#imm16,rel
● Operation:
(First operand)≠imm16
[Word comparison] : (PC) ← (PC)+<Byte count>+rel
(First operand)=imm16
[Word comparison] : (PC) ← (PC)+<Byte count>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the comparison result is "1", cleared otherwise.
Z:
Set when (First operand) = imm16, cleared otherwise.
V:
Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C:
Set when a borrow has occurred as a result of the compare operation, cleared
otherwise.
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.30 CWBNE (Compare Word Data and Branch if not Equal)
F2MC-16FX Family
● Byte count and cycle count:
First operand
A
ear
eam
Second operand
#imm16
#imm16
#imm16
Third operand
rel
rel
rel
Byte count
4
5
5+
Cycle count
5
5
6
Odd address correction
0
0
1
● Example:
CWBNE A,#0E5E5H,30H
In this example, the word data (5EE5H) of AL is compared with the 16-bit immediate data
(E5E5H). A branch is caused because the first and second operands are not equal.
AH
A
AL
5E E5
×× ××
PC
CCR
D8 56
×××××
AH
A
×× ××
PC
CCR
134
D8 8A
×
0 0 0 0
T N Z V C
T N Z V C
Before execution
AL
5E E5
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.31 DBNZ (Decrement Byte Data and Branch if not Zero)
2
F MC-16FX Family
8.31
DBNZ (Decrement Byte Data and Branch if not Zero)
Decrement the data specified by the first operand by one byte, and if the result
is not equal to 00H, a branch is generated. If the decrement result is equal to
00H, control is transferred to the next instruction.
Control is transferred to the address equal to the address of the instruction following the DBNZ
instruction plus the word data resulting from sign-extending the data specified by the second
operand. When the first operand is @PC + disp16, the operand address is equal to the "address
of the location containing the machine instruction for the DBNZ instruction + 4 + disp16", not
the "address of the location containing the machine instruction for the instruction following the
DBNZ instruction + disp16".
● Assembler format:
DBNZ ear,rel
DBNZ eam,rel
● Operation:
(ea) ← (ea)–1
[Byte subtraction]
if (ea) ≠ 0 : (PC) ← (PC)+<Byte count>+rel
if (ea) = 0 : (PC) ← (PC)+<Byte count>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
ear
eam
Second operand
rel
rel
Byte count
3
3+
Cycle count
5
6
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CHAPTER 8 DETAILED INSTRUCTIONS
8.31 DBNZ (Decrement Byte Data and Branch if not Zero)
F2MC-16FX Family
● Example:
DBNZ @RW0+2,40H
In this example, the byte data (03H) at the address (0122H) specified by the first operand
(@RW0+2) is decremented by one. A branch is caused because the operation result is not "0".
PC
E3 58
PC
E3 9C
RW0
01 20
RW0
01 20
CCR 0 0 0 0 1
T N Z V C
CCR 0 0 1 0 1
T N Z V C
Memory
RW0+2
0
3
× ×
× ×
Memory
0122
0121
0120
Before execution
136
RW0+2
0
2
× ×
× ×
0122
0121
0120
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
2
F MC-16FX Family
8.32
DEC (Decrement Byte Data)
CHAPTER 8 DETAILED INSTRUCTIONS
8.32 DEC (Decrement Byte Data)
Decrement the byte data specified by the operand by one and store the result
in the operand.
● Assembler format:
DEC ear
DEC eam
● Operation:
(ea) ← (ea)–1
[Byte subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
Operand
ear
eam
Byte count
2
2+
Cycle count
1
3
● Example:
DEC R1
In this example, the byte data (80H) of R1 is decremented by one.
R1
CCR
80
×××××
T N Z V C
Before execution
CM44-00203-3E
R1
CCR
7F
×
0 0 1
×
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.33 DECL (Decrement Long Word Data)
8.33
F2MC-16FX Family
DECL (Decrement Long Word Data)
Decrement the long word data specified by the operand by one and restore the
result in the operand.
● Assembler format:
DECL ear
DECL eam
● Operation:
(ea) ← (ea)–1
[Long word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
Operand
ear
eam
Byte count
2
2+
Cycle count
2
4
Odd address correction
0
2
● Example:
DECL RL0
In this example, the long word data (00001000H) of RL0 is decremented by one.
RL0
0 0 0 0
CCR
10 00
×××××
RL0
00 00
CCR
T N Z V C
Before execution
138
0F FF
×
0 0 0
×
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.34 DECW (Decrement Word Data)
2
F MC-16FX Family
8.34
DECW (Decrement Word Data)
Decrement the word data specified by the operand by one and restore the
result in the operand.
● Assembler format:
DECW ear
DECW eam
● Operation:
(ea) ← (ea)–1
[Word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
Operand
ear
eam
Byte count
2
2+
Cycle count
1
3
Odd address correction
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.34 DECW (Decrement Word Data)
F2MC-16FX Family
● Example:
DECW @RW0+1000H
In this example, the word data (0001H) at the address (7780H) specified by the operand
(@RW0+1000H) is decremented by one.
67 80
RW0
CCR
RW0+1000H
×××××
CCR
×
0 0 1
×
T N Z V C
T N Z V C
Memory
Memory
0
0
0
1
× ×
7781
7780
777F
Before execution
140
67 80
RW0
0
0
RW0+1000H
0
0
× ×
7781
7780
777F
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.35 DIV (Divide Word Data by Byte Data)
2
F MC-16FX Family
8.35
DIV (Divide Word Data by Byte Data)
Divide the word data specified by the first operand by the byte data specified
by the second operand and store the quotient (byte data) in the first operand
and the remainder (byte data) in the second operand. The operation assumes
that the values are signed ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of AL and
the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The operation
assumes that the values are signed ones.
If division by zero occurs, the second operand or AL retains the value it had immediately
before the instruction was executed. If an overflow occurs, the contents of AL are undefined.
● Assembler format:
(1)
DIV A,ear
(2)
DIV A
DIV A,eam
● Operation:
(1)
word (A) / byte (ea), Quotient → byte (A), Remainder → byte (ea)
(2)
word (AH) / byte (AL), Quotient → byte (AL), Remainder → byte (AH)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
First operand
A
A
A
Second operand
–
ear
eam
Byte count
2
2
2+
Cycle count
CM44-00203-3E
Overflow: 5
Overflow: 5
Overflow: 6
Normal termination: 11 Normal termination: 11 Normal termination: 13
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CHAPTER 8 DETAILED INSTRUCTIONS
8.35 DIV (Divide Word Data by Byte Data)
F2MC-16FX Family
● Example:
DIV A
In this example, the word data (1357H) of AH is divided by the byte data (AAH) of AL with a
sign. The quotient is set to the low-order byte of AL and the remainder to the low-order byte of
AH.
A
AL
00 AA
AH
13 57
CCR
×××××
A
AH
00 31
CCR
142
00 C7
×××
0 0
T N Z V C
T N Z V C
Before execution
AL
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.36 DIVW (Divide Long Word Data by Word Data)
2
F MC-16FX Family
8.36
DIVW (Divide Long Word Data by Word Data)
Divide the long word data specified by the first operand (A) by the word data
specified by the second operand and store the quotient (word data) in A and
the remainder (word data) in the second operand. The operation assumes that
the values are signed ones.
If division by zero occurs, the second operand or AL retains the value it had immediately
before the instruction was executed. If an overflow occurs, the contents of AL are undefined.
● Assembler format:
DIVW A,ear
DIVW A,eam
● Operation:
long word (A) / word (ea), Quotient → word (A), Remainder → word (ea)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
Overflow: 5
Normal termination: 19
Overflow: 6
Normal termination: 21
Odd address correction
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.36 DIVW (Divide Long Word Data by Word Data)
F2MC-16FX Family
● Example:
DIVW A,7254H
In this example, the long word data (00001357H) of the accumulator (A) is divided by the word
data (00AAH) at address 7254H with a sign. The quotient is set to AL and the remainder to
address 7254H.
A
AH
AL
00 00
13 57
CCR
×××××
A
AL
00 1D
AH
00 00
CCR
×××
T N Z V C
T N Z V C
Memory
0 0
A A
Memory
7255
7254
Before execution
144
0 0
0 0
1 5
7255
7254
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.37 DIVU (Divide unsigned Word Data by unsigned Byte Data)
2
F MC-16FX Family
8.37
DIVU (Divide unsigned Word Data by unsigned Byte
Data)
Divide the word data specified by the first operand by the byte data specified
by the second operand and store the quotient (byte data) in the first operand
and the remainder (byte data) in the second operand. The operation assumes
that the values are unsigned ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of AL and
the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The operation
assumes that the values are unsigned ones.
If an overflow or division by zero occurs, the second operand or AL retains the value it had
immediately before the instruction was executed.
● Assembler format:
(1)
DIVU A,ear
(2)
DIVU A
DIVU A,eam
● Operation:
(1)
word (A) / byte (ea), Quotient → byte (A), Remainder → byte (ea)
(2)
word (AH) / byte (AL), Quotient → byte (AL), Remainder → byte (AH)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
Second operand
–
ear
eam
Byte count
1
2
2+
Cycle count
Overflow: 4
Normal termination: 9
Overflow: 4
Overflow: 5
Normal termination: 9 Normal termination: 11
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CHAPTER 8 DETAILED INSTRUCTIONS
8.37 DIVU (Divide unsigned Word Data by unsigned Byte Data)
F2MC-16FX Family
● Example:
DIVU A
In this example, the word data (1357H) of AH is divided by the byte data (AAH) of AL without
a sign. The quotient is set to AL and the remainder to AH.
A
AH
AL
13 57
00 AA
CCR
×××××
A
AH
AL
00 15
00 1D
CCR
146
0 0
T N Z V C
T N Z V C
Before execution
×××
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.38 DIVUW (Divide unsigned Long Word Data by unsigned
Word Data)
2
F MC-16FX Family
8.38
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data)
Divide the long word data specified by the first operand (A) by the word data
specified by the second operand and store the quotient (word data) in A and
the remainder (word data) in the second operand. The operation assumes that
the values are unsigned ones.
If an overflow or division by zero occurs, the second operand or AL retains the value it had
immediately before the instruction was executed.
● Assembler format:
DIVUW A,ear
DIVUW A,eam
● Operation:
long word (A) / word (ea), Quotient → word (A), Remainder → word (ea)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor
is zero, cleared otherwise.
C:
Set when the divisor is zero, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
Overflow: 4
Normal termination: 17
Overflow: 5
Normal termination: 19
Odd address correction
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.38 DIVUW (Divide unsigned Long Word Data by unsigned
Word Data)
● Example:
F2MC-16FX Family
DIVUW A,7254H
In this example, the long word data (00001357H) of the accumulator (A) is divided by the word
data (00AAH) at address 7254H without a sign. The quotient is set to AL and the remainder to
address 7254H.
A
AH
AL
00 00
13 57
CCR
×××××
A
AH
AL
00 00
00 1D
CCR
0 0
A A
Memory
7255
7254
Before execution
148
0 0
T N Z V C
T N Z V C
Memory
×××
0 0
1 5
7255
7254
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.39 DWBNZ (Decrement Word Data and Branch if not Zero)
2
F MC-16FX Family
8.39
DWBNZ (Decrement Word Data and Branch if not
Zero)
Decrement the data specified by the first operand by one word, and if the result
is not equal to zero, cause a branch. If the decrement result is equal to zero,
control is transferred to the instruction following the DWBNZ instruction.
Control is transferred to the address equal to the address of the instruction following the
DWBNZ instruction plus the word data resulting from sign-extending the data specified by the
second operand.
When the first operand is @PC + disp16, the operand address is equal to the "address of the
location containing the machine instruction for the DWBNZ instruction + 4 + disp16", not the
"address of the location containing the machine instruction for the instruction following the
DWBNZ instruction + disp16".
● Assembler format:
DWBNZ ear,rel
DWBNZ eam,rel
● Operation:
(First operand) ← (First operand)–1
When (First operand)≠0,
[Word subtraction]
(PC) ← (PC)+<Byte count>+second operand
(PC) ← (PC)+<Byte count>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
ear
eam
Second operand
rel
rel
Byte count
3
3+
Cycle count
5
6
Odd address correction
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.39 DWBNZ (Decrement Word Data and Branch if not Zero)
F2MC-16FX Family
● Example:
DWBNZ RW0,30H
In this example, the word data (0001H) of RW0 is decremented by one. A branch is not caused
because the operation result is "0".
PC
F8 20
PC
F8 23
RW0
00 01
RW0
00 00
CCR
×××××
T N Z V C
Before execution
150
CCR
×
0 0 0
×
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.40 EXT (Sign Extend from Byte Data to Word Data)
2
F MC-16FX Family
8.40
EXT (Sign Extend from Byte Data to Word Data)
Extend the lower byte data of AL to word data as a signed binary number.
● Assembler format:
EXT
● Operation:
When bit 7 of AL=0, bits 8 to 15 of AL ← 00H
When bit 7 of AL≠0, bits 8 to 15 of AL ← FFH
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z:
Set when the sign-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
EXT
In this example, the high-order byte (bits 8 to 15) of AL is extended with FFH because the most
significant bit of the low-order byte data (80H) of AL is "1".
AH
A
AL
×× 80
×× ××
CCR
×××××
AH
A
×× ××
CCR
CM44-00203-3E
×
1 0
××
T N Z V C
T N Z V C
Before execution
AL
FF 80
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.41 EXTW (Sign Extend from Word Data to Long Word Data)
8.41
F2MC-16FX Family
EXTW (Sign Extend from Word Data to Long Word
Data)
Extend the low-order word data of A to long word data as a signed binary
number.
● Assembler format:
EXTW
● Operation:
When bit15 of A=0, (AH) ← 0000H
When bit15 of A≠0, (AH) ← FFFFH
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z:
Set when the sign-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
EXTW
In this example, AH (bits 16 to 31 of A) is extended with FFFFH because the most significant
bit of the word data (FF80H) of AL is "1".
AH
A
AL
FF 80
×× ××
CCR
×××××
A
AH
FF FF
CCR
152
×
1 0
××
T N Z V C
T N Z V C
Before execution
AL
FF 80
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.42 FILS, FILSI (Fill String Byte)
2
F MC-16FX Family
8.42
FILS, FILSI (Fill String Byte)
Transfer the contents of AL to the RW0-byte area that starts from the address
whose high-order eight bits are specified by the bank register specified by
<bank> and whose low-order 16 bits are specified by the contents of AH.
If RW0 is equal to zero, transfer is not performed. If an interrupt occurs during the execution
of the instruction, the execution of the instruction is suspended. After the interrupt has been
handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank> is
omitted, DTB is assumed.
● Assembler format:
FILS
[<bank>]
FILSI [<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL) [Byte transfer], (AH) ← (AH)+1,
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
2
Cycle count:
(RW0 + 1) / 2
Odd address correction:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.42 FILS, FILSI (Fill String Byte)
F2MC-16FX Family
● Example:
FILS
In this example, the low-order byte data (E5H) of AL is transferred from the address
(94BC00H) specified by DTB and AH to the number of bytes (0100H) specified by RW0.
A
AH
BC 00
RW0
01 00
AL
00 E5
DTB
CCR
94
A
AH
BD 00
RW0
00 00
×××××
CCR
T N Z V C
×
××
× ×
AH
1 0
94BC02
94BC01
94BC00
94BD00
94BCFF
94BCFE
E 5
E 5
...
...
...
...
94BD00
94BCFF
94BCFE
Before execution
154
94
Memory
× ×
× ×
× ×
AH
DTB
T N Z V C
Memory
× ×
× ×
× ×
AL
00 E5
E 5
E 5
E 5
94BC02
94BC01
94BC00
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.43 FILSW, FILSWI (Fill String Word)
2
F MC-16FX Family
8.43
FILSW, FILSWI (Fill String Word)
Transfer the contents of AL to the RW0-word area that starts from the address
whose high-order eight bits are specified by the bank register specified by
<bank> and whose low-order 16 bits are specified by the contents of AH.
If RW0 is equal to zero, transfer is not performed. If an interrupt occurs during the execution
of the instruction, the execution of the instruction is suspended. After the interrupt has been
handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank> is
omitted, DTB is assumed.
● Assembler format:
FILSW
[<bank>]
FILSWI [<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL) [Word transfer], (AH) ← (AH)+2,
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; RW0 cycle(s) in all other cases
Odd address correction:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.43 FILSW, FILSWI (Fill String Word)
F2MC-16FX Family
● Example:
FILSW ADB
In this example, the word data (E55EH) of AL is transferred from the address (49ABFEH)
specified by ADB and AH to the number of words (0080H) specified by RW0.
A
AH
AB FE
RW0
00 80
AL
E5 5E
ADB
CCR
49
A
AH
AC FE
RW0
00 00
×××××
CCR
T N Z V C
×
××
× ×
× ×
AH
0 0
49AC00
49ABFF
49ABFE
49ACFF
49ACFE
49ACFD
E 5
...
...
...
...
49ACFF
49ACFE
49ACFD
Before execution
156
49
Memory
× ×
× ×
× ×
AH
ADB
T N Z V C
Memory
× ×
× ×
× ×
AL
E5 5E
5 E
E 5
5 E
49AC00
49ABFF
49ABFE
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.44 INC (Increment Byte Data (Address Specification))
2
F MC-16FX Family
8.44
INC (Increment Byte Data (Address Specification))
Increment the byte data specified by the operand by one and restore the result
in the operand.
● Assembler format:
INC ear
INC eam
● Operation:
(Operand) ← (Operand)+1
[Byte increment]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
Operand
ear
eam
Byte count
2
2+
Cycle count
1
3
● Example:
INC R0
In this example, "1" is added to the byte data (FFH) of R0.
R0
CCR
FF
×××××
T N Z V C
Before execution
CM44-00203-3E
00
R0
CCR
×
0 1 0
×
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.45 INCL (Increment Long Word Data)
8.45
F2MC-16FX Family
INCL (Increment Long Word Data)
Increment the long word data specified by the operand by one and restore the
result in the operand.
● Assembler format:
INCL ear
INCL eam
● Operation:
(Operand) ← (Operand)+1
[Long word increment]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
Operand
ear
eam
Byte count
2
2+
Cycle count
2
4
Odd address correction
0
2
● Example:
INCL RL0
In this example, "1" is added to the long word data (7FFFFFFFH) of RL0.
RL0
AH
AL
7F FF
FF FF
CCR
×××××
RL0
AH
AL
80 00
00 00
CCR
158
1 0 1
×
T N Z V C
T N Z V C
Before execution
×
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.46 INCW (Increment Word Data)
2
F MC-16FX Family
8.46
INCW (Increment Word Data)
Increment the word data specified by the operand by one and restore the result
in the operand.
● Assembler format:
INCW ear
INCW eam
● Operation:
(Operand) ← (Operand)+1
[Word increment]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
Operand
ear
eam
Byte count
2
2+
Cycle count
1
3
Odd address correction
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.46 INCW (Increment Word Data)
F2MC-16FX Family
● Example:
INCW @RW0+
In this example, "1" is added to the word data (0101H) at the address (0354H) specified by the
operand (@RW0+).
03 54
RW0
CCR
×××××
CCR
0 0 0
×
T N Z V C
Memory
Memory
0
0
1
1
0357
0356
0355
0354
Before execution
160
×
T N Z V C
× ×
× ×
RW0
03 56
RW0
RW0
× ×
× ×
0
0
1
2
0357
0356
0355
0354
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.47 INT (Software Interrupt)
2
F MC-16FX Family
8.47
INT (Software Interrupt)
Cause a branch to the interrupt handling routine at the specified address in the
bank 0FFH. By executing the RETI instruction in the interrupt handling routine
to which control has been transferred, control returns to the instruction
following this instruction.
● Assembler format:
INT addr16
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR and ADB are saved as a set, DPR as
the high-order byte and ADB as the loworder byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+3), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← 0FFH, (PC) ← addr16
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I:
Cleared
S:
Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count:
3
Cycle count:
8
Odd address correction:
6
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CHAPTER 8 DETAILED INSTRUCTIONS
8.47 INT (Software Interrupt)
F2MC-16FX Family
● Example:
INT 020F2H
In this example, a branch is caused to the interrupt handling routine at address FF20F2H. FFH
is set to PCB.
A
AH
FF EE
DTB
99
DPR
BB
ILM
03
SSB
03
AL
DD CC
PCB
PC
88
77 66
ADB
CCR
AA
RP
I S T N Z V C
10
0 0 0 0 1 0 1
SSP
80 00
A
AH
FF EE
DTB
99
DPR
BB
ILM
03
SSB
03
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
162
PCB
PC
FF
20 F2
ADB
CCR
AA
I S T N Z V C
RP
0 1 0 0 1 0 1
10
SSP
7F F4
Memory
Memory
SSP
AL
DD CC
SSP
F
E
D
C
B
A
9
8
7
6
7
8
F
E
D
C
B
A
9
8
7
9
0
5
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.48 INT (Software Interrupt (Vector Specification))
2
F MC-16FX Family
8.48
INT (Software Interrupt (Vector Specification))
Cause a branch to the interrupt handling routine pointed to by the interrupt
vector specified by the operand.
● Assembler format:
INT #vct8
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR and ADB are saved as a set, DPR as
the high-order byte and ADB as the loworder byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+2), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0,
(PCB) ← Vector address (High-order byte)
(PC) ← Vector address (Low-order word)
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I:
Cleared
S:
Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count:
2
Cycle count:
12
Odd address correction:
6
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CHAPTER 8 DETAILED INSTRUCTIONS
8.48 INT (Software Interrupt (Vector Specification))
F2MC-16FX Family
● Example:
INT #11
In this example, a branch is caused to the interrupt handling routine specified by the interrupt
vector of #11.
AH
FF EE
A
DTB
99
DPR
BB
ILM
02
SSB
03
AL
DD CC
PCB
PC
88
77 66
ADB
CCR
AA
RP
I S T N Z V C
15
0 0 0 0 1 0 1
SSP
80 00
A
AH
FF EE
DTB
99
DPR
BB
ILM
02
SSB
03
Memory
PCB
PC
89
E7 95
ADB
CCR
AA
RP
I S T N Z V C
15
0 1 0 0 1 0 1
SSP
7F F4
Memory
8 9
E 7
9 5
FFFFD2
FFFFD1
FFFFD0
8 9
E 7
9 5
FFFFD2
FFFFD1
FFFFD0
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
F
E
D
C
B
A
9
8
7
6
5
8
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
SSP
×
×
×
×
×
×
×
×
×
×
×
×
Before execution
164
AL
DD CC
SSP
F
E
D
C
B
A
9
8
7
8
5
5
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.49 INT9 (Software Interrupt)
2
F MC-16FX Family
8.49
INT9 (Software Interrupt)
Cause a branch to the interrupt handling routine pointed to by the vector.
By executing the RETI instruction in the interrupt handling routine to which
control has been transferred, control returns to the instruction following this
instruction.
● Assembler format:
INT9
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR and ADB are saved as a set, DPR as
the high-order byte and ADB as the loworder byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB and PCB are saved as a set, DTB as the
high-order byte and PCB as the low-order
byte.]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+1), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0,
(PCB) ← Vector address (High-order byte)
(PC)
← Vector address (Low-order word)
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I:
Cleared
S:
Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
12
Odd address correction:
6
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CHAPTER 8 DETAILED INSTRUCTIONS
8.49 INT9 (Software Interrupt)
F2MC-16FX Family
● Example:
INT9
In this example, a branch is caused to the interrupt handling routine specified by the interrupt
vector of #9.
A
AH
AL
11 22
33 44
DTB
77
DPR
55
ILM
02
SSB
03
PCB
PC
88
99 AA
ADB
CCR
66
RP
I S T N Z V C
15
0 0 0 0 1 0 1
SSP
80 00
A
AH
AL
11 22
33 44
DTB
77
DPR
55
ILM
02
SSB
03
Memory
Memory
8 9
E 7
9 5
FFFFDA
FFFFD9
FFFFD8
8 9
E 7
9 5
FFFFDA
FFFFD9
FFFFD8
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
1
2
3
4
5
6
7
8
9
A
5
8
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
SSP
×
×
×
×
×
×
×
×
×
×
×
×
Before execution
166
PCB
PC
89
E7 95
ADB
CCR
66
RP
I S T N Z V C
15
0 1 0 0 1 0 1
SSP
7F F4
SSP
1
2
3
4
5
6
7
8
9
B
5
5
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.50 INTP (Software Interrupt)
2
F MC-16FX Family
8.50
INTP (Software Interrupt)
Cause a branch to the interrupt handling routine at the 24-bit physical address
specified by the operand. Any address in the entire 16Mbyte space can be
specified.
By executing the RETI instruction in the interrupt handling routine to which
control has been transferred, control returns to the instruction following this
instruction.
● Assembler format:
INTP addr24
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)
[DPR: High-order byte, ADB: Low-order byte]
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB)
[DTB: High-order byte, PCB: Low-order byte]
(SSP) ← (SSP)–2, ((SSP)) ← (PC+4), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0,
(PCB) ← Most significant byte of addr24,
(PC) ← Low-order word of addr24
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I:
Cleared
S:
Set
T, N, Z, V, and C: Unchanged
● Byte count and cycle count:
Byte count:
4
Cycle count:
8
Odd address correction:
6
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CHAPTER 8 DETAILED INSTRUCTIONS
8.50 INTP (Software Interrupt)
F2MC-16FX Family
● Example:
INTP 0C8F220H
In this example, a branch is caused to the interrupt handling routine at address C8F220H. C8H
is set to PCB.
A
AH
11 22
DTB
77
DPR
55
ILM
03
SSB
03
AL
33 44
PCB
PC
88
99 AA
ADB
CCR
66
RP
I S T N Z V C
10
0 0 0 0 1 0 1
SSP
80 00
A
AH
11 22
DTB
77
DPR
55
ILM
03
SSB
03
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
168
PCB
PC
C8
F2 20
ADB
CCR
66
I S T N Z V C
RP
0 1 0 0 1 0 1
10
SSP
7F F4
Memory
Memory
SSP
AL
33 44
SSP
1
2
3
4
5
6
7
8
9
A
7
8
1
2
3
4
5
6
7
8
9
E
0
5
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.51 JCTX (Jump Context)
2
F MC-16FX Family
8.51
JCTX (Jump Context)
Restore register contents or an address saved in memory.
● Assembler format:
JCTX @A
● Operation:
(temp)
← (AL)
(PS)
← ((temp)) : (temp)
← (temp)+2
(PC)
← ((temp)) : (temp)
← (temp)+2
(DTB), (PCB)
← ((temp)) : (temp)
← (temp)+2
(DPR), (ADB)
← ((temp)) : (temp)
← (temp)+2
(AL)
← ((temp)) : (temp)
← (temp)+2
(AH)
← ((temp))
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I: Stores bit 6 of the address indicated by AL.
S: Stores bit 5 of the address indicated by AL.
T: Stores bit 4 of the address indicated by AL.
N: Stores bit 3 of the address indicated by AL.
Z: Stores bit 2 of the address indicated by AL.
V: Stores bit 1 of the address indicated by AL.
C: Stores bit 0 of the address indicated by AL.
● Byte count and cycle count:
Byte count:
1
Cycle count:
23 cycles when the content of RP changes; 6 cycles in all other cases
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CHAPTER 8 DETAILED INSTRUCTIONS
8.51 JCTX (Jump Context)
F2MC-16FX Family
● Example:
JCTX @A
In this example, a context is returned from the address (09E020H) specified by DTB and AL.
AH
A
AL
E0 20
×× ××
A
DTB
09
DPR
PCB
PC
××
×× ××
××
××
ILM
RP
××
×× × × × × × × ×
ADB
CCR
I S T N Z V C
AL
B
5
2
0
8
E
0
0
8
1
6
A
09E02C
09E02B
09E02A
09E029
09E028
09E027
09E026
09E025
09E024
09E023
09E022
09E021
09E020
Before execution
170
DTB
80
DPR
08
ILM
07
AL
02 50
PCB
50
ADB
CE
RP
16
PC
88 01
CCR
I S T N Z V C
0 0 0 1 0 1 0
Memory
Memory
C
7
0
5
0
C
8
5
8
0
F
8
AH
CB 75
C
7
0
5
0
C
8
5
8
0
F
8
B
5
2
0
8
E
0
0
8
1
6
A
09E02C
09E02B
09E02A
09E029
09E028
09E027
09E026
09E025
09E024
09E023
09E022
09E021
09E020
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.52 JMP (Jump Destination Address)
2
F MC-16FX Family
8.52
JMP (Jump Destination Address)
Read the word data from the address specified by the operand and cause a
branch to the address specified by the word data.
● Assembler format:
JMP @A
JMP addr16
JMP @ear
JMP @eam
● Operation:
(PC) ← (Operand)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Operand
@A
@ear
@eam
addr16
Byte count
1
2
2+
3
Cycle count
2
2
4
2
Odd address correction
0
0
1
0
● Example:
JMP @@RW0+2
In this example, a branch is caused to the address (DB80H) specified by the word data at the
address (A0A2H) specified by the operand (@RW0+2).
PC
E0 00
PC
DB 80
RW0
A0 A0
RW0
A0 A0
Memory
RW0+2
D
8
B
0
× ×
× ×
Memory
A0A3
A0A2
A0A1
A0A0
Before execution
CM44-00203-3E
RW0+2
D
8
B
0
× ×
× ×
A0A3
A0A2
A0A1
A0A0
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.53 JMPP (Jump Destination Physical Address)
8.53
F2MC-16FX Family
JMPP (Jump Destination Physical Address)
If the operand is addr24, this instruction causes a branch to the physical
address specified by addr24.
If the operand is @ea, the instruction causes a branch to the physical address
specified by the contents of the operand.
● Assembler format:
(1)
JMPP addr24
(2)
JMPP @ear
JMPP @eam
● Operation:
(1):
(2):
(PC)
← Low-order word of addr24
(PCB)
← Most significant byte of addr24
(PC)
← (ea)
[Word transfer]
(PCB)
← (ea+2)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Operand
addr24
@ear
@eam
Byte count
4
2
2+
Cycle count
2
3
5
Odd address correction
0
0
1
● Example:
JMPP 0FFC850H
In this example, a branch is caused to FFC850H. FFH is set to PCB.
PC
12 48
PCB 3 4
Before execution
172
PC
C8 50
PCB F F
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.54 LINK (Link and Create New Stack Frame)
2
F MC-16FX Family
8.54
LINK (Link and Create New Stack Frame)
Store the current value of the frame pointer (RW3) in a stack and set a new
frame pointer. This allows an area for a new local variable to be reserved. This
instruction is used before a function is called.
● Assembler format:
LINK #imm8
● Operation:
(SP) ← (SP)–2 ; ((SP)) ← (RW3) ; (RW3) ← (SP) ; (SP) ← (SP)–imm8
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
2
Odd address correction:
1
● Example:
LINK #20H
In this example, RW3 is pushed to the stack specified by SP. Then, the 8-bit immediate data
(20H) is subtracted from the SP value (E020H).
SP
RW3
E0 22
A0 46
SP
RW3
Memory
SP
× ×
E0 20
Memory
A
4
E022
SP
Before execution
CM44-00203-3E
E0 00
0
6
E020
× ×
E000
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.55 LSL (Logical Shift Byte Data of Accumulator to Left)
8.55
F2MC-16FX Family
LSL (Logical Shift Byte Data of Accumulator to Left)
Shift the least significant byte data of the accumulator (A) to the left by the
number of bits specified by the second operand.
The least significant bit of A is set to "0". The bit last shifted out from the most significant bit
of the least significant byte data for A is stored in the carry flag (C).
● Assembler format:
LSL A,R0
● Operation:
C
A
MSB
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T: Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
174
Byte count:
2
Cycle count:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.55 LSL (Logical Shift Byte Data of Accumulator to Left)
2
F MC-16FX Family
● Example:
LSL A,R0
In this example, the low-order byte data (FEH) of AL is shifted to the left by the number of bits
(2 bits) specified by R0.
AH
A
AL
×× FF
×× ××
R0
CCR
02
×××××
T N Z V C
Before execution
CM44-00203-3E
AH
A
×× ××
R0
AL
×× FC
02
1 0 ××
T N Z V C
After execution
CCR
FUJITSU MICROELECTRONICS LIMITED
×
175
CHAPTER 8 DETAILED INSTRUCTIONS
8.56 LSLL (Logical Shift Long Word Data of Accumulator to Left)
8.56
F2MC-16FX Family
LSLL (Logical Shift Long Word Data of Accumulator
to Left)
Shift the long word data of the accumulator (A) to the left by the number of bits
specified by the second operand.
The least significant bit of the accumulator (A) is set to "0". The bit last shifted out from the
most significant bit is stored in the carry flag (C).
● Assembler format:
LSLL A,R0
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T: Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
176
Byte count:
2
Cycle count:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
2
F MC-16FX Family
CHAPTER 8 DETAILED INSTRUCTIONS
8.56 LSLL (Logical Shift Long Word Data of Accumulator to Left)
● Example:
LSLL A,R0
In this example, the long word data (33333333H) of the accumulator (A) is shifted to the left by
the number of bits (2 bits) specified by R0.
A
AH
33 33
AL
33 33
R0
CCR
A
AH
CC CC
02
×××××
CCR
T N Z V C
Before execution
CM44-00203-3E
AL
CC CC
×
R0
02
1 0
×
0
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.57 LSLW (Logical Shift Word Data of Accumulator to Left)
8.57
F2MC-16FX Family
LSLW (Logical Shift Word Data of Accumulator to
Left)
Shift the low-order word data of the accumulator (A) to the left by one bit. The
least significant bit of the accumulator (A) is set to "0".
The least significant bit of the accumulator (A) is set to "0". The bit shifted out from the most
significant bit of the low-order word data for the accumulator (A) is stored in the carry flag (C).
● Assembler format:
LSLW A/SHLW A
● Operation:
C
MSB
AL
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T: Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the MSB of A.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
LSLW A
In this example, the word data (AA55H) of AL is shifted to the left by one bit.
AH
A
AL
AA 55
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
Before execution
178
AL
55 AA
×
0 0
×
1
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.58 LSLW (Logical Shift Word Data of Accumulator to Left)
2
F MC-16FX Family
8.58
LSLW (Logical Shift Word Data of Accumulator to
Left)
Shift the low-order word data of the accumulator (A) to the left by the number of
bits specified by the second operand.
The least significant bit of the accumulator (A) is set to "0". The bit last shifted out from the
most significant bit of the low-order word data for the accumulator (A) is stored in the carry
flag (C).
● Assembler format:
LSLW A,R0
● Operation:
C
MSB
AL
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T: Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.58 LSLW (Logical Shift Word Data of Accumulator to Left)
F2MC-16FX Family
● Example:
LSLW A,R0
In this example, the word data (AA55H) of AL is shifted to the left by the number of bits (4
bits) specified by R0.
A
AH
AL
×× ××
AA 55
R0
CCR
A
AH
AL
×× ××
A5 50
04
×××××
R0
CCR
T N Z V C
Before execution
180
×
1 0
04
×
0
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.59 LSR (Logical Shift Byte Data of Accumulator to Right)
2
F MC-16FX Family
8.59
LSR (Logical Shift Byte Data of Accumulator to
Right)
Shift the least significant byte data of the accumulator (A) to the right by the
number of bits specified by the second operand.
The most significant bit of the least significant byte of the accumulator (A) is set to "0". The
bit last shifted out from the least significant bit is stored in the carry flag (C).
● Assembler format:
LSR A,R0
● Operation:
AL
MSB
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.59 LSR (Logical Shift Byte Data of Accumulator to Right)
F2MC-16FX Family
● Example:
LSR A,R0
In this example, the low-order byte data (FFH) of AL is shifted to the right by the number of
bits (5 bits) specified by R0.
AH
A
AL
×× ××
××
R0
CCR
FF
05
×××××
AH
A
AL
×× ××
R0
182
07
05
CCR 1 1 0
T N Z V C
Before execution
××
×
1
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.60 LSRL (Logical Shift Long Word Data of Accumulator to
Right)
2
F MC-16FX Family
8.60
LSRL (Logical Shift Long Word Data of Accumulator
to Right)
Shift the long word data of the accumulator (A) to the right by the number of
bits specified by the second operand.
The most significant bit of the accumulator (A) is set to "0". The bit last shifted out from the
least significant bit of the accumulator (A) is stored in the carry flag (C).
● Assembler format:
LSRL A,R0
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.60 LSRL (Logical Shift Long Word Data of Accumulator to
Right)
● Example:
F2MC-16FX Family
LSRL A,R0
In this example, the long word data (33333333H) of the accumulator (A) is shifted to the right
by the number of bits (16 bits) specified by R0.
A
AH
33 33
AL
33 33
R0
CCR
A
AH
00 00
10
×××××
R0
CCR 1 0 0
T N Z V C
Before execution
184
AL
33 33
10
×
0
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.61 LSRW (Logical Shift Word Data of Accumulator to Right)
2
F MC-16FX Family
8.61
LSRW (Logical Shift Word Data of Accumulator to
Right)
Shift the low-order word data of the accumulator (A) to the right by one bit.
The most significant bit of the low-order word data of the accumulator (A) is set to "0". The
least significant bit is stored in the carry flag (C).
● Assembler format:
LSRW A/SHRW A
● Operation:
MSB
AL
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
R
*
–
*
I and S: Unchanged
T:
Stores the OR of the shifted-out data from the carry and the old T flag value.
N:
Cleared
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.61 LSRW (Logical Shift Word Data of Accumulator to Right)
F2MC-16FX Family
● Example:
LSRW A
In this example, the word data (AAAAH) of AL is shifted to the right by one bit.
AH
A
×× ××
AL
AA AA
CCR 1
×××
AH
A
0
×× ××
CCR 1 0 0
T N Z V C
Before execution
186
AL
55 55
×
0
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.62 LSRW (Logical Shift Word Data of Accumulator to Right)
2
F MC-16FX Family
8.62
LSRW (Logical Shift Word Data of Accumulator to
Right)
Shift the low-order word data of the accumulator (A) to the right by the number
of bits specified by the second operand.
The most significant bit of the low-order word data of the accumulator (A) is set to "0". The
bit last shifted out from the least significant bit is stored in the carry flag (C).
● Assembler format:
LSRW A,R0
● Operation:
MSB
AL
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S: Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is zero.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is zero.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.62 LSRW (Logical Shift Word Data of Accumulator to Right)
F2MC-16FX Family
● Example:
LSRW A,R0
In this example, the word data (AAAAH) of AL is shifted to the right by the number of bits (12
bits) specified by R0.
A
AH
AL
×× ××
AA AA
R0
CCR
A
AH
AL
×× ××
00 0A
0C
×××××
R0
CCR 1 0 0
T N Z V C
Before execution
188
0C
×
1
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.63 MOV (Move Byte Data from Source to Accumulator)
2
F MC-16FX Family
8.63
MOV (Move Byte Data from Source to Accumulator)
The value in AL is transferred to AH. And then 00H is transferred to the upper
bytes of AL; the byte data in the second operand is transferred to the lower
bytes of AL.
If the second operand is @A, transfer to AH is not performed.
● Assembler format:
MOV A,#imm8
MOV A,Ri
MOV A,@A
MOV A,dir
MOV A,@RLi + disp8
MOV A,addr16
MOV A,io
MOV A,brg1
MOV A,eam
MOV A,ear
● Operation:
(A) ← (Second operand)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
First operand
Second operand
A
A
A
#imm8 @A @RLi+disp8
A
A
A
A
A
A
A
io
addr16
Ri
dir
ear
eam
brg1
Byte count
2
2
3
2
3
1
2
2
2+
2
Cycle count
1
1
1
1
1
1
1
1
1
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.63 MOV (Move Byte Data from Source to Accumulator)
F2MC-16FX Family
● Example:
MOV A,0092H
In this example, the word data (A046H) of AL is transferred to AH, and then the byte data
(71H) at address 0092H is transferred to AL.
AH
A
AL
A0 46
×× ××
CCR
×××××
A
AH
A0 46
AL
00 71
×
CCR
7 1
Memory
0092
Before execution
190
××
T N Z V C
T N Z V C
Memory
0 0
7 1
0092
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.64 MOV (Move Byte Data from Accumulator to Destination)
2
F MC-16FX Family
8.64
MOV (Move Byte Data from Accumulator to
Destination)
Transfer the least significant byte data of the accumulator (A) to the address
specified by the first operand.
● Assembler format:
MOV dir,A
MOV Ri,A
MOV @RLi+disp8,A
MOV io,A
MOV addr16,A
MOV brg2,A
MOV ear,A
MOV eam,A
● Operation:
(First operand) ← (A)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
dir
@RLi+disp8 addr16
io
Ri
ear
eam
brg2
Second operand
A
A
A
A
A
A
A
A
Byte count
2
3
3
2
1
2
2+
2
Cycle count
1
1
1
1
1
1
1
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.64 MOV (Move Byte Data from Accumulator to Destination)
F2MC-16FX Family
● Example:
MOV R1,A
In this example, the low-order byte data (32H) of AL is transferred to R1.
AH
AL
A
×× ××
49 32
CCR
×××××
R1
AH
××
T N Z V C
A
CCR
×× ××
×
0 0
××
49 32
R1
32
T N Z V C
Before execution
192
AL
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After execution
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.65 MOV (Move Byte Immediate Data to Destination)
2
F MC-16FX Family
8.65
MOV (Move Byte Immediate Data to Destination)
Transfer the 8-bit immediate data specified by the second operand to the
address specified by the first operand.
When the first operand is @PC + disp16, the data is transferred to the "address of the location
containing the machine instruction for the MOV instruction + 4 + rel", not the "address of the
location containing the machine instruction for the instruction following the MOV instruction +
rel".
● Assembler format:
MOV RP,#imm8
MOV ILM,#imm8
MOV io,#imm8
MOV dir,#imm8
MOV ear,#imm8
MOV eam,#imm8
● Operation:
(First operand) ← imm8
● CCR:
If the data is transferred to a generalpurpose registers (R0 to R7) or bank
register
If the data is transferred to a register other
than the general-purpose registers (R0 to
R7) and the bank register
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
–
–
–
–
–
–
–
I, S, and T: Unchanged
N:
Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, N is set when
the MSB of the transferred data is "1", cleared otherwise.
Z:
Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, Z is set when the
transferred data is zero, cleared otherwise.
V and C:
Unchanged
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CHAPTER 8 DETAILED INSTRUCTIONS
8.65 MOV (Move Byte Immediate Data to Destination)
F2MC-16FX Family
● Byte count and cycle count:
First operand
RP
ILM
dir
io
ear
eam
Second operand
#imm8
Byte count
2
2
3
3
3
3+
Cycle count
19 when the content of RP
changes; 4 in all other cases
1
1
1
1
1
#imm8 #imm8 #imm8 #imm8 #imm8
● Example:
MOV 009FH,#22H
In this example, the 8-bit immediate data (22H) is transferred to address 009FH in bytes.
A
AH
AL
×× ××
×× ××
CCR
×××××
A
AH
AL
×× ××
×× ××
CCR
T N Z V C
T N Z V C
Memory
Memory
7 1
009F
Before execution
194
×××××
2 2
009F
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.66 MOV (Move Byte Data from Source to Destination)
2
F MC-16FX Family
8.66
MOV (Move Byte Data from Source to Destination)
Transfer the byte data specified by the second operand to the first operand.
MOV Ri, #imm8, described below, is an instruction contained in the basic page map (see C.1
Table C.2-1 ), with code different from that contained in MOV ear, #imm8.
● Assembler format:
MOV Ri,#imm8
MOV Ri,ear
MOV Ri,eam
MOV ear,Ri
MOV eam,Ri
● Operation:
(First operand) ← (Second operand)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
Ri
Ri
Ri
ear
eam
Second operand
#imm8
ear
eam
Ri
Ri
Byte count
2
2
2+
2
2+
Cycle count
1
1
1
1
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.66 MOV (Move Byte Data from Source to Destination)
F2MC-16FX Family
● Example:
MOV R3,@RW0
In this example, the byte data (71H) at the address (E001H) specified by the second operand
(@RW0) is transferred to R3.
RW0
R3
××
E0 01
CCR
Memory
7 1
×××××
T N Z V C
E001
Before execution
196
RW0
R3
71
E0 01
CCR
Memory
7 1
××
0 0 ×
T N Z V C
E001
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.67 MOV (Move Byte Data from AH to Memory)
2
F MC-16FX Family
8.67
MOV (Move Byte Data from AH to Memory)
Transfer the low-order byte data of AH to the memory location specified by the
contents of AL.
● Assembler format:
MOV @AL,AH
● Operation:
((AL)) ← (AH)
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
● Example:
MOV @AL,AH
In this example, the low-order byte data (22H) of AH is transferred to the address (E084H)
specified by the word data of AL in bytes.
A
AH
01 22
AL
E0 84
CCR
×××××
A
AH
01 22
CCR
0 0
××
Memory
Memory
E084
Before execution
CM44-00203-3E
×
T N Z V C
T N Z V C
7 1
AL
E0 84
2 2
E084
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.68 MOVB (Move Bit Data from Bit Address to Accumulator)
8.68
F2MC-16FX Family
MOVB (Move Bit Data from Bit Address to
Accumulator)
The value in AL is transferred to AH. And then transfer zeros to bits 8 to 15 of
the accumulator (A). 00H is transferred to bits 0 to 7 of A if the bit of the
address specified by the second operand is equal to 00H and FFH is transferred
if the bit is equal to "1".
● Assembler format:
MOVB A,addr16:bp
MOVB A,dir:bp
MOVB A,io:bp
● Operation:
If (Second operand)=0 : (A) ← 00H
[Byte transfer]
If (Second operand)=1 : (A) ← FFH
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the transferred bit is "1", cleared when "0".
Z:
Set when the transferred bit is "0", cleared when "1".
V and C:
Unchanged
● Byte count and cycle count:
198
First operand
A
A
A
Second operand
addr16:bp
dir:bp
io:bp
Byte count
4
3
3
Cycle count
1
1
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.68 MOVB (Move Bit Data from Bit Address to Accumulator)
2
F MC-16FX Family
● Example:
MOVB A,32H:3
In this example, 00FFH is set to AL because bit 3 of the byte data (7FH) at address 32H is equal
to "1".
AH
A
AL
×× ××
×× ××
CCR
×××××
AH
A
×× ××
CCR
1 0
××
Memory
Memory
× ×
CM44-00203-3E
×
T N Z V C
T N Z V C
7 F
AL
00 FF
× ×
0032
7 F
0032
× ×
× ×
Before execution
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.69 MOVB (Move Bit Data from Accumulator to Bit Address)
8.69
F2MC-16FX Family
MOVB (Move Bit Data from Accumulator to Bit
Address)
Transfer bit data 0 to the bit address specified by the first operand if the least
significant byte data of the accumulator (A) is 00H.
Bit data 1 is transferred to the bit address specified by the first operand if the
least significant byte data of A is not 00H.
● Assembler format:
MOVB addr16:bp,A
MOVB dir:bp,A
MOVB io:bp,A
● Operation:
If the byte data of (A) is 00H :
(First operand) b=0
[Bit transfer]
If the byte data of (A) is not 00H : (First operand) b=1
[Bit transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the byte data for A is "1", cleared otherwise.
Z:
Set when the byte data of A is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
200
First operand
addr16:bp
dir:bp
io:bp
Second operand
A
A
A
Byte count
4
3
3
Cycle count
3
3
3
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.69 MOVB (Move Bit Data from Accumulator to Bit Address)
2
F MC-16FX Family
● Example:
MOVB 765FH: 7,A
In this example, bit 7 at address 765FH is set to "1" because the low-order byte data of AL is
not equal to 00H.
AH
A
AL
01
×× ××
××
CCR
×××××
AH
A
×× ××
CCR
CM44-00203-3E
0 0
××
Memory
× ×
7 F
×
T N Z V C
T N Z V C
Memory
AL
01
××
× ×
765F
F F
× ×
× ×
Before execution
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.70 MOVEA (Move Effective Address to Destination)
8.70
F2MC-16FX Family
MOVEA (Move Effective Address to Destination)
Transfer the value specified by the second operand (effective address) to the
first operand.
If a general-purpose register is specified by the second operand, the address of the generalpurpose register is transferred. If the destination (first operand) is the accumulator (A), the
value in AL before the address transfer is transferred to AH.
● Assembler format:
MOVEA A,ear
MOVEA A,eam
MOVEA RWi,ear
MOVEA RWi,eam
● Operation:
First operand ← ea
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
202
First operand
A
A
RWi
RWi
Second operand
ear
eam
ear
eam
Byte count
2
2+
2
2+
Cycle count
1
1
1
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
2
F MC-16FX Family
CHAPTER 8 DETAILED INSTRUCTIONS
8.70 MOVEA (Move Effective Address to Destination)
● Example:
MOVEA RW2,@RW0+2
In this example, the address value (006BH) specified by the second operand (@RW0+2) is
transferred to RW2.
RW0
00 69
RW0
00 69
RW2
×× ××
RW2
00 6B
CCR
×××××
T N Z V C
Before execution
CM44-00203-3E
CCR
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.71 MOVL (Move Long Word Data from Source to Accumulator)
8.71
F2MC-16FX Family
MOVL (Move Long Word Data from Source to
Accumulator)
Transfer the long word data specified by the second operand to the
accumulator (A).
● Assembler format:
MOVL A,#imm32
MOVL A,ear
MOVL A,eam
● Operation:
(A) ← (Second operand)
[Long word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
204
First operand
A
A
A
Second operand
#imm32
ear
eam
Byte count
5
2
2+
Cycle count
2
2
2
Odd address correction
0
0
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.71 MOVL (Move Long Word Data from Source to Accumulator)
2
F MC-16FX Family
● Example:
MOVL A,#0053FF64H
In this example, the 32-bit immediate data (0053FF64H) is transferred to the accumulator (A)
as long word data.
A
AH
AL
×× ××
×× ××
CCR
×××××
A
AH
AL
00 53
FF 64
CCR
CM44-00203-3E
0 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.72 MOVL (Move Long Word Data from Accumulator to
Destination)
8.72
F2MC-16FX Family
MOVL (Move Long Word Data from Accumulator to
Destination)
Transfer the long word data of the accumulator (A) to the first operand.
● Assembler format:
MOVL ear,A
MOVL eam,A
● Operation:
(First operand) ← (A)
[Long word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
206
First operand
ear
eam
Second operand
A
A
Byte count
2
2+
Cycle count
2
2
Odd address correction
0
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.72 MOVL (Move Long Word Data from Accumulator to
Destination)
2
F MC-16FX Family
● Example:
MOVL RL1,A
In this example, the long word data (0197A024H) of the accumulator (A) is transferred to RL1.
AH
AL
A
01 97
A0 24
RL1
×× ××
×× ××
CCR
×××××
AH
AL
A
01 97
A0 24
RL1
01 97
A0 24
CCR
CM44-00203-3E
0 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.73 MOVN (Move Immediate Nibble Data to Accumulator)
8.73
F2MC-16FX Family
MOVN (Move Immediate Nibble Data to
Accumulator)
The value in AL is transferred to AH. And then 000H is transferred to the bit 4 to
bit 15 of AL; nibble data specified by the second operand is transferred to bit0
to bit3 of AL.
● Assembler format:
MOVN A,#imm4
● Operation:
(A) ← imm4
[Byte transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T: Unchanged
N:
Cleared
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
MOVN A,#0FH
In this example, the word data (6207H) of AL is transferred to AH, and then the byte data
(0FH) with the 4-bit immediate data (FH) zero-extended is transferred to AL.
A
AH
AL
×× ××
62 07
CCR
×××××
A
AH
AL
62 07
00 0F
CCR
208
0 0
××
T N Z V C
T N Z V C
Before execution
×
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.74 MOVS, MOVSI (Move String Byte with Increment)
2
F MC-16FX Family
8.74
MOVS, MOVSI (Move String Byte with Increment)
Transfer byte data from the address specified by AL in the space specified by
<source bank> to the address specified by AH in the space specified by
<destination bank>. The transfer is repeated the number of times specified by
RW0, with the addresses being incremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVS
[<destination bank>] [,<source bank>]
MOVSI [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL))
[Byte transfer]
(AH) ← (AH)+1, (AL) ← (AL)+1
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; RW0 cycles when RW0 is grayer
than 1 and the transfer area of source address and destination
address do not overlap; 2 × RW0 cycles in all other cases
Odd address correction:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.74 MOVS, MOVSI (Move String Byte with Increment)
F2MC-16FX Family
● Example:
MOVSI ADB,PCB
In this example, byte data is transferred from the address (FF0000H) specified by PCB and AL
to the address (018000H) specified by ADB and AH.
RW0
AH
80 00
AL
00 00
00 03
CCR
AH
80 03
×××××
RW0
00 00
AL
00 03
CCR
T N Z V C
PCB
FF
ADB
T N Z V C
PCB
01
FF
ADB
01
Memory
Memory
C
D
E
F
FF0003
FF0002
FF0001
FF0000
AL
AL
F
F
F
F
F
F
F
F
C
D
E
F
FF0003
FF0002
FF0001
FF0000
×
×
×
×
018003
018002
018001
018000
AH
× ×
AH
×
×
×
×
018003
018002
018001
018000
Before execution
210
×××××
FUJITSU MICROELECTRONICS LIMITED
F D
F E
F F
After execution
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.75 MOVSD (Move String Byte with Decrement)
2
F MC-16FX Family
8.75
MOVSD (Move String Byte with Decrement)
Transfer byte data from the address specified by AL in the space specified by
<source bank> to the address specified by AH in the space specified by
<destination bank>. The transfer is repeated the number of times specified by
RW0, with the addresses being decremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVSD [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL))
[Byte transfer]
(AH) ← (AH)-1, (AL) ← (AL)-1
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 2 × RW0 in all other cases
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.76 MOVSW, MOVSWI (Move String Word with Increment)
8.76
F2MC-16FX Family
MOVSW, MOVSWI (Move String Word with
Increment)
Transfer word data from the address specified by AL in the space specified by
<source bank> to the address specified by AH in the space specified by
<destination bank>. The transfer is repeated the number of times specified by
RW0, with the addresses being incremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVSW
[<destination bank>] [,<source bank>]
MOVSWI [<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL))
[Word transfer]
(AH) ← (AH)+2, (AL) ← (AL)+2
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
212
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 2 × RW0 in all other cases
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.76 MOVSW, MOVSWI (Move String Word with Increment)
2
F MC-16FX Family
● Example:
MOVSW,ADB
In this example, word data is transferred from the address (38A000H) specified by ADB and
AL to the address (CD0000H) specified by DTB and AH.
A
AH
00 00
RW0
00 03
AL
A0 00
CCR
×××××
A
AH
00 06
RW0
00 00
AL
A0 06
CCR
T N Z V C
T N Z V C
DTB
CD
ADB
DTB
38
CD
ADB
AH
×
×
×
×
×
×
38
Memory
Memory
×
×
×
×
×
×
×××××
CD0005
CD0004
CD0003
CD0002
CD0001
CD0000
AH
2
4
3
3
4
4
6
2
6
1
D
6
CD0005
CD0004
CD0003
CD0002
CD0001
CD0000
2
4
3
3
4
4
6
2
6
1
D
6
38A005
38A004
38A003
38A002
38A001
38A000
AL
AL
2
4
3
3
4
4
6
2
6
1
D
6
38A005
38A004
38A003
38A002
38A001
38A000
Before execution
CM44-00203-3E
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.77 MOVSWD (Move String Word with Decrement)
8.77
F2MC-16FX Family
MOVSWD (Move String Word with Decrement)
Transfer word data from the address specified by AL in the space specified by
<source bank> to the address specified by AH in the space specified by
<destination bank>. The transfer is repeated the number of times specified by
RW0, with the addresses being decremented each time.
The transfer is not performed if RW0 is equal to zero. Four types of registers PCB, DTB,
ADB, and SPB can be used as <destination bank> and <source bank>. By default, DTB is
assumed.
If an interrupt occurs during the transfer, the transfer is suspended to handle the interrupt. The
transfer is resumed after the interrupt has been handled.
● Assembler format:
MOVSWD
[<destination bank>] [,<source bank>]
● Operation:
The following is repeated until RW0 becomes equal to zero:
((AH)) ← ((AL))
[Word transfer]
(AH) ← (AH)–2, (AL) ← (AL)–2
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
214
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 2 × RW0 in all other cases
Odd address correction:
RW0 cycle(s) when the transfer destination is an odd address;
RW0 cycle(s) when the transfer source is an odd address; and 2
× RW0 cycles when both the transfer destination and the
transfer source are odd addresses
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.78 MOVW (Move Word Data from Source to Accumulator)
2
F MC-16FX Family
8.78
MOVW (Move Word Data from Source to
Accumulator)
The value in AL is transferred to AH. And then the word data in the second
operand is transferred to AL.
If the second operand is @A, transfer to AH is not performed.
● Assembler format:
MOVW A,#imm16
MOVW A,@RWi+disp8
MOVW A,@A
MOVW A,addr16
MOVW A,@RLi+disp8
MOVW A,RWi
MOVW A,SP
MOVW A,dir
MOVW A,io
MOVW A,ear
MOVW A,eam
● Operation:
(A) ← (Second operand)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
First operand
Second operand
A
A
A
A
#imm16 @A @RLi+disp8 SP
A
A
A
A
A
A
A
io @RWi+disp8 addr16 RWi dir ear eam
Byte count
3
2
3
1
2
2
3
1
2
2
2+
Cycle count
1
1
1
1
1
1
1
1
1
1
1
Odd address correction
0
1
1
0
1
1
1
0
1
0
1
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.78 MOVW (Move Word Data from Source to Accumulator)
F2MC-16FX Family
● Example:
MOVW A,0F9A0H
In this example, the word data (4901H) of AL is transferred to AH, and then the word data
(AE86H) at address F9A0H is transferred to AL.
AH
A
AL
49 01
×× ××
CCR
×××××
A
AH
49 01
CCR
T N Z V C
Memory
A E
8 6
×
1 0
××
T N Z V C
Memory
F9A1
F9A0
Before execution
216
AL
AE 86
A E
8 6
F9A1
F9A0
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.79 MOVW (Move Word Data from Accumulator to Destination)
2
F MC-16FX Family
8.79
MOVW (Move Word Data from Accumulator to
Destination)
Transfer the low-order word data of the accumulator (A) to the first operand.
● Assembler format:
MOVW @RLi+disp8,A
MOVW addr16,A
MOVW SP,A
MOVW RWi,A
MOVW io,A
MOVW dir,A
MOVW @RWi+disp8,A
MOVW ear,A
MOVW eam,A
● Operation:
(First operand) ← (A)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
First operand
CM44-00203-3E
dir @RLi+disp8 addr16 SP io @RWi+disp8 RWi ear eam
Second operand
A
A
A
A
A
A
A
A
A
Byte count
2
3
3
1
2
2
1
2
2+
Cycle count
1
1
1
1
1
1
1
1
1
Odd address correction 1
1
1
0
1
1
0
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.79 MOVW (Move Word Data from Accumulator to Destination)
F2MC-16FX Family
● Example:
MOVW RW0,A
In this example, the word data (0000H) of AL is transferred to RW0.
AH
A
AL
00 00
×× ××
RW0
CCR
×× ××
×××××
AH
A
×× ××
RW0
CCR
T N Z V C
Before execution
218
AL
00 00
00 00
×
0 1
××
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.80 MOVW (Move Immediate Word Data to Destination)
2
F MC-16FX Family
8.80
MOVW (Move Immediate Word Data to Destination)
This instruction transfers the 16-bit immediate data to the first operand.
When the first operand is @PC + disp16, the transfer destination address is the address where
the machine instruction of the MOVW instruction is stored + 4 + disp16. Note that this is not
the address where the machine instruction of the instruction subsequent to the MOVW
instruction is stored+disp16.
● Assembler format:
MOVW ear,#imm16
MOVW eam,#imm16
● Operation:
(First operand) ← imm16
● CCR:
If the data is transferred to a generalpurpose register (RW0 to RW7)
If the data is transferred to a register other
than the general-purpose registers (RW0 to
RW7)
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
–
–
–
–
–
–
–
I, S, and T: Unchanged
N:
Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, N is set when
the MSB of the transferred data is "1", cleared otherwise.
Z:
Unchanged if the data is transferred to a register other than the general-purpose
registers. If the data is transferred to the general-purpose register, Z is set when the
transferred data is zero, cleared otherwise.
V and C:
Unchanged and none of the flags is changed.
● Byte count and cycle count:
First operand
Second operand
CM44-00203-3E
ear
eam
#imm16 #imm16
Byte count
4
4+
Cycle count
2
2
Odd address correction
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.80 MOVW (Move Immediate Word Data to Destination)
F2MC-16FX Family
● Example:
MOVW RW0,#2343H
In this example, the 16-bit immediate data (2343H) is transferred to RW0.
CCR
×××××
CCR
T N Z V C
RW0
×× ××
Before execution
220
RW0
×
0 0
××
T N Z V C
23 43
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.81 MOVW (Move Word Data from Source to Destination)
2
F MC-16FX Family
8.81
MOVW (Move Word Data from Source to
Destination)
Transfer the word data specified by the second operand to the first operand.
● Assembler format:
MOVW RWi,#imm16
MOVW ear,RWi
MOVW eam,RWi
MOVW RWi,ear
MOVW RWi,eam
● Operation:
(First operand) ← (Second operand)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
RWi
RWi
RWi
ear
eam
Second operand
#imm16
ear
eam
RWi
RWi
Byte count
3
2
2+
2
2+
Cycle count
1
1
1
1
1
Odd address correction
0
0
1
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.81 MOVW (Move Word Data from Source to Destination)
F2MC-16FX Family
● Example:
MOVW RW1,RW0
In this example, the word data (004AH) of RW0 is transferred to RW1.
A
AH
AL
×× ××
×× ××
A
AH
AL
×× ××
×× ××
RW0
00 4A
RW0
00 4A
RW1
×× ××
RW1
00 4A
CCR
×××××
CCR
T N Z V C
Before execution
222
×
0 0
××
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.82 MOVW (Move Immediate Word Data to io)
2
F MC-16FX Family
8.82
MOVW (Move Immediate Word Data to io)
Transfer 16-bit immediate data to the I/O area specified by the first operand.
● Assembler format:
MOVW io,#imm16
● Operation:
(First operand) ← imm16
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
4
Cycle count:
1
Odd address correction:
1
● Example:
MOVW 24H,#2343H
In this example, the 16-bit immediate data (2343H) is transferred to address 24H in the I/O area
as word data.
×××××
CCR
CCR
T N Z V C
×
×
×
×
× ×
000025
000024
Before execution
CM44-00203-3E
T N Z V C
Memory
Memory
×
×
×
×
×××××
2 3
4 3
000025
000024
× ×
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.83 MOVW (Move Word Data from AH to Memory)
8.83
F2MC-16FX Family
MOVW (Move Word Data from AH to Memory)
Transfer the word data of AH to the memory location specified by the contents
of AL.
● Assembler format:
MOVW @AL,AH
● Operation:
((AL)) ← (AH)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
Odd address correction:
1
● Example:
MOVW @AL,AH
In this example, the word data (00CBH) of AH is transferred to the address (FEFFH) specified
by AL.
A
AH
AL
00 CB
FE FF
CCR
×××××
A
AH
AL
00 CB
FE FF
CCR
T N Z V C
FEFF
Before execution
224
1 0
××
T N Z V C
Memory
Memory
7 1
×
C B
FEFF
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.84 MOVX (Move Byte Data with Sign Extension from Source
to Accumulator)
2
F MC-16FX Family
8.84
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator)
The value in AL is transferred to AH. And then the word data that is sign
extended from a byte data in the second operand is transferred to AL.
If the second operand is @A, transfer to AH is not performed.
● Assembler format:
MOVX A,#imm8
MOVX A,@RWi+disp8
MOVX A,@A
MOVX A,addr16
MOVX A,@RLi+disp8
MOVX A,Ri
MOVX A,dir
MOVX A,io
MOVX A,ear
MOVX A,eam
● Operation:
(A) ← (Second operand)
[Byte transfer with sign extension]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T: Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
First operand
A
A
A
A
A
A
A
A
Second operand
#imm8
@A
@RLi+disp8
dir
io
@RWi+disp8
addr16
Ri
Byte count
2
2
3
2
2
2
3
1
2
2+
Cycle count
1
1
1
1
1
1
1
1
1
1
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
A
A
ear eam
225
CHAPTER 8 DETAILED INSTRUCTIONS
8.84 MOVX (Move Byte Data with Sign Extension from Source
to Accumulator)
● Example:
F2MC-16FX Family
MOVX A,0E001H
In this example, the word data (A046H) of AL is transferred to AH, and then the word data
(FF86H), for which the byte data (86H) at address E001H is sign-extended, is transferred to AL.
AH
A
AL
A0 46
×× ××
CCR
×××××
A
AH
A0 46
CCR
T N Z V C
Memory
8 6
×
1 0
××
T N Z V C
Memory
E001
Before execution
226
AL
FF 86
8 6
E001
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.85 MUL (Multiply Byte Data of Accumulator)
2
F MC-16FX Family
8.85
MUL (Multiply Byte Data of Accumulator)
This instruction multiplies the low-order byte data of AH by that of AL as
signed binary numbers, then returns the result to AL of the accumulator (A).
● Assembler format:
MUL A
● Operation:
word (A) ← byte (AH)×byte (AL)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
4
● Example:
MUL A
In this example, the low-order byte data (FAH) of AH is multiplied by the low-order byte data
(11H) of AL with a sign. The word data (FF9AH) is set to AL as the multiplication result.
A
AH
AL
00 FA
00 11
CCR
×××××
T N Z V C
Before execution
CM44-00203-3E
A
AH
AL
00 FA
FF 9A
CCR
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.86 MUL (Multiply Byte Data of Accumulator and Effective
Address)
8.86
F2MC-16FX Family
MUL (Multiply Byte Data of Accumulator and
Effective Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the
second operand as signed binary numbers and restore the result in bits 0 to 15
of A.
● Assembler format:
MUL A,ear
MUL A,eam
● Operation:
word (A) ← byte (A) × byte (ea)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
4
5
● Example:
MUL A,R7
In this example, the low-order byte data (85H) of AL is multiplied by the byte data (A5H) in R7
with a sign. The word data (2B89H) is set to AL as the multiplication result.
A
AH
AL
×× ××
00 85
R7
CCR
A
AH
AL
×× ××
2B B9
A5
×××××
R7
CCR
T N Z V C
Before execution
228
A5
×××××
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.87 MULW (Multiply Word Data of Accumulator)
2
F MC-16FX Family
8.87
MULW (Multiply Word Data of Accumulator)
Multiply the word data of AH by the word data specified by AL as signed binary
numbers and restore the result in the accumulator (A) as long word data.
● Assembler format:
MULW A
● Operation:
long (A) ← word (AH)×word (AL)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
6
● Example:
MULW A
In this example, the word data (AD01H) of AH is multiplied by the word data (05EDH) of AL
with a sign. The long word data is set to the accumulator (A) as the multiplication result.
A
AH
AL
AD 01
05 ED
CCR
×××××
A
AH
AL
FE 14
2E ED
CCR
T N Z V C
Before execution
CM44-00203-3E
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.88 MULW (Multiply Word Data of Accumulator and Effective
Address)
8.88
F2MC-16FX Family
MULW (Multiply Word Data of Accumulator and
Effective Address)
Multiply the word data of the accumulator (A) by the word data specified by the
second operand as signed binary numbers and restore the result in A as long
word data.
● Assembler format:
MULW A,ear
MULW A,eam
● Operation:
long (A) ← word (A) × word (Second operand)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
6
7
Odd address correction
0
1
● Example:
MULW A,RW5
In this example, the word data (8342H) of AL is multiplied by the word data (4314H) in RW5
with a sign. The long word data is set to the accumulator (A) as the multiplication result.
A
AH
AL
×× ××
83 42
RW5
CCR
43 14
×××××
A
AH
AL
DF 50
87 28
RW5
CCR
T N Z V C
Before execution
230
43 14
×××××
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.89 MULU (Multiply Unsigned Byte Data of Accumulator)
2
F MC-16FX Family
8.89
MULU (Multiply Unsigned Byte Data of Accumulator)
Multiply the low-order byte data of AH by the low-order byte data of AL as
unsigned binary numbers and restore the result in the AL of the accumulator
(A).
● Assembler format:
MULU A
● Operation:
word (A) ← byte (AH)×byte (AL)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
2
● Example:
MULU A
In this example, the low-order byte data (FAH) of AH is multiplied by the low-order byte data
(11H) of AL without a sign. The word data (109AH) is set to AL as the multiplication result.
A
AH
00 FA
AL
00 11
CCR
×××××
A
AH
00 FA
CCR
T N Z V C
Before execution
CM44-00203-3E
AL
10 9A
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.90 MULU (Multiply Unsigned Byte Data of Accumulator and
Effective Address)
8.90
F2MC-16FX Family
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the
second operand as unsigned binary numbers and restore the result in bits 0 to
15 of A.
● Assembler format:
MULU A, ear
MULU A, eam
● Operation:
word (A) ← byte (A) × byte (Second operand)
[Byte multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
2
3
● Example:
MULU A, R7
In this example, the low-order byte data (85H) of AL is multiplied by the byte data (A5H) in R7
without a sign. The word data (55B9H) is set to AL as the multiplication result.
AH
A
AL
00 85
×× ××
R7
CCR
AH
A
×× ××
A5
×××××
R7
CCR
T N Z V C
Before execution
232
AL
55 B9
A5
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.91 MULUW (Multiply Unsigned Word Data of Accumulator)
2
F MC-16FX Family
8.91
MULUW (Multiply Unsigned Word Data of
Accumulator)
Multiply the word data of AH by the word data of AL as unsigned binary
numbers and restore the result in the accumulator (A) as long word data.
● Assembler format:
MULUW A
● Operation:
long (A) ← word (AH) × word (AL)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
4
● Example:
MULUW A
In this example, the word data (AD01H) of AH is multiplied by the word data (05EDH) of AL
without a sign. The long word data is set to the accumulator (A) as the multiplication result.
AH
A
AL
AD 01
05 ED
CCR
×××××
AH
A
AL
04 01
CCR
T N Z V C
Before execution
CM44-00203-3E
2E ED
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.92 MULUW (Multiply Unsigned Word Data of Accumulator and
Effective Address)
8.92
F2MC-16FX Family
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)
Multiply the word data of the accumulator (A) by the word data specified by the
second operand as unsigned binary numbers and restore the result in A as
long word data.
● Assembler format:
MULUW A, ear
MULUW A, eam
● Operation:
long (A) ← word (A) × word (Second operand)
[Word multiplication]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
4
5
Odd address correction
0
1
● Example:
MULUW A, RW5
In this example, the word data (8342H) of AL is multiplied by the word data (4314H) in RW5
without a sign. The long word data is set to the accumulator (A) as the multiplication result.
AH
A
RW5
×× ××
43 14
AL
83 42
CCR
×××××
A
RW5
AH
22 64
43 14
T N Z V C
Before execution
234
FUJITSU MICROELECTRONICS LIMITED
AL
87 28
CCR
×××××
T N Z V C
After execution
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.93 NEG (Negate Byte Data of Destination)
2
F MC-16FX Family
8.93
NEG (Negate Byte Data of Destination)
Take the 2's complement of the byte data specified by the operand and restore
the result in the operand. If the operand is the accumulator (A), the value
resulting from sign-extending the operation result is transferred to upper byte
of AL.
● Assembler format:
NEG A
NEG ear
NEG eam
● Operation:
(Operand) ← 0–(Operand)
[Byte operation]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Operand
A
ear
eam
Byte count
1
2
2+
Cycle count
1
1
3
● Example:
NEG R0
In this example, the 2's complement of the byte data (59H) in R0 is obtained.
R0
CCR
59
×××××
T N Z V C
Before execution
CM44-00203-3E
R0
CCR
×
A7
1 0 0 1
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.94 NEGW (Negate Word Data of Destination)
8.94
F2MC-16FX Family
NEGW (Negate Word Data of Destination)
Take the 2's complement of the word data specified by the operand and restore
the result in the operand.
● Assembler format:
NEGW A
NEGW ear
NEGW eam
● Operation:
(Operand) ← 0–(Operand)
[Word operation]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Operand
A
ear
eam
Byte count
1
2
2+
Cycle count
1
1
3
Odd address correction
0
0
2
● Example:
NEGW A
In this example, the 2's complement of the word data (AB98H) of AL is obtained.
AH
A
AL
AB 98
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
Before execution
236
AL
54 68
×
0 0 0 1
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.95 NOP (No Operation)
2
F MC-16FX Family
8.95
NOP (No Operation)
Perform no operation.
● Assembler format:
NOP
● Operation:
No operation is performed.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
NOP
The NOP instruction performs no operations.
A
AH
AL
×× ××
×× ××
PC
AH
×× ××
A
F0 00
CCR
AL
PC
×××××
CCR
T N Z V C
PC
0 0
×××××
Memory
F001
F000
Before execution
CM44-00203-3E
F0 01
T N Z V C
Memory
× ×
×× ××
PC
× ×
0 0
F001
F000
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.96 NOT (Not Byte Data of Destination)
8.96
F2MC-16FX Family
NOT (Not Byte Data of Destination)
Take the logical NOT of the byte data specified by the operand and restore the
result in the operand.
● Assembler format:
NOT A
NOT ear
NOT eam
● Operation:
(Operand) ← not (Operand)
[Byte logical NOT]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
238
Operand
A
ear
eam
Byte count
1
2
2+
Cycle count
1
1
3
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.96 NOT (Not Byte Data of Destination)
2
F MC-16FX Family
● Example:
NOT 0071H
In this example, the byte data (FFH) at address 0071H is inverted for each bit.
A
AH
AL
×× ××
×× ××
CCR
×××××
A
AH
AL
×× ××
×× ××
CCR
T N Z V C
0071
Before execution
CM44-00203-3E
0 1 0
×
T N Z V C
Memory
Memory
F F
×
0 0
0071
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.97 NOTW (Not Word Data of Destination)
8.97
F2MC-16FX Family
NOTW (Not Word Data of Destination)
Take the logical NOT of the word data specified by the operand and restore the
result in the operand.
● Assembler format:
NOTW A
NOTW ear
NOTW eam
● Operation:
(Operand) ← not (Operand)
[Word logical NOT]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
Operand
A
ear
eam
Byte count
1
2
2+
Cycle count
1
1
3
Odd address correction
0
0
2
● Example:
NOTW RW3
In this example, the word data (258BH) of RW3 is inverted for each bit.
RW3
CCR
25 8B
×××××
T N Z V C
Before execution
240
RW3
CCR
DA 74
×
1 0 0
×
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.98 NRML (NORMALIZE Long Word)
2
F MC-16FX Family
8.98
NRML (NORMALIZE Long Word)
Shift the long word data of the accumulator (A) to the left until the most
significant bit of the accumulator (A) becomes "1", if the long word data is not
zero.
R0 is set to the number of shifts required and the zero flag (Z) is cleared.
If the long word data of the accumulator (A) is zero, R0 is set to zero and the zero flag (Z) is
set.
● Assembler format:
NRML A,R0
● Operation:
If A≠0: The long word data is shifted to the left until the most significant bit of A becomes 1.
(R0) ← Number of shifts required, Z ← 0
If A=0: (R0) ← 0, Z ← 1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N: Unchanged
Z:
Set when A is equal to zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
● Example:
NRML A,R0
In this example, the long word data (00008361H) of the accumulator (A) is shifted to the left by
16 bits. The number of shifted bits (10H) is set to R0.
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.98 NRML (NORMALIZE Long Word)
A
AH
AL
00 00
83 61
R0
CCR
F2MC-16FX Family
A
AH
AL
83 61
00 00
34
×××××
R0
CCR
T N Z V C
Before execution
242
××
10
0
××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.99 OR (Or Byte Data of Destination and Source to Destination)
2
F MC-16FX Family
8.99
OR (Or Byte Data of Destination and Source to
Destination)
Take the logical OR of the byte data specified by the first operand and the byte
data specified by the second operand and restore the result in the first
operand.
● Assembler format:
OR A,#imm8
OR A,ear
OR A,eam
OR ear,A
OR eam,A
● Operation:
(First operand) ← (First operand) or (Second operand)
[Byte logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
ear
eam
Second operand
#imm8
ear
eam
A
A
Byte count
2
2
2+
2
2+
Cycle count
1
1
2
1
3
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CHAPTER 8 DETAILED INSTRUCTIONS
8.99 OR (Or Byte Data of Destination and Source to Destination)
F2MC-16FX Family
● Example:
OR 0052H,A
In this example, the logical OR is taken between the byte data at address 0052H and the loworder byte data (37H) of AL.
AH
A
AL
00 37
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
0052
Before execution
244
×
1 0 0
×
T N Z V C
Memory
Memory
F A
AL
00 37
F F
0052
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.100 OR (Or Byte Data of Immediate Data and Condition Code
Register to Condition Code Register)
2
F MC-16FX Family
8.100 OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
Take the logical OR of the byte data in the condition code register (CCR) and
specified 8-bit immediate data and restore the result in the condition code
register (CCR).
Bit 7 of the immediate data is ignored because the condition code register (CCR) is 7 bits long.
● Assembler format:
OR CCR,#imm8
● Operation:
(CCR) ← (CCR) or imm8
[Byte logical OR]
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I: Stores bit 6 of the operation result.
S: Stores bit 5 of the operation result.
T: Stores bit 4 of the operation result.
N: Stores bit 3 of the operation result.
Z: Stores bit 2 of the operation result.
V: Stores bit 1 of the operation result.
C: Stores bit 0 of the operation result.
● Byte count and cycle count:
Byte count:
2
Cycle count:
1
CM44-00203-3E
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CHAPTER 8 DETAILED INSTRUCTIONS
8.100 OR (Or Byte Data of Immediate Data and Condition Code
Register to Condition Code Register)
● Example:
F2MC-16FX Family
OR CCR,#57H
In this example, the logical OR is taken between CCR and bits 6 to 0 of the 8-bit immediate
data (57H).
A
CCR
AH
AL
×× ××
×× ××
I
0
S
1
T
1
N
0
Z
1
V
0
C
1
A
CCR
AH
AL
×× ××
×× ××
I
1
S
1
T
1
ILM2 ILM1 ILM0
× × ×
ILM
MSB
RP
Before execution
246
Z
1
V
1
C
1
ILM2 ILM1 ILM0
× × ×
ILM
LSB
× × × × ×
N
0
MSB
RP
LSB
× × × × ×
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.101 ORL (Or Long Word Data of Destination and Source to
Destination)
2
F MC-16FX Family
8.101 ORL (Or Long Word Data of Destination and Source
to Destination)
Take the logical OR of the long word data for the accumulator (A) and that
specified by the second operand and restore the result in A.
● Assembler format:
ORL A,ear
ORL A,eam
● Operation:
(A) ← (A) or (Second operand)
[Long word logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
2
3
Odd address correction
0
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.101 ORL (Or Long Word Data of Destination and Source to
Destination)
● Example:
F2MC-16FX Family
ORL A,0FFF0H
In this example, the logical OR is taken between the long word data (725DF05CH) of the
accumulator (A) and the long word data (FF55AA00H) at address FFF0H.
A
AH
AL
72 5D
F0 5C
CCR
A
AH
AL
FF 5D
FA 5C
×××××
CCR
T N Z V C
Memory
F
5
A
0
F
5
A
0
1 0 0
×
T N Z V C
Memory
FFF3
FFF2
FFF1
FFF0
Before execution
248
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.102 ORW (Or Word Data of AH and AL to AL)
2
F MC-16FX Family
8.102 ORW (Or Word Data of AH and AL to AL)
Take the logical OR of the word data for AH and that for AL and restore the
result in AL.
● Assembler format:
ORW A
● Operation:
(AL) ← (AH) or (AL)
[Word logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
ORW A
In this example, the logical OR is taken between the word data (AB98H) of AL and the word
data (0426H) of AH.
A
AH
04 26
AL
AB 98
CCR
×××××
A
AH
04 26
CCR
T N Z V C
Before execution
CM44-00203-3E
AL
AF BE
×
1 0 0
×
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.103 ORW (Or Word Data of Destination and Source to
Destination)
8.103
F2MC-16FX Family
ORW (Or Word Data of Destination and Source to
Destination)
Take the logical OR of the word data specified by the first operand and the word
data specified by the second operand and restore the result in the first
operand.
● Assembler format:
ORW A,#imm16
ORW A,ear
ORW A,eam
ORW ear,A
ORW eam,A
● Operation:
(First operand) ← (First operand) or (Second operand)
[Word logical OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
250
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Byte count
3
2
2+
2
2+
Cycle count
1
1
2
1
3
Odd address correction
0
0
1
0
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.103 ORW (Or Word Data of Destination and Source to
Destination)
2
F MC-16FX Family
● Example:
ORW 0E001H,A
In this example, the logical OR is taken between the word data (4283H) at address E001H and
the word data (5963H) of AL.
AH
A
AL
59 63
×× ××
CCR
×××××
AH
A
×× ××
CCR
T N Z V C
E002
E001
Before execution
CM44-00203-3E
×
1 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
AL
59 63
D B
6 3
E002
E001
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.104 POPW (Pop Word Data of Accumulator from Stack
Memory)
8.104
F2MC-16FX Family
POPW (Pop Word Data of Accumulator from Stack
Memory)
The AL value is transferred to AH. Then, the word data of the memory location
pointed to by the stack pointer (SP) is transferred to AL. After the data is
transferred, 0002H is word-added to the value of SP (word data).
● Assembler format:
POPW A
● Operation:
(A) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
252
Byte count:
1
Cycle count:
1
Odd address correction:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.104 POPW (Pop Word Data of Accumulator from Stack
Memory)
2
F MC-16FX Family
● Example:
POPW A
In this example, the word data (1635H) of AL is transferred to AH, and then the word data
(10ACH) at the address (0120H) specified by SP is transferred to AL. "2" is added to SP.
A
AH
AL
04 22
16 35
SP
01 20
CCR
A
×××××
AH
AL
16 35
10 AC
SP
01 22
CCR
T N Z V C
T N Z V C
Memory
Memory
SP
1 0
A C
0122
0121
0120
Before execution
CM44-00203-3E
×××××
SP
1 0
A C
0122
0121
0120
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.105 POPW (Pop Word Data of AH from Stack Memory)
8.105
F2MC-16FX Family
POPW (Pop Word Data of AH from Stack Memory)
Transfer word data from the memory location pointed to by the stack pointer
(SP) to AH. Then, 0002H is word-added to the value of SP (word data).
● Assembler format:
POPW AH
● Operation:
(AH) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
Odd address correction:
1
● Example:
POPW AH
In this example, the word data (4314H) at the address (0120H) specified by SP is transferred to
AH. "2" is added to SP.
A
AH
04 22
AL
16 35
SP
CCR
A
01 20
AH
43 14
SP
×××××
CCR
T N Z V C
SP
×××××
Memory
0122
0121
0120
Before execution
254
01 22
T N Z V C
Memory
4 3
1 4
AL
16 35
SP
4 3
1 4
0122
0121
0120
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.106 POPW (Pop Word Data of Program Status from Stack
Memory)
2
F MC-16FX Family
8.106 POPW (Pop Word Data of Program Status from
Stack Memory)
Transfer word data from the memory location pointed to by the stack pointer
(SP) to the processor status (PS). Bit 7 of the word data is ignored. Then,
0002H is word-added to the value of SP (word data).
● Assembler format:
POPW PS
● Operation:
(PS) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
The values of the corresponding bits for the stack memory are transferred.
● Byte count and cycle count:
Byte count:
1
Cycle count:
19 when the content of RP changes; 4 in all other cases
Odd address correction:
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.106 POPW (Pop Word Data of Program Status from Stack
Memory)
● Example:
F2MC-16FX Family
POPW PS
In this example, the word data (4314H) at the address (0120H) specified by SP is transferred to
PS. "2" is added to SP.
SP
I
CCR
S
T
N
Z
V
SP
C
× × × × × × ×
MSB
ILM2 ILM1 ILM0
ILM
01 20
× × ×
RP
CCR
LSB
× × × × ×
SP
0
1
0
T
1
N Z V C
0 1 0 0
MSB
LSB
RP 0 0 0 1 1
Memory
0122
0121
0120
Before execution
256
S
0
ILM2 ILM1 ILM0
ILM
Memory
4 3
1 4
I
0
01 22
SP
4 3
1 4
0122
0121
0120
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.107 POPW (Pop Registers from Stack Memory)
2
F MC-16FX Family
8.107 POPW (Pop Registers from Stack Memory)
Transfer the data pointed to by the stack pointer (SP) to the multiple generalpurpose word registers specified by the register list (rlst).
In assembler representation, register names are enumerated as a register list. After assembly,
the register list turns into byte data.
● Assembler format:
POPW rlst
● Operation:
(RWx) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
The above operation is repeated for all the registers specified by rlst.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
(Number of transfers)
Odd address correction:
(Number of transfers)
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CHAPTER 8 DETAILED INSTRUCTIONS
8.107 POPW (Pop Registers from Stack Memory)
F2MC-16FX Family
● Example:
POPW (RW0,RW4)
In this example, RW0 and RW4 are popped from the stack specified by SP.
SP
34 FA
××
××
××
××
××
××
××
××
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Memory
SP
0
0
0
0
4
3
2
1
××
××
××
××
××
××
××
××
34FE
34FD
34FC
34FB
34FA
Before execution
258
SP
34 FE
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
02
01
××
××
××
××
××
××
04
03
××
××
××
××
××
××
Memory
0
0
0
0
4
3
2
1
34FE
34FD
34FC
34FB
34FA
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.108 PUSHW (Push Word Data of Inherent Register to Stack
Memory)
2
F MC-16FX Family
8.108 PUSHW (Push Word Data of Inherent Register to
Stack Memory)
Decrement the value of the stack pointer (SP) by two words and transfer the
word data of the register to the memory location pointed to by the resulting SP
value.
● Assembler format:
PUSHW A
PUSHW AH
PUSHW PS
● Operation:
(SP) ← (SP)–2
[Word subtraction]
((SP)) ← (Operand)
[Word transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
CM44-00203-3E
Operand
A
AH
PS
Byte count
1
1
1
Cycle count
1
1
1
Odd address correction
1
1
1
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CHAPTER 8 DETAILED INSTRUCTIONS
8.108 PUSHW (Push Word Data of Inherent Register to Stack
Memory)
● Example:
F2MC-16FX Family
PUSHW A
In this example, "2" is subtracted from SP, and the word data of AL is transferred to the
address (0120H) specified by SP.
A
AH
AL
×× ××
45 A4
SP
01 22
CCR
A
AH
AL
×× ××
45 A4
SP
01 20
×××××
CCR
T N Z V C
T N Z V C
Memory
Memory
SP
× ×
× ×
0122
0121
0120
Before execution
260
×××××
SP
4 5
A 4
0122
0121
0120
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.109 PUSHW (Push Registers to Stack Memory)
2
F MC-16FX Family
8.109 PUSHW (Push Registers to Stack Memory)
Transfer the contents of the multiple general-purpose word registers specified
by the register list (rlst) to the memory location pointed to by the stack pointer
(SP).
In assembler representation, register names are enumerated as a register list. After assembly,
the register list turns into byte data.
● Assembler format:
PUSHW rlst
● Operation:
(SP) ← (SP)–2
[Word subtraction]
((SP))← (RWx)
[Word transfer]
The above operation is repeated for all the registers specified by rlst.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
2
Cycle count:
(Number of transfers)
Odd address correction:
(Number of transfers)
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CHAPTER 8 DETAILED INSTRUCTIONS
8.109 PUSHW (Push Registers to Stack Memory)
F2MC-16FX Family
● Example:
PUSHW (RW1,RW3)
In this example, RW3 and RW1 are pushed to the stack specified by SP.
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
34 FE
×× ××
3 5
A 4
×× ××
6 D
F 0
×
×
×
×
×
×
×
×
×
×
×
×
Memory
×
×
×
×
×
×
×
×
×
×
×
×
34FE
34FD
34FC
34FB
34FA
Before execution
262
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
34 FA
×× ××
3 5
×× ××
6 D
F 0
×
×
×
×
×
×
×
×
×
×
×
×
Memory
SP
A 4
6
F
3
A
D
0
5
4
×
×
×
×
34FE
34FD
34FC
34FB
34FA
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.110 RET (Return from Subroutine)
2
F MC-16FX Family
8.110 RET (Return from Subroutine)
Cause a branch to the address pointed to by the stack pointer (SP).
If this instruction is used in combination with a subroutine call instruction (CALL, CALLV),
control returns to the instruction following the subroutine call instruction after the branch
operation is completed.
● Assembler format:
RET
● Operation:
(PC) ← ((SP))
[Word transfer]
(SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
4
Odd address correction:
1
● Example:
RET
In this example, the word data (FC22H) at the address (0062H) specified by SP is set to PC. "2"
is added to SP.
SP
00 62
SP
00 64
PC
F0 02
PC
FC 22
Memory
SP
F C
2 2
Memory
0064
0063
0062
Before execution
CM44-00203-3E
SP
F C
2 2
0064
0063
0062
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.111 RETI (Return from Interrupt)
8.111
F2MC-16FX Family
RETI (Return from Interrupt)
This instruction returns the data in the memory that is indicated by (SSP) to PS
to detect interrupt requests performed using IF or ILM.
When the next interrupt request is received, the procedure branches to the detected interruption
vector. If no next interrupt is received, the procedure will return from the interruption process.
● Assembler format:
RETI
● Operation:
(1)
If the next interrupt is accepted
(PS)
←
((SSP))
(S)
←
1, (PCB), (PC) ← Interrupt vector address
(ILM)
←
Accepted interrupt level
DTB, PCB, DPR, ADB, AL, and AH are not restored.
(2)
If control is returned from the next interrupt
(PS)
←
((SSP)), (SSP)
←
(SSP)+2;
(PC)
←
((SSP)), (SSP)
←
(SSP)+2;
(DTB),(PCB)
←
((SSP)), (SSP)
←
(SSP)+2;
(DPR),(ADB)
←
((SSP)), (SSP)
←
(SSP)+2;
(AL)
←
((SSP)), (SSP)
←
(SSP)+2;
(AH)
←
((SSP)), (SSP)
←
(SSP)+2
● CCR
(1) If the next interrupt is accepted
264
(2) If control is returned from the next
interrupt
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
*
S
*
*
*
*
*
*
*
*
*
*
*
*
I: Restored to the saved I value.
I: Restored to the saved I value.
S: Set
S: Restored to the saved S value.
T: Restored to the saved T value.
T: Restored to the saved T value.
N: Restored to the saved N value.
N: Restored to the saved N value.
Z: Restored to the saved Z value.
Z: Restored to the saved Z value.
V: Restored to the saved V value.
V: Restored to the saved V value.
C: Restored to the saved C value.
C: Restored to the saved C value.
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.111 RETI (Return from Interrupt)
2
F MC-16FX Family
● Byte count and cycle count:
Byte count:
1
Cycle count:
23 when the content of RP changes; 6 in all other cases
Odd address correction:
1
● Example:
RETI (if control is returned from the interrupt)
In this example, the word data is transferred from the address (037FF4H) specified by SSB and
SP to each register. "2" is added to SP each time data is transferred to a register.
A
AH
AL
××××
××××
DTB
A
PCB
PC
×× ××
××
××
DPR
ADB
××
××
CCR
ILM
RP
I S T N Z V C
××
××
× ×× × × × ×
SSB
03
SSP
7F F4
AH
FFFE
DTB
PCB
99
88
DPR ADB
BB
AA
ILM
RP
03
01
SSB
03
SSP
F
E
D
C
B
A
9
8
7
6
1
0
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
CM44-00203-3E
CCR
I S T N Z V C
0 0 0 0 0 0 0
SSP
80 00
Memory
Memory
F
E
D
C
B
A
9
8
7
6
6
8
AL
DDCC
PC
77 66
SSP
F
E
D
C
B
A
9
8
7
6
6
8
F
E
D
C
B
A
9
8
7
6
1
0
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.112 RETP (Return from Physical Address)
8.112
F2MC-16FX Family
RETP (Return from Physical Address)
Cause a branch to the physical address pointed to by the stack pointer (SP).
If this instruction is used in combination with the CALLP instruction, control returns to the
instruction following the CALLP instruction after the branch operation is completed.
● Assembler format:
RETP
● Operation:
(PC) ← ((SP)), (SP) ← (SP)+2
[Word addition]
(PCB) ← ((SP)) (Byte transfer), (SP) ← (SP)+2
[Word addition]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
266
Byte count:
1
Cycle count:
5
Odd address correction:
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.112 RETP (Return from Physical Address)
2
F MC-16FX Family
● Example:
RETP
In this example, PC and PCB are popped from the stack specified by USB and SP, and a
branch is caused to address AD4345H.
PC
22 FC
PCB
CCR
SP
F8 FC
08
×
USB
0
PC
43 45
15
SP
PCB
×××××
AD
×
CCR
I S T N Z V C
0
A
4
4
SP
0
D
3
5
0
15
×××××
Memory
15F900
15F8FF
15F8FE
15F8FD
15F8FC
Before execution
CM44-00203-3E
USB
I S T N Z V C
Memory
× ×
F9 00
SP
× ×
0
A
4
4
0
D
3
5
15F900
15F8FF
15F8FE
15F8FD
15F8FC
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.113 ROLC (Rotate Byte Data of Accumulator with Carry to
Left)
8.113
F2MC-16FX Family
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)
Rotate or shift the byte data specified by the operand to the left by one bit,
including the carry flag (C). The most significant bit of the operand is placed in
the carry flag (C).
● Assembler format:
ROLC A
ROLC ear
ROLC eam
● Operation:
MSB
A or operand
LSB
C
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T: Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the MSB of A.
● Byte count and cycle count:
268
Operand
A
ear
eam
Byte count
2
2
2+
Cycle count
1
1
3
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.113 ROLC (Rotate Byte Data of Accumulator with Carry to
Left)
2
F MC-16FX Family
● Example:
ROLC A
In this example, the low-order byte data (32H) of AL and the C flag ("0") are rotated to the left.
AH
A
AL
×× ××
××
CCR
AH
32
××××
A
0
AL
×× ××
CCR
T N Z V C
Before execution
CM44-00203-3E
××
×
64
0 0
×
0
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.114 RORC (Rotate Byte Data of Accumulator with Carry to
Right)
8.114
F2MC-16FX Family
RORC (Rotate Byte Data of Accumulator with Carry
to Right)
Rotate or shift the byte data specified by the operand to the right by one bit,
including the carry flag (C). The least significant bit of the operand is placed in
the carry flag (C).
● Assembler format:
RORC A
RORC ear
RORC eam
● Operation:
MSB
A or operand
LSB
C
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T: Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is zero, cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Byte count and cycle count:
270
Operand
A
ear
eam
Byte count
2
2
2+
Cycle count
1
1
3
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.114 RORC (Rotate Byte Data of Accumulator with Carry to
Right)
2
F MC-16FX Family
● Example:
RORC A
In this example, the low-order byte data (32H) of AL and the C flag ("0") are rotated to the
right.
AH
A
AL
32
×× ××
××
××××
0
T N Z V C
Before execution
CCR
CM44-00203-3E
AH
A
×× ××
CCR
AL
19
××
×
0 0 ×0
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.115 SBBS (Set Bit and Branch if Bit Set)
8.115
F2MC-16FX Family
SBBS (Set Bit and Branch if Bit Set)
Cause a branch if the bit data specified by the first operand is "1".
Control is transferred to the address resulting from word-adding the value resulting from signextending the second operand to the address of the instruction following the SBBS instruction.
After the instruction has been executed, the bit specified by the first operand is set to "1".
● Assembler format:
SBBS addr16:bp,rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+<Byte count>+rel
[Word addition], (addr16:bp) ← 1
If the condition is not satisfied:
(PC) ← (PC)+<Byte count>
[Word addition], (addr16:bp) ← 1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N: Unchanged
Z:
Set when the bit data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
5
Cycle count:
5
● Example:
SBBS 1234H:5,20H
In this example, after bit 7 has been set to "1", a branch is caused (condition satisfied) because
bit 7 in the byte data (7FH) at address 1234H is equal to "1".
PC
E1 00
PC
Memory
Memory
× ×
7 F
272
E1 25
× ×
1234
7 F
1234
× ×
× ×
Before execution
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.116 SCEQ, SCEQI (Scan String Byte until equal with
Increment)
2
F MC-16FX Family
8.116 SCEQ, SCEQI (Scan String Byte until equal with
Increment)
Compare the byte data specified by AH in the space specified by <bank> with
the data of AL. The address is incremented and RW0 is decremented until the
byte data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCEQ [<bank>]
SCEQI [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
[Byte comparison]:
(AH) ← (AH)+1
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to "0".
V:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
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CHAPTER 8 DETAILED INSTRUCTIONS
8.116 SCEQ, SCEQI (Scan String Byte until equal with
Increment)
● Byte count and cycle count:
F2MC-16FX Family
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 × (Number
of times the comparison was performed) in all other cases
● Example:
SCEQ
In this example, the byte data (54H) at the address (031580H) specified by DTB and AH is
compared with the low-order byte data (46H) of AL. Both of them match with the byte data
(46H) at address 031585H.
AH
15 80
A
RW0
AL
00 46
01 00
DTB
CCR
03
A
RW0
AH
15 86
AL
00 46
00 FA
×××××
CCR
T N Z V C
Memory
AH
4
4
4
4
4
5
6
8
9
D
E
4
031586
031585
031584
031583
031582
031581
031580
Before execution
274
DTB
×
03
0 1 0 0
T N Z V C
AH
Memory
4
4
4
4
4
5
6
8
9
D
E
4
131586
031585
031584
031583
031582
031581
031580
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.117 SCEQD (Scan String Byte until equal with Decrement)
2
F MC-16FX Family
8.117 SCEQD (Scan String Byte until equal with
Decrement)
Compare the byte data specified by AH in the space specified by <bank> with
the data of AL. The address is decremented and RW0 is decremented until the
byte data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCEQD [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
[Byte comparison]:
(AH) ← (AH)–1
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to zero.
V:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
275
CHAPTER 8 DETAILED INSTRUCTIONS
8.117 SCEQD (Scan String Byte until equal with Decrement)
F2MC-16FX Family
● Byte count and cycle count:
276
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 ×
(Number of times the comparison was performed) in all other
cases
Odd address correction:
Number of times the comparison was performed
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.118 SCWEQ, SCWEQI (Scan String Word until equal with
Increment)
2
F MC-16FX Family
8.118 SCWEQ, SCWEQI (Scan String Word until equal with
Increment)
Compare the word data specified by AH in the space specified by <bank> with
the data of AL. The address is incremented and RW0 is decremented until the
word data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCWEQ [<bank>]
SCWEQI [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
[Word comparison]:
(AH) ← (AH)+2
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to zero.
V:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
277
CHAPTER 8 DETAILED INSTRUCTIONS
8.118 SCWEQ, SCWEQI (Scan String Word until equal with
Increment)
● Byte count and cycle count:
F2MC-16FX Family
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 ×
(Number of times the comparison was performed) in all other
cases
Odd address correction:
Number of times the comparison was performed
● Example:
SCWEQ
In this example, the word data (E1E0H) at the address (DEC000H) specified by DTB and AH is
compared with the word data (00FFH) of AL. RW0 is set to "0", and processing is terminated.
A
RW0
AH
C0 00
AL
00 FF
00 03
DTB
CCR
DE
A
RW0
AH
C0 06
AL
00 FF
00 00
×××××
DTB
CCR
T N Z V C
AH
6
5
4
3
2
1
0
Memory
DEC006
DEC005
DEC004
DEC003
DEC002
DEC001
DEC000
Before execution
278
1 0 0 1
T N Z V C
Memory
E
E
E
E
E
E
E
×
DE
AH
E
E
E
E
E
E
E
6
5
4
3
2
1
0
DEC006
DEC005
DEC004
DEC003
DEC002
DEC001
DEC000
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.119 SCWEQD (Scan String Word until Equal with Decrement)
2
F MC-16FX Family
8.119 SCWEQD (Scan String Word until Equal with
Decrement)
Compare the word data specified by AH in the space specified by <bank> with
the data of AL. The address is decremented and RW0 is decremented until the
word data matches the data or RW0 becomes equal to zero.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By default,
DTB is assumed.
If RW0 is equal to zero, comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is resumed.
● Assembler format:
SCWEQD [<bank>]
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
[Word comparison]:
(AH) ← (AH)–2
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, N is set when the MSB of the last compare operation result is "1", cleared
otherwise.
Z:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, Z is set when a match with the contents of AL is found; cleared when the
instruction terminates with RW0 being set to zero.
V:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when an overflow has occurred as a result of the last compare
operation; cleared otherwise.
C:
Unchanged if the initial value of RW0 is zero. If the initial value of RW0 is not
zero, V is set when a borrow has occurred as a result of the last compare operation;
cleared otherwise.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
279
CHAPTER 8 DETAILED INSTRUCTIONS
8.119 SCWEQD (Scan String Word until Equal with Decrement)
F2MC-16FX Family
● Byte count and cycle count:
280
Byte count:
2
Cycle count:
1 cycle when RW0 is zero; 3 cycles when RW0 is 1; and 2+2 ×
(Number of times the comparison was performed) in all other
cases
Odd address correction:
Number of times the comparison was performed
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.120 SETB (Set Bit)
2
F MC-16FX Family
8.120 SETB (Set Bit)
Set the contents of the bit address specified by the operand to "1".
● Assembler format:
SETB addr16:bp
SETB dir:bp
SETB io:bp
● Operation:
(Operand) b ← 1
[Bit transfer]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
Byte count and cycle count:
Operand
addr16:bp
dir:bp
io:bp
Byte count
4
3
3
Cycle count
3
3
3
● Example:
SETB 0AA55H:4
In this example, bit 4 in data (FFH) at address AA55H is set to "1".
CCR
00000
TNZVC
Memory
CCR
× ×
6 F
CM44-00203-3E
00000
TNZVC
Memory
× ×
AA55
7 F
AA55
× ×
× ×
Before execution
After execution
FUJITSU MICROELECTRONICS LIMITED
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CHAPTER 8 DETAILED INSTRUCTIONS
8.121 SUB (Subtract Byte Data of Source from Destination to
Destination)
8.121
F2MC-16FX Family
SUB (Subtract Byte Data of Source from Destination
to Destination)
Subtract the byte data specified by the second operand from the byte data
specified by the first operand and restore the result in the first operand. If the
first operand is A, 00H is transferred to upper byte of AL.
● Assembler format:
SUB A,#imm8
SUB A,dir
SUB A,ear
SUB A,eam
SUB ear,A
SUB eam,A
● Operation:
(First operand) ← (First operand)–(Second operand)
[Byte subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
282
First operand
A
A
A
A
ear
eam
Second operand
#imm8
dir
ear
eam
A
A
Byte count
2
2
2
2+
2
2+
Cycle count
1
2
1
2
1
3
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.121 SUB (Subtract Byte Data of Source from Destination to
Destination)
2
F MC-16FX Family
● Example:
SUB A,#22H
In this example, the 8-bit immediate data (22H) is subtracted from the low-order byte data
(01H) of AL.
AH
A
AL
49 01
×× ××
CCR
×××××
AH
A
×× ××
CCR
CM44-00203-3E
×
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
00 DF
After execution
FUJITSU MICROELECTRONICS LIMITED
283
CHAPTER 8 DETAILED INSTRUCTIONS
8.122 SUBC (Subtract Byte Data of AL from AH with Carry to AL)
8.122
F2MC-16FX Family
SUBC (Subtract Byte Data of AL from AH with Carry
to AL)
Subtract the low-order byte data of AL and the carry flag (C) from the low-order
byte data of AH and restore the result in AL. 00H is transferred to upper byte of
AL.
● Assembler format:
SUBC A
● Operation:
(AL) ← (AH)–(AL)–(C)
[Byte subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
SUBC A
In this example, the low-order byte data (D4H) of AL and the carry flag C ("1") are subtracted
from the low-order byte data (30H) of AL. The result is stored in the low-order byte of AL.
A
AH
05 05
AL
00 D4
CCR
×××××
A
AH
05 05
CCR
284
×
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
00 30
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.123 SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
2
F MC-16FX Family
8.123 SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
Subtract the byte data specified by the second operand and the carry flag (C)
from the byte data of the accumulator (A) and restore the result in A. 00H is
transferred to upper byte of AL.
● Assembler format:
SUBC A,ear
SUBC A,eam
● Operation:
(A) ← (A)–(Second operand)–(C)
[Byte subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
1
2
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285
CHAPTER 8 DETAILED INSTRUCTIONS
8.123 SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
● Example:
F2MC-16FX Family
SUBC A,R1
In this example, the byte data (54H) of R1 and the C flag ("0") are subtracted from the loworder byte data (35H) of AL.
AH
A
AL
00 35
×× ××
R1
CCR
AH
A
×× ××
54
××××
0
R1
CCR
286
×
54
1 0 0 1
T N Z V C
T N Z V C
Before execution
AL
00 E1
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.124 SUBCW (Subtract Word Data of Effective Address from
Accumulator with Carry to Accumulator)
2
F MC-16FX Family
8.124 SUBCW (Subtract Word Data of Effective Address
from Accumulator with Carry to Accumulator)
Subtract the word data specified by the second operand and the carry flag (C)
from the low-order word data of the accumulator (A) and restore the result in A.
● Assembler format:
SUBCW A,ear
SUBCW A,eam
● Operation:
(A) ← (A)–(Second operand)–(C)
[Word subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
1
2
Odd address correction
0
1
FUJITSU MICROELECTRONICS LIMITED
287
CHAPTER 8 DETAILED INSTRUCTIONS
8.124 SUBCW (Subtract Word Data of Effective Address from
Accumulator with Carry to Accumulator)
● Example:
F2MC-16FX Family
SUBCW A,0E024H
In this example, the word data (A95BH) at address E024H and the C flag ("1") are subtracted
from the word data (7558H) of AL.
A
AH
AL
×× ××
75 58
CCR
××××
A
1
AH
AL
×× ××
CB FC
CCR
A 9
5 B
Memory
E025
E024
Before execution
288
1 0 0 1
T N Z V C
T N Z V C
Memory
×
A 9
5 B
E025
E024
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.125 SUBDC (Subtract Decimal Data of AL from AH with Carry
to AL)
2
F MC-16FX Family
8.125 SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)
Subtract the low-order byte data of AL and the carry flag (C) from the low-order
byte data of AH and restore the result in AL. 00H is transferred to upper byte of
AL.
● Assembler format:
SUBDC A
● Operation:
(AL) ← (AH)–(AL)–(C)
[Decimal subtraction with a carry]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Undefined
C:
Set when a borrow has occurred as a result of the decimal operation, cleared otherwise.
● Byte count and cycle count:
Byte count:
1
Cycle count:
2
● Example:
SUBDC A
In this example, the byte data (86H) of AL and the C flag ("0") are subtracted from the byte
data (86H) of AH in decimal operation.
AH
A
××
AL
××
86
CCR
AH
86
××××
A
0
××
AL
86
CCR
CM44-00203-3E
×
0 1
×
0
T N Z V C
T N Z V C
Before execution
00 00
After execution
FUJITSU MICROELECTRONICS LIMITED
289
CHAPTER 8 DETAILED INSTRUCTIONS
8.126 SUBL (Subtract Long Word Data of Source from
Destination to Destination)
8.126
F2MC-16FX Family
SUBL (Subtract Long Word Data of Source from
Destination to Destination)
Subtract the long word data specified by the second operand from the long
word data of the accumulator (A) and restore the result in A.
● Assembler format:
SUBL A,#imm32
SUBL A,ear
SUBL A,eam
● Operation:
(First operand) ← (First operand)–(Second operand)
[Long word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
290
First operand
A
A
A
Second operand
#imm32
ear
eam
Byte count
5
2
2+
Cycle count
2
2
3
Odd address correction
0
0
1
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.126 SUBL (Subtract Long Word Data of Source from
Destination to Destination)
2
F MC-16FX Family
● Example:
SUBL A,0FD12H
In this example, the long word data (525F31BDH) at address FD12H is subtracted from the
long word data (34B3F201H) of the accumulator (A).
A
AH
34 B3
AL
F2 01
CCR
A
AH
E2 54
×××××
AL
C0 44
CCR
5
5
3
B
2
F
1
D
Memory
FD16
FD15
FD14
FD13
FD12
Before execution
CM44-00203-3E
1 0 0 1
T N Z V C
T N Z V C
Memory
×
5
5
3
B
2
F
1
D
FD16
FD15
FD14
FD13
FD12
After execution
FUJITSU MICROELECTRONICS LIMITED
291
CHAPTER 8 DETAILED INSTRUCTIONS
8.127 SUBW (Subtract Word Data of Source from Destination to
Destination)
8.127
F2MC-16FX Family
SUBW (Subtract Word Data of Source from
Destination to Destination)
Subtract the word data specified by the second operand from the word data
specified by the first operand and restore the result in the first operand.
● Assembler format:
SUBW A,#imm16
SUBW A,ear
SUBW A,eam
SUBW ear,A
SUBW eam,A
● Operation:
(First operand) ← (First operand)–(Second operand)
[Word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
292
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Byte count
3
2
2+
2
2+
Cycle count
1
1
2
1
3
Odd address correction
0
0
1
0
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
2
F MC-16FX Family
● Example:
CHAPTER 8 DETAILED INSTRUCTIONS
8.127 SUBW (Subtract Word Data of Source from Destination to
Destination)
SUBW @RW0+,A
In this example, the word data (3104H) of AL is subtracted from the word data (5DABH) of the
address (E2A4H) specified by the first operand (@RW0+).
A
AH
AL
×× ××
31 04
RW0
CCR
E2 A4
×××××
A
AH
AL
×× ××
31 04
RW0
CCR
T N Z V C
E2A5
E2A4
Before execution
CM44-00203-3E
×
0 0 0 0
T N Z V C
Memory
Memory
5 D
A B
E2 A6
2 C
A 7
E2A5
E2A4
After execution
FUJITSU MICROELECTRONICS LIMITED
293
CHAPTER 8 DETAILED INSTRUCTIONS
8.128 SUBW (Subtract Word Data of AL from AH to AL)
8.128
F2MC-16FX Family
SUBW (Subtract Word Data of AL from AH to AL)
Subtract the word data of AL from the word data of AH and restore the result to
AL.
● Assembler format:
SUBW A
● Operation:
(AL) ← (AH)–(AL)
[Word subtraction]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
SUBW A
In this example, the word data (1019H) of AL is subtracted from the word data (83A2H) of AH.
The subtraction result (7389H) is set to AL.
A
AH
AL
83 A2
10 19
CCR
×××××
A
AH
AL
83 A2
73 89
CCR
T N Z V C
Before execution
294
×
0 0 1 0
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.129 SWAP (Swap Byte Data of Accumulator)
2
F MC-16FX Family
8.129 SWAP (Swap Byte Data of Accumulator)
Swap the high- and low-order bytes of the word data for the accumulator (A)
with each other.
● Assembler format:
SWAP
● Operation:
temp ← AL[7:0]
AL[7:0] ← AL[15:8]
AL[15:8] ← temp
[Byte swapping]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
SWAP
In this example, the high-order byte data (06H) of AL is exchanged with the low-order byte
data (90H) of AL.
AH
A
×× ××
CCR
AL
AH
AL
06 90
×× ××
90 06
×××××
A
CCR
T N Z V C
Before execution
CM44-00203-3E
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.130 SWAPW (Swap Word Data of Accumulator)
8.130
F2MC-16FX Family
SWAPW (Swap Word Data of Accumulator)
Swap the high- and low-order words of the long word data for the accumulator
(A) with each other.
● Assembler format:
SWAPW
● Operation:
temp ← (AH)
(AH) ← (AL)
(AL) ← temp
[Word swapping]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
SWAPW
In this example, the word data (1986H) of AH is exchanged with the word data (9861H) of AL.
A
AH
AL
19 86
98 61
CCR
×××××
A
AH
AL
98 61
19 86
CCR
T N Z V C
Before execution
296
×××××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.131 UNLINK (Unlink and Create New Stack Frame)
2
F MC-16FX Family
8.131 UNLINK (Unlink and Create New Stack Frame)
Restore an old frame pointer from a stack.
● Assembler format:
UNLINK
● Operation:
(SP) ← (RW3), (RW3) ← ((SP)), (SP) ← (SP)+2
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
Odd address correction:
1
● Example:
UNLINK
In this example, the word data (E020H) of RW3 is transferred to SP, and RW3 is popped from
the stack specified by SP.
SP
RW3
E0 00
SP
E0 20
A 0
4 6
A0 46
RW3
Memory
E0 22
Memory
E020
SP
× ×
A 0
4 6
SP
× ×
E000
Before execution
CM44-00203-3E
E022
E021
E020
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.132 WBTc (Wait until Bit Condition Satisfied)
8.132
F2MC-16FX Family
WBTc (Wait until Bit Condition Satisfied)
This instruction keeps reading data from the bit address specified by the
operand until that data satisfies the conditions. Once the data at the specified
bit address satisfies the conditions, control is transferred to the instruction
subsequent to the WBTc instruction.
● Assembler format:
WBTC io:bp
WBTS io:bp
● Operation:
Data is read from the bit address specified by io:bp until the data satisfies the condition. If the
data from the bit address satisfies the condition, control is transferred to the next instruction.
Interrupts are acceptable while the read operation is repeated with the condition not satisfied.
If an interrupt is generated in this state, the RETI instruction causes control to return to the
WBTc instruction, not to the instruction following the WBTc instruction.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
Instruction
WBTC
WBTS
Condition
Bit data=0
Bit data=1
Byte count
3
3
Cycle count
298
Undefined
Undefined
(Until the condition is satisfied) (Until the condition is satisfied)
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.132 WBTc (Wait until Bit Condition Satisfied)
2
F MC-16FX Family
● Example:
WBTS 34H:7
In this example, wait until bit 7 in the byte data at address 34H is set to "1".
PC
E1 00
Memory
Peripheral
register
× ×
7 F
0034H
× ×
Before execution
CM44-00203-3E
Data is read from address 34H until bit 7 is set to "1"
(because of resource operation, for example).
When bit 7 becomes "1", execute the next instruction.
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.133 XCH (Exchange Byte Data of Source to Destination)
8.133
F2MC-16FX Family
XCH (Exchange Byte Data of Source to Destination)
Exchange the byte data specified by the first operand with that specified by the
second operand.
If the first operand is A, the high-order byte of AL is set to 00H.
● Assembler format:
XCH A,ear
XCH A,eam
XCH Ri,ear
XCH Ri,eam
● Operation:
temp ← (First operand)
(First operand) ← (Second operand)
(Second operand) ← temp
[Byte exchange]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
300
First operand
A
A
Ri
Ri
Second operand
ear
eam
ear
eam
Byte count
2
2+
2
2+
Cycle count
1
2
2
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.133 XCH (Exchange Byte Data of Source to Destination)
2
F MC-16FX Family
● Example:
XCH R4,@RW0+
In this example, the byte data (F1H) of R4 is exchanged with the byte data (22H) at address
(0060H) specified by the second operand (@RW0+).
RW0
00 60
R4
CCR
RW0
F1
R4
×××××
CCR
T N Z V C
2 2
×××××
Memory
0061
0060
Before execution
CM44-00203-3E
22
T N Z V C
Memory
RW0
00 61
RW0
F 1
0061
0060
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.134 XCHW (Exchange Word Data of Source to Destination)
8.134
F2MC-16FX Family
XCHW (Exchange Word Data of Source to
Destination)
Exchange the word data specified by the first operand with that specified by
the second operand.
● Assembler format:
XCHW A,ear
XCHW A,eam
XCHW RWi,ear
XCHW RWi,eam
● Operation:
temp ← (First operand)
(First operand) ← (Second operand)
(Second operand) ← temp
[Word exchange]
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Byte count and cycle count:
302
First operand
A
A
RWi
RWi
Second operand
ear
eam
ear
eam
Byte count
2
2+
2
2+
Cycle count
1
2
2
2
Odd address correction
0
2
0
2
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.134 XCHW (Exchange Word Data of Source to Destination)
2
F MC-16FX Family
● Example:
XCHW A,@RW0
In this example, the word data (24B4H) of AL is exchanged with the word data (2D58H) at
address (E001H) specified by the second operand (@RW0).
A
AH
AL
×× ××
34 B4
RW0
E0 01
CCR
A
×××××
AH
AL
×× ××
2D 58
RW0
E0 01
CCR
T N Z V C
T N Z V C
Memory
Memory
RW0
2 D
5 8
E002
E001
Before execution
CM44-00203-3E
×××××
RW0
3 4
B 4
E002
E001
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.135 XOR (Exclusive Or Byte Data of Destination and Source
to Destination)
8.135
F2MC-16FX Family
XOR (Exclusive Or Byte Data of Destination and
Source to Destination)
Take the logical exclusive OR of the byte data specified by the first operand
and the byte data specified by the second operand and restore the result in the
first operand.
● Assembler format:
XOR A,#imm8
XOR A,ear
XOR A,eam
XOR ear,A
XOR eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand)
[Byte logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
304
First operand
A
A
A
ear
eam
Second operand
#imm8
ear
eam
A
A
Byte count
2
2
2+
2
2+
Cycle count
1
1
2
1
3
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.135 XOR (Exclusive Or Byte Data of Destination and Source
to Destination)
2
F MC-16FX Family
● Example:
XOR 0052H,A
In this example, the logical exclusive OR is taken between the byte data (FAH) at address
0052H and the low-order byte data (55H) of AL.
A
AH
AL
×× ××
00 55
CCR
×××××
A
AH
AL
×× ××
00 55
CCR
T N Z V C
Before execution
CM44-00203-3E
1 0 0
×
T N Z V C
Memory
Memory
F A
×
000052
A F
000052
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.136 XORL (Exclusive Or Long Word Data of Destination and
Source to Destination)
8.136
F2MC-16FX Family
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination)
Take the logical exclusive OR of the long word data for the accumulator (A) and
that specified by the second operand and restore the result in A.
● Assembler format:
XORL A,ear
XORL A,eam
● Operation:
(A) ← (A) xor (Second operand)
[Long word logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
306
First operand
A
A
Second operand
ear
eam
Byte count
2
2+
Cycle count
2
3
Odd address correction
0
1
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.136 XORL (Exclusive Or Long Word Data of Destination and
Source to Destination)
2
F MC-16FX Family
● Example:
XORL A,0FFF0H
In this example, the logical exclusive OR is taken between the long word data (8252FEACH)
of the accumulator (A) and the long word data (FF55AA00H) at address FFF0H.
A
AH
AL
82 52
FE AC
CCR
A
AH
AL
7D 07
54 AC
×××××
CCR
T N Z V C
Memory
F
5
A
0
F
5
A
0
0 0 0
×
T N Z V C
Memory
FFF3
FFF2
FFF1
FFF0
Before execution
CM44-00203-3E
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.137 XORW (Exclusive Or Word Data of AH and AL to AL)
8.137
F2MC-16FX Family
XORW (Exclusive Or Word Data of AH and AL to AL)
Take the logical exclusive OR for the word data of AH and that of AL and
restore the result in AL.
● Assembler format:
XORW A
● Operation:
(AL) ← (AH) xor (AL)
[Word logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
XORW A
In this example, the logical exclusive OR is taken between the word data (AB98H) of AL and
the word data (0426H) of AH.
A
AH
AL
04 26
AB 98
CCR
×××××
AH
A
AL
04 26
CCR
T N Z V C
Before execution
308
AF BE
×
1 0 0
×
T N Z V C
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.138 XORW (Exclusive Or Word Data of Destination and
Source to Destination)
2
F MC-16FX Family
8.138 XORW (Exclusive Or Word Data of Destination and
Source to Destination)
Take the logical exclusive OR of the word data specified by the first operand
and the word data specified by the second operand and restore the result in the
first operand.
● Assembler format:
XORW A,#imm16
XORW A,ear
XORW A,eam
XORW ear,A
XORW eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand)
[Word logical exclusive OR]
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T: Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is zero, cleared otherwise.
V:
Cleared
C:
Unchanged
● Byte count and cycle count:
CM44-00203-3E
First operand
A
A
A
ear
eam
Second operand
#imm16
ear
eam
A
A
Byte count
3
2
2+
2
2+
Cycle count
1
1
2
1
3
Odd address correction
0
0
1
0
2
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CHAPTER 8 DETAILED INSTRUCTIONS
8.138 XORW (Exclusive Or Word Data of Destination and
Source to Destination)
● Example:
F2MC-16FX Family
XORW 0E001H,A
In this example, the logical exclusive OR is taken between the word data (8342H) at address
E001H and the word data (5963H) of AL.
AH
A
×× ××
CCR
AL
AH
AL
59 63
×× ××
59 63
×××××
A
CCR
T N Z V C
E002
E001
Before execution
310
1 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
×
D A
2 1
E002
E001
After execution
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CM44-00203-3E
CHAPTER 8 DETAILED INSTRUCTIONS
8.139 ZEXT (Zero Extend from Byte Data to Word Data)
2
F MC-16FX Family
8.139 ZEXT (Zero Extend from Byte Data to Word Data)
Transfer 00H to upper byte of AL.
● Assembler format:
ZEXT
● Operation:
AL[15:8] ← 00H
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T: Unchanged
N:
Cleared
Z:
Set when the zero-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
ZEXT
In this example, the upper byte of AL is set to 00H.
AH
A
AL
×× ××
××
CCR
80
×××××
AH
A
AL
×× ××
CCR
T N Z V C
Before execution
CM44-00203-3E
00 80
×
0 0
××
T N Z V C
After execution
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CHAPTER 8 DETAILED INSTRUCTIONS
8.140 ZEXTW (Zero Extend from Word Data to Long Word Data)
8.140
F2MC-16FX Family
ZEXTW (Zero Extend from Word Data to Long Word
Data)
Transfer 0000H to AH.
● Assembler format:
ZEXTW
● Operation:
AH ← 0000H
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T: Unchanged
N:
Cleared
Z:
Set when the zero-extended data is zero, cleared otherwise.
V and C:
Unchanged
● Byte count and cycle count:
Byte count:
1
Cycle count:
1
● Example:
ZEXTW
In this example, AH is set to 0000H.
A
AH
AL
×× ××
FF 80
CCR
×××××
A
AH
AL
00 00
FF 80
CCR
T N Z V C
Before execution
312
×
0 0
××
T N Z V C
After execution
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
This appendix includes lists and maps of
instructions for the F2MC-16FX CPU.
APPENDIX A Explanation of Instruction Lists
APPENDIX B Instruction Lists (351 Instructions)
APPENDIX C Instruction Maps
CM44-00203-3E
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APPENDIX
APPENDIX A Explanation of Instruction Lists
F2MC-16FX Family
APPENDIX A Explanation of Instruction Lists
This section explains items and symbols used in each instruction list included
in Instruction Lists (351 Instructions).
A.1 Items Used in Instruction Lists
A.2 Symbols Used in Instruction Lists
A.3 Effective Address Field
314
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APPENDIX
APPENDIX A Explanation of Instruction Lists
2
F MC-16FX Family
A.1 Items Used in Instruction Lists
Table A.1-1 explains the items used in the instruction lists.
Table A.1-1 Explanation of the Items Used in the Instruction Lists
Item
Mnemonic
Description
Upper-case letters and symbols:
Lower-case letters:
Numbers after lower-case letters:
Described as they appear in assembler.
Replaced when described in assembler.
Indicate the bit width within the instruction.
#
Indicates the byte count.
~
Indicates the cycle count.
B
Indicates the cycle count required for correcting odd addresses.
The actual cycle count during instruction execution is the correction value added to the
value in the "~" column.
Operation
Indicates operation of instruction.
LH
Indicates special operations involving bits 15 through 08 of the accumulator.
Z: Transfers "0".
X: Sign-extended transfer through sign extension.
- : Transfers nothing.
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH.
- : No transfer
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH using sign extension AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack),
T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
- : No change
S: Set by execution of instruction.
R: Clear by execution of instruction.
Z
V
C
RMW
CM44-00203-3E
Indicates whether the instruction is a read-modify-write instruction (a single instruction
that reads data from memory, etc., processes the data, and then writes the result to
memory.).
*: Instruction is a read-modify-write instruction.
-: Instruction is not a read-modify-write instruction.
Note:
A read-modify-write instruction cannot be used on addresses of the I/O register, etc.,
that have different meanings depending on whether they are read or written.
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APPENDIX
APPENDIX A Explanation of Instruction Lists
F2MC-16FX Family
■ Execution cycle count
The cycle count required to execute instructions (execution cycle count) is the summation of
the cycle count of each instruction and the odd address correction value determined by access
conditions for data. At the actual instruction execution time, the execution cycle count may
become larger than the calculated value due to the instruction fetch delay, the data access
conflict, etc. Especially, when performing instruction fetch and data access from an external
bus by using the external bus interface, the execution cycle count becomes larger than the
calculated value.
■ Odd address correction
For some instructions, the execution cycles increases when performing data access to odd
addresses. The execution cycles that increases at data access time to odd addresses is shown
under the title of "odd address correction" in item B in the instruction list.
316
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CM44-00203-3E
APPENDIX
APPENDIX A Explanation of Instruction Lists
2
F MC-16FX Family
A.2 Symbols Used in Instruction Lists
Table A.2-1 explains the symbols used in the instruction lists.
■ Explanation of the Symbols Used in the Instruction Lists
Table A.2-1 Explanation of the Symbols Used in the Instruction Lists (1 / 2)
Symbol
A
Explanation
32 bit accumulator
The bit length used is different for each instruction.
Byte: Lower 8 bits of AL
Word: 16 bits of AL
Long Word: 32 bits of AL and AH
AH
Upper 16 bits of A
AL
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
Ri
R0, R1, R2, R3, R4, R5, R6, R7
Rj
R0, R1, R2, R3
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of address 24
ad24 16-23
Bit16 to bit23 of address 24
io
CM44-00203-3E
I/O area (000000H to 0000FFH)
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APPENDIX
APPENDIX A Explanation of Instruction Lists
F2MC-16FX Family
Table A.2-1 Explanation of the Symbols Used in the Instruction Lists (2 / 2)
Symbol
imm4
4-bit immediate data
imm8
8-bit immediate data
imm16
16-bit immediate data
imm32
32-bit immediate data
ext (imm8)
16-bit data signed and extended from 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
318
Explanation
Bit offset value
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
Branch specification relative to PC
ear
Effective addressing (codes 00 to 07)
eam
Effective addressing (codes 08 to 1F)
rlst
Register list
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
APPENDIX A Explanation of Instruction Lists
2
F MC-16FX Family
A.3 Effective Address Field
Table A.3-1 lists address formats used in the effective address field.
Table A.3-1 Effective Address Field
Code
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RL0
RW1
(RL0)
RW2
RL1
RW3
(RL1)
RW4
RL2
RW5
(RL2)
RW6
RL3
RW7
(RL3)
@RW0
@RW1
@RW2
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
@RW6+disp8
@RW7+disp8
@RW0+disp16
@RW1+disp16
@RW2+disp16
@RW3+disp16
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
Address format
Byte count of address
expansion part*
Register direct
Note: The general purpose register name
on the left notation corresponds to
the byte,
word
and long-word types.
-
Register indirect
0
Register indirect with post-incrementing
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit
displacement
2
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
*: The byte count of the address expansion part is shown in the "#" (byte count) column. "numeric value+", such as "2+",
written in the detailed instructions indicates the byte count of the address expansion part added to the value.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
319
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
APPENDIX B Instruction Lists (351 Instructions)
Instruction lists used by the assembler is shown here.
For each item and symbol in the instruction lists, see “APPENDIX A
Explanation of Instruction Lists”.
Table B-1 Transfer Instructions (Byte) : 41 instructions
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
#
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RLi+disp8
A, #imm4
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A, @RWi+disp8
A, @RLi+disp8
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
A, ear
A, eam
Ri, ear
Ri, eam
2
3
1
2
2+
2
2
2
3
1
2
3
1
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 / 2*1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Operation
byte (A) ←(dir)
byte (A) ←(addr16)
byte (A) ←(Ri)
byte (A) ←(ear)
byte (A) ←(eam)
byte (A) ←(io)
byte (A) ←imm8
byte (A) ←((A))
byte (A) ←((RLi)+disp8)
byte (A) ←imm4
byte (A) ←(dir)
byte (A) ←(addr16)
byte (A) ←(Ri)
byte (A) ←(ear)
byte (A) ←(eam)
byte (A) ←(io)
byte (A) ←imm8
byte (A) ←((A))
byte (A) ←((RWi)+disp8)
byte (A) ←((RLi)+disp8)
byte (dir) ←(A)
byte (addr16) ←(A)
byte (Ri) ←(A)
byte (ear) ←(A)
byte (eam) ←(A)
byte (io) ←(A)
byte ((RLi)+disp8) ←(A)
byte (Ri) ←(ear)
byte (Ri) ←(eam)
byte (ear) ←(Ri)
byte (eam) ←(Ri)
byte (Ri) ←imm8
byte (io) ←imm8
byte (dir) ←imm8
byte (ear) ←imm8
byte (eam) ←imm8
byte ((A)) ←(AH)
byte (A) ←→(ear)
byte (A) ←→(eam)
byte (Ri) ←→(ear)
byte (Ri) ←→(eam)
LH AH
I
S
T
N
Z
V
C RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
*1 : 1 cycle in case of eam is [email protected][email protected][email protected]+RW7, 2 cycles in other case.
320
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-2 Transfer Instructions (Word, Long Word) : 38 instructions
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
#
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
dir, A
addr16, A
SP, A
RWi, A
ear, A
eam, A
io, A
@RWi+disp8, A
@RLi+disp8, A
RWi, ear
RWi, eam
ear, RWi
eam, RWi
RWi, #imm16
io, #imm16
ear, #imm16
eam, #imm16
@AL, AH
A, ear
A, eam
RWi, ear
RWi, eam
A, ear
A, eam
A, #imm32
ear, A
eam, A
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
2
2
2
2
2
2
2
3 / 2*1
1
1
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
2
0
2
0
1
0
0
1
Operation
word (A) ←(dir)
word (A) ←(addr16)
word (A) ←(SP)
word (A) ←(RWi)
word (A) ←(ear)
word (A) ←(eam)
word (A) ←(io)
word (A) ←((A))
word (A) ←imm16
word (A) ←((RWi)+disp8)
word (A) ←((RLi)+disp8)
word (dir) ←(A)
word (addr16) ←(A)
word (SP) ←(A)
word (RWi) ←(A)
word (ear) ←(A)
word (eam) ←(A)
word (io) ←(A)
word ((RWi)+disp8) ←(A)
word ((RLi)+disp8) ←(A)
word (RWi) ←(ear)
word (RWi) ←(eam)
word (ear) ←(RWi)
word (eam) ←(RWi)
word (RWi) ←imm16
word (io) ←imm16
word (ear) ←imm16
word (eam) ←imm16
word ((A)) ←(AH)
word (A) ←→ear
word (A) ←→eam
word (RWi) ←→ear
word (RWi) ←→eam
long (A) ←(ear)
long (A) ←(eam)
long (A) ←imm32
long (ear) ←(A)
long (eam) ←(A)
LH AH
-
*
*
*
*
*
*
*
*
*
*
-
I
S
T
N
Z
V
C RMW
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
*1 : 3 cycle in case of eam is @RWi+, 2 cycles in other case.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
321
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-3 Addition/Subtraction Instructions (Byte, Word, Long Word) : 42 instructions
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
322
#
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A
A, ear
A, eam
A, #imm16
ear, A
eam, A
A, ear
A, eam
A
A, ear
A, eam
A, #imm16
ear, A
eam, A
A, ear
A, eam
A, ear
A, eam
A, #imm32
A, ear
A, eam
A, #imm32
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
B
1
2
1
2
1
3
1
1
2
2
1
2
1
2
1
3
1
1
2
2
1
1
2
1
1
3
1
2
1
1
2
1
1
3
1
2
2
3
2
2
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
1
0
0
1
0
Operation
LH AH I
byte (A) ←(A) + imm8
byte (A) ←(A) + (dir)
byte (A) ←(A) + (ear)
byte (A) ←(A) + (eam)
byte (ear) ←(ear) + (A)
byte (eam) ←(eam) + (A)
byte (A) ←(AH) + (AL) + (C)
byte (A) ←(A) + (ear) + (C)
byte (A) ←(A) + (eam) + (C)
byte (A) ←(AH) + (AL) + (C) : decimal
byte (A) ←(A) - imm8
byte (A) ←(A) - (dir)
byte (A) ←(A) - (ear)
byte (A) ←(A) - (eam)
byte (ear) ←(ear) - (A)
byte (eam) ←(eam) - (A)
byte (A) ←(AH) - (AL) - (C)
byte (A) ←(A) - (ear) - (C)
byte (A) ←(A) - (eam) - (C)
byte (A) ←(AH) - (AL) - (C) : decimal
word (A) ←(AH) + (AL)
word (A) ←(A) + (ear)
word (A) ←(A) + (eam)
word (A) ←(A) + imm16
word (ear) ←(ear) + (A)
word (eam) ←(eam) + (A)
word (A) ←(A) + (ear) + (C)
word (A) ←(A) + (eam) + (C)
word (A) ←(AH) - (AL)
word (A) ←(A) - (ear)
word (A) ←(A) - (eam)
word (A) ←(A) - imm16
word (ear) ←(ear) - (A)
word (eam) ←(eam) - (A)
word (A) ←(A) - (ear) - (C)
word (A) ←(A) - (eam) - (C)
long (A) ←(A) + (ear)
long (A) ←(A) + (eam)
long (A) ←(A) + imm32
long (A) ←(A) - (ear)
long (A) ←(A) - (eam)
long (A) ←(A) - imm32
FUJITSU MICROELECTRONICS LIMITED
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
S
T
N
Z
V
C RMW
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-4 Increment/Decrement Instructions (Byte, Word, Long Word) : 12 instructions
Mnemonic
INC
INC
DEC
DEC
INCW
INCW
DECW
DECW
INCL
INCL
DECL
DECL
#
ear
eam
ear
eam
ear
eam
ear
eam
ear
eam
ear
eam
CM44-00203-3E
2
2+
2
2+
2
2+
2
2+
2
2+
2
2+
B
1
3
1
3
1
3
1
3
2
4
2
4
0
0
0
0
0
2
0
2
0
2
0
2
Operation
byte (ear) ←(ear) + 1
byte (eam) ←(eam) + 1
byte (ear) ←(ear) - 1
byte (eam) ←(eam) - 1
word (ear) ←(ear) + 1
word (eam) ←(eam) + 1
word (ear) ←(ear) - 1
word (eam) ←(eam) - 1
long (ear) ←(ear) + 1
long (eam) ←(eam) + 1
long (ear) ←(ear) - 1
long (eam) ←(eam) - 1
LH AH
-
FUJITSU MICROELECTRONICS LIMITED
-
I
S
T
N
Z
V
C RMW
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
323
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-5 Compare Instructions (Byte, Word, Long Word) : 11 instructions
Mnemonic
CMP
CMP
CMP
CMP
CMPW
CMPW
CMPW
CMPW
CMPL
CMPL
CMPL
324
#
A
A, ear
A, eam
A, #imm8
A
A, ear
A, eam
A, #imm16
A, ear
A, eam
A, #imm32
1
2
2+
2
1
2
2+
3
2
2+
5
B
1
1
2
1
1
1
2
1
2
3
2
0
0
0
0
0
0
1
0
0
1
0
Operation
byte (AH) - (AL)
byte (A) - (ear)
byte (A) - (eam)
byte (A) - imm8
word (AH) - (AL)
word (A) - (ear)
word (A) - (eam)
word (A) - imm16
long (A) - (ear)
long (A) - (eam)
long (A) - imm32
LH AH
-
FUJITSU MICROELECTRONICS LIMITED
-
I
S
T
N
Z
V
C RMW
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-6 Unsigned Multiplication/Division Instructions (Word, Long Word) : 11 instructions
Mnemonic
#
B
*1
0
DIVU
A
1
4/9
DIVU
A, ear
2
4 / 9*1
0
DIVU
A, eam
2+ 5 / 11*2
0
DIVUW
A, ear
2
4 / 17*3
0
DIVUW
A, eam
2+ 5 / 19*4
2
MULU
MULU
MULU
MULUW
MULUW
MULUW
A
A, ear
A, eam
A
A, ear
A, eam
1
2
2+
1
2
2+
0
0
0
0
0
1
2
2
3
4
4
5
Operation
word (AH) / byte (AL)
quotient →byte (AL), remainder →byte (AH)
word (A) / byte (ear)
quotient →byte (A), remainder →byte (ear)
word (A) / byte (eam)
quotient →byte (A), remainder →byte (eam)
long (A) / word (ear)
quotient →word (A), remainder →word (ear)
long (A) / word (eam)
quotient →word (A), remainder →word (eam)
byte (AH) * byte (AL) →word (A)
byte (A) * byte (ear) →word (A)
byte (A) * byte (eam) →word (A)
word (AH) * word (AL) →long (A)
word (A) * word (ear) →long (A)
word (A) * word (eam) →long (A)
LH AH I
S
T
N
Z
V
C RMW
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
-
-
-
*1 : 4 cycles in case of overflow, 9 cycles in other case.
*2 : 5 cycles in case of overflow, 11 cycles in other case.
*3 : 4 cycles in case of overflow, 17 cycles in other case.
*4 : 5 cycles in case of overflow, 19 cycles in other case.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
325
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-7 Signed Multiplication/Division Instructions (Word, Long Word) : 11 instructions
Mnemonic
#
B
*1
DIV
A
2
5 / 11
0
DIV
A, ear
2
5 / 11*1
0
DIV
A, eam
2+ 6 / 13*2
0
DIVW
A, ear
2
5 / 19*3
0
DIVW
A, eam
2+ 6 / 21*4
2
MUL
MUL
MUL
MULW
MULW
MULW
A
A, ear
A, eam
A
A, ear
A, eam
2
2
2+
2
2
2+
0
0
0
0
0
1
4
4
5
6
6
7
Operation
word (AH) / byte (AL)
quotient →byte (AL), remainder →byte (AH)
word (A) / byte (ear)
quotient →byte (A), remainder →byte (ear)
word (A) / byte (eam)
quotient →byte (A), remainder →byte (eam)
long (A) / word (ear)
quotient →word (A), remainder →word (ear)
long (A) / word (eam)
quotient →word (A), remainder →word (eam)
byte (AH) * byte (AL) →word (A)
byte (A) * byte (ear) →word (A)
byte (A) * byte (eam) →word (A)
word (AH) * word (AL) →long (A)
word (A) * word (ear) →long (A)
word (A) * word (eam) →long (A)
LH AH I
S
T
N
Z
V
C RMW
Z
-
-
-
-
-
-
*
*
-
Z
-
-
-
-
-
-
*
*
-
Z
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
*
*
-
-
-
-
-
-
-
-
-
-
-
*1 : 5 cycles in case of overflow, 11 cycles in other case.
*2 : 6 cycles in case of overflow, 13 cycles in other case.
*3 : 5 cycles in case of overflow, 19 cycles in other case.
*4 : 6 cycles in case of overflow, 21 cycles in other case.
326
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-8 Logic Instructions (Byte, Word, Long Word) : 45 instructions
Mnemonic
AND
AND
AND
AND
AND
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
NOT
NOT
NOT
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
ORW
ORW
ORW
ORW
ORW
ORW
XORW
XORW
XORW
XORW
XORW
XORW
NOTW
NOTW
NOTW
ANDL
ANDL
ORL
ORL
XORL
XORL
#
A, #imm8
A, ear
A, eam
ear, A
eam, A
A, #imm8
A, ear
A, eam
ear, A
eam, A
A, #imm8
A, ear
A, eam
ear, A
eam, A
A
ear
eam
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
A, #imm16
A, ear
A, eam
ear, A
eam, A
A
ear
eam
A, ear
A, eam
A, ear
A, eam
A, ear
A, eam
CM44-00203-3E
2
2
2+
2
2+
2
2
2+
2
2+
2
2
2+
2
2+
1
2
2+
1
3
2
2+
2
2+
1
3
2
2+
2
2+
1
3
2
2+
2
2+
1
2
2+
2
2+
2
2+
2
2+
B
1
1
2
1
3
1
1
2
1
3
1
1
2
1
3
1
1
3
1
1
1
2
1
3
1
1
1
2
1
3
1
1
1
2
1
3
1
1
3
2
3
2
3
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
0
1
0
2
0
0
0
1
0
2
0
0
2
0
1
0
1
0
1
Operation
byte (A) ←(A) and imm8
byte (A) ←(A) and (ear)
byte (A) ←(A) and (eam)
byte (ear) ←(ear) and (A)
byte (eam) ←(eam) and (A)
byte (A) ←(A) or imm8
byte (A) ←(A) or (ear)
byte (A) ←(A) or (eam)
byte (ear) ←(ear) or (A)
byte (eam) ←(eam) or (A)
byte (A) ←(A) xor imm8
byte (A) ←(A) xor (ear)
byte (A) ←(A) xor (eam)
byte (ear) ←(ear) xor (A)
byte (eam) ←(eam) xor (A)
byte (A) ←not (A)
byte (ear) ←not (ear)
byte (eam) ←not (eam)
word (A) ←(AH) and (A)
word (A) ←(A) and imm16
word (A) ←(A) and (ear)
word (A) ←(A) and (eam)
word (ear) ←(ear) and (A)
word (eam) ←(eam) and (A)
word (A) ←(AH) or (A)
word (A) ←(A) or imm16
word (A) ←(A) or (ear)
word (A) ←(A) or (eam)
word (ear) ←(ear) or (A)
word (eam) ←(eam) or (A)
word (A) ←(AH) xor (A)
word (A) ←(A) xor imm16
word (A) ←(A) xor (ear)
word (A) ←(A) xor (eam)
word (ear) ←(ear) xor (A)
word (eam) ←(eam) xor (A)
word (A) ←not (A)
word (ear) ←not (ear)
word (eam) ←not (eam)
long (A) ←(A) and (ear)
long (A) ←(A) and (eam)
long (A) ←(A) or (ear)
long (A) ←(A) or (eam)
long (A) ←(A) xor (ear)
long (A) ←(A) xor (eam)
LH AH
-
FUJITSU MICROELECTRONICS LIMITED
-
I
S
T
N
Z
V
C RMW
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
*
*
*
*
*
*
*
*
-
327
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-9 Sign Inversion Instructions (Byte, Word) : 6 instructions
Mnemonic
NEG
NEG
NEG
NEGW
NEGW
NEGW
328
#
A
ear
eam
A
ear
eam
1
2
2+
1
2
2+
1
1
3
1
1
3
B
Operation
0
0
0
0
0
2
byte (A) ←0 - (A)
byte (ear) ←0 - (ear)
byte (eam) ←0 - (eam)
word (A) ←0 - (A)
word (ear) ←0 - (ear)
word (eam) ←0 - (eam)
LH AH
I
S
T
N
Z
V
C RMW
X
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
FUJITSU MICROELECTRONICS LIMITED
-
*
*
CM44-00203-3E
2
F MC-16FX Family
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
Table B-10 Shift/Normalization Instructions (Byte, Word, Long Word) : 19 instructions
Mnemonic
#
B
RORC
RORC
RORC
ROLC
ROLC
ROLC
ASR
LSR
LSL
ASRW
LSRW/SHRW
LSLW/SHLW
ASRW
LSRW
LSLW
ASRL
LSRL
LSLL
A
ear
eam
A
ear
eam
A, R0
A, R0
A, R0
A
A
A
A, R0
A, R0
A, R0
A, R0
A, R0
A, R0
2
2
2+
2
2
2+
2
2
2
1
1
1
2
2
2
2
2
2
1
1
3
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NRML
A, R0
2
1
0
CM44-00203-3E
Operation
byte (A) ←Right rotation of (A) with carry
byte (ear) ←Right rotation of (ear) with carry
byte (eam) ←Right rotation of (eam) with carry
byte (A) ←Left rotation of (A) with carry
byte (ear) ←Right rotation of (ear) with carry
byte (eam) ←Right rotation of (eam) with carry
byte (A) ←Arithmetic right barrel shift of (A) , (R0) bits
byte (A) ←Logical right barrel shift of (A) , (R0) bits
byte (A) ←Logical left barrel shift of (A) , (R0) bits
word (A) ←Arithmetic right shift of (A) , 1 bit
word (A) ←Logical right shift of (A) , 1 bits
word (A) ←Logical left shift of (A) , 1 bits
word (A) ←Arithmetic right barrel shift of (A) , (R0) bits
word (A) ←Logical right barrel shift of (A) , (R0) bits
word (A) ←Logical left barrel shift of (A) , (R0) bits
long (A) ←Arithmetic right barrel shift of (A) , (R0) bits
long (A) ←Logical right barrel shift of (A) , (R0) bits
long (A) ←Logical left barrel shift of (A) , (R0) bits
long (A) ←Shift left (A) until the MSB is "1"
byte (R0) ←Shift count (the first "1" bit position)
FUJITSU MICROELECTRONICS LIMITED
LH AH I
S
T
N
Z
V C RMW
-
-
-
-
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
-
*
-
-
-
329
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-11 Branch Instructions 1 : 31 instructions
Mnemonic
#
B
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
BP
BV
BNV
BT
BNT
BLT
BGE
BLE
BGT
BLS
BHI
BRA
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
rel
@A
addr16
@ear
@eam
@ear
@eam
addr24
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
3
2
2+
2
2+
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
3
5
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
CALL
@ear
2
3
1
CALL
@eam
2+
5
1+1*a
CALL
addr16
3
3
1
CALLV
#vct4
1
5
1
CALLP
@ear
2
5
2
CALLP
@eam
2+
7
2+1*b
CALLP
addr24
4
4
2
Operation
Branch on (Z) = 1
Branch on (Z) = 0
Branch on (C) = 1
Branch on (C) = 0
Branch on (N) = 1
Branch on (N) = 0
Branch on (V) = 1
Branch on (V) = 0
Branch on (T) = 1
Branch on (T) = 0
Branch on (V) xor (N) = 1
Branch on (V) xor (N) = 0
Branch on ((V) xor (N)) or (Z) = 1
Branch on ((V) xor (N)) or (Z) = 0
Branch on (C) or (Z) = 1
Branch on (C) or (Z) = 0
Branch always (Unconditional branch)
word (PC) ←(A)
word (PC) ←addr16
word (PC) ←(ear)
word (PC) ←(eam)
word (PC) ←(ear), (PCB) ←(ear+2)
word (PC) ←(eam), (PCB) ←(eam+2)
word (PC) ←ad24 0-15, (PCB) ←ad24 16-23
word (SP) ←(SP)-2, ((SP)) ←(PC)+2
word (PC) ←(ear)
word (SP) ←(SP)-2, ((SP)) ←(PC)+ 2+
word (PC) ←(eam)
word (SP) ←(SP)-2, ((SP)) ←(PC)+3
word (PC) ←addr16
word (SP) ←(SP)-2, ((SP)) ←(PC)+1
word (PC) ←(vecter_address)
word (SP) ←(SP)-2, ((SP)) ←(PCB)
word (SP) ←(SP)-2, ((SP)) ←(PC)+2
word (PC) ←(ear), (PCB) ←(ear+2)
word (SP) ←(SP)-2, ((SP)) ←(PCB)
word (SP) ←(SP)-2, ((SP)) ←(PC)+ 2+
word (PC) ←(eam), (PCB) ←(eam+2)
word (SP) ←(SP)-2, ((SP)) ←(PCB)
word (SP) ←(SP)-2, ((SP)) ←(PC)+4
word (PC) ←ad24 0-15, (PCB) ←ad24 16-23
LH AH I
S
T
N
Z
V
C RMW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
*a : compensation value: +1 for odd stack, +1 for odd operand address
*b : compensation value +2 for odd stack, +1 for odd operand address.
330
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-12 Branch Instructions 2 : 19 instructions
Mnemonic
CBNE
CWBNE
CBNE
CBNE
CWBNE
CWBNE
DBNZ
DBNZ
DWBNZ
DWBNZ
INT
INT
INTP
INT9
INTE
#
A, #imm8, rel
A, #imm16, rel
ear, #imm8, rel
eam, #imm8, rel
ear, #imm16, rel
eam, #imm16, rel
ear, rel
eam, rel
ear, rel
eam, rel
#vct8
addr16
addr24
RETI
LINK
#imm8
B
3
4
4
4+
5
5+
3
3+
3
3+
2
3
4
1
1
5
5
4
5
5
6
5
6
5
6
11
8
8
11
12
0
0
0
0
0
1
0
0
0
2
6
6
6
6
6
1
22 / 6*1
1
2
2
1
UNLINK
1
1
1
RET
1
4
1
RETP
1
5
1
Operation
LH AH I
S T N Z V C RMW
Branch on byte (A) not equal to imm8
Branch on word (A) not equal to imm16
Branch on byte (ear) not equal to imm8
Branch on byte (eam) not equal to imm8
Branch on word (ear) not equal to imm16
Branch on word (eam) not equal to imm16
byte (ear) ←(ear) - 1, Branch on (ear) not equal to 0
byte (eam) ←(eam) - 1, Branch on (eam) not equal to 0
word (ear) ←(ear) - 1, Branch on (ear) not equal to 0
word (eam) ←(eam) - 1, Branch on (eam) not equal to 0
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Software interrupt for break point (reserved for emulator)
-
-
R
R
R
R
R
S
S
S
S
S
-
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
-
*
*
-
Return from interrupt
-
-
*
*
*
*
*
*
*
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
word (SP) ←(SP) - 2, ((SP)) ←(RW3),
word (RW3) ←(SP), (SP) ←(SP) - imm8
word (SP) ←(RW3), (RW3) ←((SP)),
word (SP) ←(SP) + 2
word (PC) ←((SP)), (SP) ←(SP) + 2
word (PC) ←((SP)), (SP) ←(SP) + 2,
byte (PCB) ←((SP)), (SP) ←(SP) + 2
*1 : 6 cycles in case of RP stable, 22 cycles in other case.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
331
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-13 Other Control Instructions (Byte, Word, Long Word) : 28 instructions
Mnemonic
#
B
Operation
LH AH I
S
T
N
Z
V C RMW
-
-
-
-
-
A
AH
PS
1
1
1
1
1
1
1
1
1
word (SP) ←(SP) - 2, ((SP)) ←(A)
word (SP) ←(SP) - 2, ((SP)) ←(AH)
word (SP) ←(SP) - 2, ((SP)) ←(PS)
PUSHW
rlst
2
-
-
-
-
-
-
-
-
-
1
1
N*a
1
1
-
A
AH
N*1
1
1
multi word (SP) ←(SP) - 2n, ((SP)) ←(rlst)
POPW
POPW
word (A) ←((SP)), (SP) ←(SP) + 2
word (AH) ←((SP)), (SP) ←(SP) + 2
-
*
-
-
-
-
-
-
-
-
-
POPW
PS
1
18 / 4*2
1
POPW
rlst
2
JCTX
AND
OR
MOV
MOV
MOVEA
MOVEA
MOVEA
MOVEA
ADDSP
ADDSP
MOV
MOV
NOP
ADB
DTB
PCB
SPB
NCC
CMR
@A
CCR, #imm8
CCR, #imm8
RP, #imm8
ILM, #imm8
RWi, ear
RWi, eam
A, ear
A, eam
#imm8
#imm16
A, brg1
brg2, A
1
2
2
2
2
2
2+
2
2+
2
3
2
2
1
1
1
1
1
1
1
N*1
22 / 6*3
1
1
19 / 4*2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N*a
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PUSHW
PUSHW
PUSHW
-
-
-
-
-
word (PS) ←((SP)), (SP) ←(SP) + 2
-
-
*
*
*
*
*
*
*
-
multi word (rlst) ←((SP)), (SP) ←(SP) + 2n
-
-
-
-
-
-
-
-
-
-
Context switch
byte (CCR) ←(CCR) and imm8
byte (CCR) ←(CCR) or imm8
byte (RP) ←imm8
byte (ILM) ←imm8
word (RWi) ←ear
word (RWi) ←eam
word (A) ←ear
word (A) ←eam
word (SP) ←(SP) + ext(imm8)
word (SP) ←(SP) + imm16
byte (A) ←(brg1)
byte (brg2) ←(A)
No operation
Prefix code for AD space access
Prefix code for DT space access
Prefix code for PC space access
Prefix code for SP space access
Prefix code for flags no change
Prefix code for common register bank
Z
-
*
*
*
-
*
*
*
-
*
*
*
-
*
*
*
-
*
*
*
*
*
-
*
*
*
*
*
-
*
*
*
-
*
*
*
-
-
*1 : N depends on number of registers to be saved/restored, minimum 1 cycle
*2 : 4 cycles in case of RP stable, 18 cycles in other case
*3 : 6 cycles in case of RP stable, 22 cycles in other case
*a : N depends on number of registers to be saved
332
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-14 Bit Operation Instructions : 21 instructions
S T N Z
V C RMW
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
SETB
SETB
SETB
CLRB
CLRB
CLRB
BBC
BBC
BBC
BBS
BBS
BBS
SBBS
Mnemonic
A, dir:bp
A, addr16:bp
A, io:bp
dir:bp, A
addr16:bp, A
io:bp, A
dir:bp
addr16:bp
io:bp
dir:bp
addr16:bp
io:bp
dir:bp, rel
addr16:bp, rel
io:bp, rel
dir:bp, rel
addr16:bp, rel
io:bp, rel
addr16:bp, rel
#
3
4
3
3
4
3
3
4
3
3
4
3
4
5
4
4
5
4
5
1
1
1
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
byte (A) ←(dir:bp) b
byte (A) ←(addr16:bp) b
byte (A) ←(io:bp) b
bit (dir:bp) b ←(A)
bit (addr16:bp) b ←(A)
bit (io:bp) b ←(A)
bit (dir:bp) b ←1
bit (addr16:bp) b ←1
bit (io:bp) b ←1
bit (dir:bp) b ←0
bit (addr16:bp) b ←0
bit (io:bp) b ←0
Branch on (dir:bp) b = 0
Branch on (addr16:bp) b = 0
Branch on (io:bp) b = 0
Branch on (dir:bp) b = 1
Branch on (addr16:bp) b = 1
Branch on (io:bp) b = 1
Branch on (addr16:bp) b = 1, bit (addr16:bp) b ←1
Operation
LH AH I
Z
Z
Z
-
*
*
*
-
-
-
-
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
*
*
*
*
*
*
*
*
*
*
WBTS
io:bp
3
undefined*1
0
Wait until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
WBTC
io:bp
3
undefined*2
0
Wait until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
*1 : 4 cycles if the bit is set already. In other case, the cycle is undefined.
*2 : 4 cycles if the bit is cleared already. In other case, the cycle is undefined.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
333
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
F2MC-16FX Family
Table B-15 Accumulator Instructions (Byte, Word) : 6 instructions
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
334
#
1
1
1
1
1
1
B
1
1
1
1
1
1
0
0
0
0
0
0
Operation
byte (A) 0-7 ←→(A) 8-15
word (AH) ←→(AL)
Byte sign extension
Word sign extension
Byte zero extension
Word zero extension
LH AH I
S
T
N
Z
V
C
RMW
X
Z
-
-
-
*
*
R
R
*
*
*
*
-
-
-
FUJITSU MICROELECTRONICS LIMITED
*
X
Z
-
CM44-00203-3E
APPENDIX
APPENDIX B Instruction Lists (351 Instructions)
2
F MC-16FX Family
Table B-16 String Instructions : 10 instructions
Mnemonic
#
S
T
N
Z
V C
1
byte transfer @AH+ [email protected]+, (RW0) times
-
-
-
-
-
-
-
-
-
-
2
RW0*2
2*RW0
0
byte transfer @AH- ←@AL-, (RW0) times
-
-
-
-
-
-
-
-
-
-
brg3
2
2+2*N*3
0
byte search @AH+ = AL, (RW0) times or till match
-
-
-
-
-
*
*
*
*
-
SCEQD
brg3
2
2+2*N*3
0
byte search @AH- = AL, (RW0) times or till match
-
-
-
-
-
*
*
*
*
-
FILS/FILSI
brg3
2
1
byte fill @AH+ ←AL, (RW0) times
-
-
-
-
-
*
*
-
-
-
1
word transfer @AH+ [email protected]+, (RW0) times
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
*
*
*
*
-
MOVS/MOVSI
brg3, brg3
2
MOVSD
brg3, brg3
SCEQ/SCEQI
B
Operation
LH AH I
RMW
MOVSW/MOVSWI brg3, brg3
2
RW0/2*4
2*RW0
MOVSWD
brg3, brg3
2
2*RW0
SCWEQ/SCWEQI
brg3
2
2+2*N*3
N*b
word search @AH+ = AL, (RW0) times or till match
SCWEQD
brg3
2
-
-
-
-
*
*
*
*
-
2
N*b
1
-
brg3
2+2*N*3
RW0
word search @AH- = AL, (RW0) times or till match
FILSW/FILSWI
word fill @AH+ ←AL, (RW0) times
-
-
-
-
-
*
*
-
-
-
(1+1)*RW0*a word transfer @AH- ←@AL-, (RW0) times
*1 : All String operations need 1 cycle if RW0=0.
*2 : 2*RW0 cycles if overlapping ranges, optimization can not be done.
*3 : 1 cycle if RW0=0, 3 cycles if RW0=1, N is number of items compared till match occurs.
*4 : The number of cycle is round up in case of odd number of bytes.
*a : Correction is 2*RW0 if both src and dest address is odd, 1*RW0 if only src or dest is odd.
*b : N is number of items compared till match occurs.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
335
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
APPENDIX C Instruction Maps
This appendix describes F2MC-16FX CPU instruction maps.
C.1 Structure of the Instruction Map
C.2 Basic Page Map
C.3 Bit Operation Instruction Map
C.4 Character String Operation Instruction Map
C.5 2-byte Instruction Map
C.6 ea-type Instruction Map
C.7 MOVEA RWi, ea Instruction Map
C.8 MOV Ri, ea Instruction Map
C.9 MOVW RWi, ea Instruction Map
C.10 MOV ea, Ri Instruction Map
C.11 MOVW ea, RWi Instruction Map
C.12 XCH Ri, ea Instruction Map
C.13 XCHW RWi, ea Instruction Map
336
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
APPENDIX
APPENDIX C Instruction Maps
2
F MC-16FX Family
C.1 Structure of the Instruction Map
The instruction code of the F2MC-16FX CPU consists of one- and two-byte
instructions. The instruction map consists of more than one page that can be
used for one- and two- byte instructions.
■ Structure of the Instruction Map
Figure C.1-1 shows the structure of the instruction map.
Figure C.1-1 Structure of the F2MC-16FX CPU Instruction Map
Basic page map
Bit operation
instruction
Character string
operation
instruction
2-byte
instructions
: First byte
ea-type
instruction × 9
: Second byte
The instruction code is described on the basic page map for one-byte instructions (such as the
NOP instruction). For two-byte instructions (such as the MOVS instruction), see the basic page
map to find the name of the map that describes the second byte of the instruction code to be
referenced next.
Figure C.1-2 shows the relationship between actual instruction codes and instruction maps.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
337
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Figure C.1-2 Relationship Between Actual Instruction Codes and Instruction Maps
May not exist for
some instruction.
The length varies
depending on
instructions.
Instruction
code
First byte
Second byte
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: Extended page map is a generic name for bit operation instruction, character string
operation instruction, 2-byte instruction, and ea-type instruction. More than one extended
page map exists for each type of instruction.
338
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
2
F MC-16FX Family
C.2 Basic Page Map
APPENDIX
APPENDIX C Instruction Maps
Table C.2-1 shows the basic page map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
339
340
JCTX
@A
NEG
LINK
SPB
ADB
DTB
PCB
FUJITSU MICROELECTRONICS LIMITED
SWAPW
ADDSP
#imm16
ASRW
+E A
LSRW
+F A
+D
EXTW
LSLW
+C A
ZEXTW
CMPL
A,
#imm32
NEGW
+B A
INTE
MOV
ILM,
#imm8
MULUW
A
XORW
A
ORW
A
ANDW
A
CMPW
A
CBNE
A,
#imm8, rel
SUBW
A
ADDW
A
ADDL
A,
#imm32
SUBL
A,
#imm32
MULU
A
DIVU
A
OR
CCR,
#imm8
AND
CCR,
#imm8
CMP
A
ADDC
A
SUB
A,
dir
ADD
A,
dir
20
ADDSP
#imm8
SWAP
ZEXT
MOV
+A RP,
#imm8
+9
UNLINK
+8 #imm8
+7
+6
+5
+4
+3 A
EXT
SUBDC
A
NCC
CMR
10
ADDDC
INT9
NOP
+2 A
+1
+0
00
MOVW
dir,
A
MOVW
A,
dir
MOVW
SP,
A
MOVW
A,
SP
MOVX
A,
dir
MOV
dir,
#imm8
MOVX
A,
#imm8
MOV
A,
#imm8
MOV
dir,
A
MOV
A,
dir
40
NOTW
A
XORW
A,
#imm16
ORW
A,
#imm16
ANDW
A,
#imm16
CMPW
A,
#imm16
PUSHW
rlst
PUSHW
PS
PUSHW
AH
PUSHW
A
MOVL
A,
#imm32
CWBNE
MOVW
A,
A,
#imm16, rel #imm16
SUBW
A,
#imm16
ADDW
A,
#imm16
NOT
A
XOR
A,
#imm8
OR
A,
#imm8
AND
A,
#imm8
CMP
A,
#imm8
SUBC
A
SUB
A,
#imm8
ADD
A,
#imm8
30
POPW
rlst
POPW
PS
POPW
AH
POPW
A
MOVW
addr16,
A
MOVW
A,
addr16
MOVW
io,
A
MOVW
A,
io
MOVX
A,
addr16
MOVW
io,
#imm16
MOVX
A,
io
MOV
io,
#imm8
MOV
addr16,
A
MOV
A,
addr16
MOV
io,
A
MOV
A,
io
50
ea
MOVW
RW2,
A
MOVW
RW3,
A
MOVW
RW4,
A
MOVW
A,
RW2
MOVW
A,
RW3
MOVW
A,
RW4
instruction
instruction
instruction
XCHW RWi, ea
instruction
instruction
2-byte
instruction
XCH Ri, ea
String operation
instruction
MOVW ea, RWi
MOV ea, Ri
instruction
MOVW RWi, ea
instruction
MOV Ri, ea
instruction
MOVW
RW5,
A
MOVW
RW6,
A
MOVW
RW7,
A
MOVW
A,
RW5
MOVW
A,
RW6
MOVW
A,
RW7
A,
RW1
MOVW
RW1,
A
MOVEA RWi, ea MOVW
MOV
R7,
A
MOV
R6,
A
MOV
R5,
A
MOV
R4,
A
MOV
R3,
A
MOV
R2,
A
MOV
R1,
A
MOV
R0,
A
90
MOVW
RW0,
A
MOV
A,
R7
MOV
A,
R6
MOV
A,
R5
MOV
A,
R4
MOV
A,
R3
MOV
A,
R2
MOV
A,
R1
MOV
A,
R0
80
MOVW
A,
RW0
instruction 9
ea
instruction 8
ea
instruction 7
ea
instruction 6
ea
instruction 5
ea
instruction 4
ea
instruction 3
ea
instruction 2
ea
instruction 1
70
Bit operation
RETI
INTP
addr24
INT
addr16
INT
#vct8
RET
RETP
CALLP
addr24
CALL
addr16
JMPP
addr24
JMP
addr16
JMP
@A
BRA
rel
60
MOVW
RW7,
#imm16
MOVW
RW6,
#imm16
MOVW
RW5,
#imm16
MOVW
RW4,
#imm16
MOVW
RW3,
#imm16
MOVW
RW2,
#imm16
MOVW
RW1,
#imm16
MOVW
RW0,
#imm16
MOV
R7,
#imm8
MOV
R6,
#imm8
MOV
R5,
#imm8
MOV
R4,
#imm8
MOV
R3,
#imm8
MOV
R2,
#imm8
MOV
R1,
#imm8
MOV
R0,
#imm8
A0
D0
MOVN
A,
#imm4
MOVN
A,
#imm4
A
@RW7+disp8
#imm4
@RW7+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW6+disp8
MOVW
@RW6+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW5+disp8
MOVW
@RW5+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW4+disp8
MOVW
@RW4+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW3+disp8
MOVW
@RW3+disp8, A,
MOVW
A,
MOVN
#imm4
A
@RW2+disp8
MOVW
@RW2+disp8, A,
MOVW
A,
MOVN
#imm4
A
MOVW
@RW1+disp8, A,
@RW1+disp8
MOVN
#imm4
MOVW
A,
MOVW
A
@RW0+disp8
MOVN
@RW0+disp8, A,
MOVW
MOVN
A,
@RW7+disp8 #imm4
MOVX
A
MOVN
A,
@RW6+disp8 #imm4
MOVX
A
@RW5+disp8
MOVX
A
MOVN
A,
@RW4+disp8 #imm4
MOVX
A
MOVN
A,
@RW3+disp8 #imm4
MOVX
A
MOVN
A,
@RW2+disp8 #imm4
MOVX
A
@RW1+disp8
MOVX
A
MOVN
A,
@RW0+disp8 #imm4
MOVX
A
C0
MOVW
A,
MOVX
A,
R7
MOVX
A,
R6
MOVX
A,
R5
MOVX
A,
R4
MOVX
A,
R3
MOVX
A,
R2
MOVX
A,
R1
MOVX
A,
R0
B0
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
CALLV
#vct4
E0
BHI
rel
BLS
rel
BGT
rel
BLE
rel
BGE
rel
BLT
rel
BNT
rel
BT
rel
BNV
rel
BV
rel
BP
rel
BN
rel
BNC/BHS
rel
BC/BLO
rel
BNZ/BNE
rel
BZ/BEQ
rel
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.2-1 Basic Page Map
CM44-00203-3E
2
F MC-16FX Family
C.3 Bit Operation Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.3-1 shows the bit operation instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
341
342
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
ip:bp,
A
MOVB
dir:bp,
A
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
MOVB
FUJITSU MICROELECTRONICS LIMITED
MOVB
MOVB
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
A,
addr16:bp
MOVB
MOVB
CM44-00203-3E
dir:bp
+F A,
dir:bp
+E A,
dir:bp
+D A,
MOVB
dir:bp
+C A,
dir:bp
+B A,
dir:bp
+A A,
dir:bp
+9 A,
dir:bp
+8 A,
io:bp
+7 A,
io:bp
+6 A,
io:bp
+5 A,
io:bp
+4 A,
io:bp
+3 A,
io:bp
+2 A,
io:bp
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
dir:bp,
A
MOVB
ip:bp,
A
+1 A,
io:bp
+0 A,
MOVB
20
MOVB
ip:bp,
A
10
MOVB
00
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
MOVB
addr16:bp
30
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
dir:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
CLRB
io:bp
40
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
CLRB
addr16:bp
50
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
dir:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
SETB
io:bp
60
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
SETB
addr16:bp
70
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
dir:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
BBC
ip:bp,
rel
80
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
BBS
io:bp,
rel
A0
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
BBC
BBS
addr16:bp, dir:bp,
rel
rel
90
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
BBS
addr16:bp,
rel
B0
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
WBTS
io:bp
C0
D0
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
WBTC
io:bp
E0
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
SBBS
addr16:bp,
rel
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.3-1 Bit Operation Instruction Map (First Byte = 6CH)
2
APPENDIX
APPENDIX C Instruction Maps
F MC-16FX Family
C.4 Character String Operation Instruction Map
Table C.4-1 shows the character string operation instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
343
344
MOVSD
PCB,
PCB
MOVSD
PCB,
DTB
MOVSD
PCB,
ADB
MOVSD
PCB,
SPB
MOVSD
DTB,
PCB
MOVSD
DTB,
DTB
MOVSD
DTB,
ADB
MOVSD
DTB,
SPB
MOVSD
ADB,
PCB
MOVSD
ADB,
DTB
MOVSD
ADB,
ADB
MOVSD
ADB,
SPB
MOVSD
SPB,
PCB
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
MOVSI
FUJITSU MICROELECTRONICS LIMITED
MOVSI
MOVSI
MOVSD
SPB,
DTB
MOVSD
SPB,
ADB
MOVSD
SPB,
SPB
MOVSI
MOVSI
CM44-00203-3E
SPB
+F SPB,
ADB
+E SPB,
DTB
+D SPB,
MOVSI
PCB
+C SPB,
SPB
+B ADB,
ADB
+A ADB,
DTB
+9 ADB,
PCB
+8 ADB,
SPB
+7 DTB,
ADB
+6 DTB,
DTB
+5 DTB,
PCB
+4 DTB,
SPB
+3 PCB,
ADB
+2 PCB,
DTB
+1 PCB,
PCB
+0 PCB,
10
00
MOVSWI
SPB,
SPB
MOVSWI
SPB,
ADB
MOVSWI
SPB,
DTB
MOVSWI
SPB,
PCB
MOVSWI
ADB,
SPB
MOVSWI
ADB,
ADB
MOVSWI
ADB,
DTB
MOVSWI
ADB,
PCB
MOVSWI
DTB,
SPB
MOVSWI
DTB,
ADB
MOVSWI
DTB,
DTB
MOVSWI
DTB,
PCB
MOVSWI
PCB,
SPB
MOVSWI
PCB,
ADB
MOVSWI
PCB,
DTB
MOVSWI
PCB,
PCB
20
MOVSWD
SPB,
SPB
MOVSWD
SPB,
ADB
MOVSWD
SPB,
DTB
MOVSWD
SPB,
PCB
MOVSWD
ADB,
SPB
MOVSWD
ADB,
ADB
MOVSWD
ADB,
DTB
MOVSWD
ADB,
PCB
MOVSWD
DTB,
SPB
MOVSWD
DTB,
ADB
MOVSWD
DTB,
DTB
MOVSWD
DTB,
PCB
MOVSWD
PCB,
SPB
MOVSWD
PCB,
ADB
MOVSWD
PCB,
DTB
MOVSWD
PCB,
PCB
30
40
50
60
70
SCEQI
SPB
SCEQI
ADB
SCEQI
DTB
SCEQI
PCB
80
SCEQD
SPB
SCEQD
ADB
SCEQD
DTB
SCEQD
PCB
90
SCWEQI
SPB
SCWEQI
ADB
SCWEQI
DTB
SCWEQI
PCB
A0
SCWEQD
SPB
SCWEQD
ADB
SCWEQD
DTB
SCWEQD
PCB
B0
FILSI
SPB
FILSI
ADB
FILSI
DTB
FILSI
PCB
C0
D0
FILSWI
SPB
FILSWI
ADB
FILSWI
DTB
FILSWI
PCB
E0
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.4-1 Character String Operation Instruction Map (First Byte = 6EH)
2
F MC-16FX Family
C.5 2-byte Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.5-1 shows the 2-byte instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
345
346
MOV
SSB,
A
MOV
USB,
A
MOV
DPR,
A
MOV
@AL,
AH
MOVX
A,
@A
RORC
A
MOV
MOV
MOV
MOV
MOV
ROLC
FUJITSU MICROELECTRONICS LIMITED
LSLW
MOVW
@AL,
AH
ASRL
A,
R0
LSRL
A,
R0
ASRW
LSRW
CM44-00203-3E
R0
+F A,
R0
+E A,
@A
+D A,
MOVW
R0
+C A,
+B
+A
+9
+8
+7 A
PCB
+6 A,
@A
+5 A,
DPR
+4 A,
USB
+3 A,
SSB
+2 A,
ADB
LSLL
A,
R0
MOV
ADB,
A
MOV
+1 A,
DTB
+0 A,
MOV
DTB,
A
10
MOV
00
MOV
30
MOV
40
MOV
MOV
MOV
MOV
MOV
MOV
LSR
A,
R0
ASR
A,
R0
NRML
A,
R0
LSL
A,
R0
MOVW
MOVW
MOVW
MOVW
@RL3+disp8, A,
@RL3+disp8
A
MOVW
@RL2+disp8, A,
@RL2+disp8
A
MOVW
@RL1+disp8, A,
@RL1+disp8
A
MOVW
@RL0+disp8, A,
@RL0+disp8
A
MOVW
@RL3+disp8, A,
@RL3+disp8 A
@RL3+disp8
MOVX
A,
@RL2+disp8, A,
A,
@RL2+disp8 A
@RL2+disp8
MOVX
@RL1+disp8, A,
@RL1+disp8 A
@RL1+disp8
MOVX
A,
@RL0+disp8, A,
A,
@RL0+disp8 A
@RL0+disp8
MOVX
20
50
60
DIV
A
MULW
A
MUL
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.5-1 2-byte Instruction Map (First Byte = 6FH)
2
F MC-16FX Family
C.6 ea-type Instruction Map
APPENDIX
APPENDIX C Instruction Maps
ea-type instruction maps (first byte = 70H to first byte = 78H) are shown in the
following nine tables:
• Table C.6-1 for ea-type instruction (1) (first byte = 70H)
• Table C.6-2 for ea-type instruction (2) (first byte = 71H)
• Table C.6-3 for ea-type instruction (3) (first byte = 72H)
• Table C.6-4 for ea-type instruction (4) (first byte = 73H)
• Table C.6-5 for ea-type instruction (5) (first byte = 74H)
• Table C.6-6 for ea-type instruction (6) (first byte = 75H)
• Table C.6-7 for ea-type instruction (7) (first byte = 76H)
• Table C.6-8 for ea-type instruction (8) (first byte = 77H)
• Table C.6-9 for ea-type instruction (9) (first byte = 78H)
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
347
348
RL0
20
FUJITSU MICROELECTRONICS LIMITED
SUBL
A,
@RW1+disp8 RL0
ADDL
A,
SUBL
A,
@RW2+disp8 RL1
ADDL
A,
SUBL
A,
@RW3+disp8 RL1
ADDL
A,
SUBL
A,
@RW4+disp8 RL2
ADDL
A,
SUBL
A,
@RW5+disp8 RL2
ADDL
A,
SUBL
A,
@RW6+disp8 RL3
ADDL
A,
SUBL
A,
@RW7+disp8 RL3
ADDL
A,
SUBL
A,
@RW0+disp16 @RW0
ADDL
A,
SUBL
A,
@RW1+disp16 @RW1
ADDL
A,
SUBL
A,
@RW2+disp16 @RW2
ADDL
A,
SUBL
A,
@RW3+disp16 @RW3
ADDL
A,
ADDL
+2 A,
RL1
ADDL
+3 A,
RL1
ADDL
+4 A,
RL2
ADDL
+5 A,
RL2
ADDL
+6 A,
RL3
ADDL
+7 A,
RL3
ADDL
+8 A,
@RW0
ADDL
+9 A,
@RW1
ADDL
+A A,
@RW2
ADDL
+B A,
@RW3
ADDL
+C A,
@RW0+
SUBL
A,
@RW1+RW7 @RW1+
ADDL
A,
SUBL
A,
@PC+disp16 @RW2+
ADDL
A,
addr16
ADDL
+E A,
@RW2+
ADDL
+F A,
@RW3+
SUBL
A,
@RW3+
ADDL
A,
ADDL
+D A,
@RW1+
SUBL
A,
@RW0+RW7 @RW0+
ADDL
A,
ADDL
+1 A,
RL0
SUBL
A,
ADDL
A,
+0 A,
@RW0+disp8 RL0
10
ADDL
00
CWBNE
RW0,
40
CWBNE
RW1,
CWBNE
RW2,
CWBNE
RW3,
CWBNE
RW4,
CWBNE
RW5,
CWBNE
RW6,
CWBNE
RW7,
CWBNE
@RW0,
CWBNE
@RW1,
CWBNE
@RW2,
CWBNE
@RW3,
CWBNE
@RW0+,
CWBNE
@RW1+,
CWBNE
@RW2+,
SUBL
A,
addr16
CWBNE
addr16,
#imm16, rel
#imm16, rel
CMPL
A,
@RW3+
CMPL
@PC+disp16, A,
#imm16, rel
@RW2+
CWBNE
CMPL
@RW1+RW7, A,
#imm16, rel
@RW1+
CWBNE
CMPL
@RW0+RW7, A,
#imm16, rel
@RW0+
CWBNE
CMPL
@RW3+disp16, A,
#imm16, rel
@RW3
CWBNE
CMPL
@RW2+disp16, A,
#imm16, rel
@RW2
CWBNE
CMPL
@RW1+disp16, A,
#imm16, rel
@RW1
CWBNE
CMPL
@RW0+disp16, A,
#imm16, rel
@RW0
CWBNE
CMPL
@RW7+disp8, A,
#imm16, rel
RL3
CWBNE
CMPL
@RW6+disp8, A,
#imm16, rel
RL3
CWBNE
CMPL
@RW5+disp8, A,
#imm16, rel
RL2
CWBNE
CMPL
@RW4+disp8, A,
#imm16, rel
RL2
CWBNE
CMPL
@RW3+disp8, A,
#imm16, rel
RL1
CWBNE
CMPL
@RW2+disp8, A,
#imm16, rel
RL1
CWBNE
CMPL
@RW1+disp8, A,
#imm16, rel
RL0
CWBNE
60
CMPL
@RW0+disp8, A,
#imm16, rel
RL0
CWBNE
50
CWBNE
@RW3+,
@PC+disp16 #imm16, rel
SUBL
A,
@RW1+RW7 #imm16, rel
SUBL
A,
@RW0+RW7 #imm16, rel
SUBL
A,
@RW3+disp16 #imm16, rel
SUBL
A,
@RW2+disp16 #imm16, rel
SUBL
A,
@RW1+disp16 #imm16, rel
SUBL
A,
@RW0+disp16 #imm16, rel
SUBL
A,
@RW7+disp8 #imm16, rel
SUBL
A,
@RW6+disp8 #imm16, rel
SUBL
A,
@RW5+disp8 #imm16, rel
SUBL
A,
@RW4+disp8 #imm16, rel
SUBL
A,
@RW3+disp8 #imm16, rel
SUBL
A,
@RW2+disp8 #imm16, rel
SUBL
A,
@RW1+disp8 #imm16, rel
SUBL
A,
@RW0+disp8 #imm16, rel
SUBL
A,
30
CMPL
A,
addr16
ANDL
A,
@RW3+
ANDL
A,
@PC+disp16 @RW2+
CMPL
A,
ANDL
A,
@RW1+RW7 @RW1+
CMPL
A,
ANDL
A,
@RW0+RW7 @RW0+
CMPL
A,
ANDL
A,
@RW3+disp16 @RW3
CMPL
A,
ANDL
A,
@RW2+disp16 @RW2
CMPL
A,
ANDL
A,
@RW1+disp16 @RW1
CMPL
A,
ANDL
A,
@RW0+disp16 @RW0
CMPL
A,
ANDL
A,
@RW7+disp8 RL3
CMPL
A,
ANDL
A,
@RW6+disp8 RL3
CMPL
A,
ANDL
A,
@RW5+disp8 RL2
CMPL
A,
ANDL
A,
@RW4+disp8 RL2
CMPL
A,
ANDL
A,
@RW3+disp8 RL1
CMPL
A,
ANDL
A,
@RW2+disp8 RL1
CMPL
A,
ANDL
A,
@RW1+disp8 RL0
CMPL
A,
80
ANDL
A,
@RW0+disp8 RL0
CMPL
A,
70
ANDL
A,
addr16
ORL
A,
@RW3+
ORL
A,
@PC+disp16 @RW2+
ANDL
A,
ORL
A,
@RW1+RW7 @RW1+
ANDL
A,
ORL
A,
@RW0+RW7 @RW0+
ANDL
A,
ORL
A,
@RW3+disp16 @RW3
ANDL
A,
ORL
A,
@RW2+disp16 @RW2
ANDL
A,
ORL
A,
@RW1+disp16 @RW1
ANDL
A,
ORL
A,
@RW0+disp16 @RW0
ANDL
A,
ORL
A,
@RW7+disp8 RL3
ANDL
A,
ORL
A,
@RW6+disp8 RL3
ANDL
A,
ORL
A,
@RW5+disp8 RL2
ANDL
A,
ORL
A,
@RW4+disp8 RL2
ANDL
A,
ORL
A,
@RW3+disp8 RL1
ANDL
A,
ORL
A,
@RW2+disp8 RL1
ANDL
A,
ORL
A,
@RW1+disp8 RL0
ANDL
A,
A0
ORL
A,
@RW0+disp8 RL0
ANDL
A,
90
ORL
A,
addr16
XORL
A,
@RW3+
XORL
A,
@PC+disp16 @RW2+
ORL
A,
XORL
A,
@RW1+RW7 @RW1+
ORL
A,
XORL
A,
@RW0+RW7 @RW0+
ORL
A,
XORL
A,
@RW3+disp16 @RW3
ORL
A,
XORL
A,
@RW2+disp16 @RW2
ORL
A,
XORL
A,
@RW1+disp16 @RW1
ORL
A,
XORL
A,
@RW0+disp16 @RW0
ORL
A,
XORL
A,
@RW7+disp8 RL3
ORL
A,
XORL
A,
@RW6+disp8 RL3
ORL
A,
XORL
A,
@RW5+disp8 RL2
ORL
A,
XORL
A,
@RW4+disp8 RL2
ORL
A,
XORL
A,
@RW3+disp8 RL1
ORL
A,
XORL
A,
@RW2+disp8 RL1
ORL
A,
XORL
A,
@RW1+disp8 RL0
ORL
A,
C0
XORL
A,
@RW0+disp8 RL0
ORL
A,
B0
CBNE
R0,
E0
XORL
A,
addr16
CBNE
@RW3+,
#imm8, rel
CBNE
@RW2+,
@PC+disp16 #imm8, rel
XORL
A,
CBNE
@RW1+,
@RW1+RW7 #imm8, rel
XORL
A,
CBNE
@RW0+,
@RW0+RW7 #imm8, rel
XORL
A,
CBNE
@RW3,
@RW3+disp16 #imm8, rel
XORL
A,
CBNE
@RW2,
@RW2+disp16 #imm8, rel
XORL
A,
CBNE
@RW1,
@RW1+disp16 #imm8, rel
XORL
A,
CBNE
@RW0,
@RW0+disp16 #imm8, rel
XORL
A,
CBNE
R7,
@RW7+disp8 #imm8, rel
XORL
A,
CBNE
R6,
@RW6+disp8 #imm8, rel
XORL
A,
CBNE
R5,
@RW5+disp8 #imm8, rel
XORL
A,
CBNE
R4,
@RW4+disp8 #imm8, rel
XORL
A,
CBNE
R3,
@RW3+disp8 #imm8, rel
XORL
A,
CBNE
R2,
@RW2+disp8 #imm8, rel
XORL
A,
CBNE
R1,
@RW1+disp8 #imm8, rel
XORL
A,
@RW0+disp8 #imm8, rel
XORL
A,
D0
CBNE
addr16,
#imm8, rel
#imm8, rel
@PC+disp16,
CBNE
#imm8, rel
@RW1+RW7,
CBNE
#imm8, rel
@RW0+RW7,
CBNE
#imm8, rel
@RW3+disp16,
CBNE
#imm8, rel
@RW2+disp16,
CBNE
#imm8, rel
@RW1+disp16,
CBNE
#imm8, rel
@RW0+disp16,
CBNE
#imm8, rel
@RW7+disp8,
CBNE
#imm8, rel
@RW6+disp8,
CBNE
#imm8, rel
@RW5+disp8,
CBNE
#imm8, rel
@RW4+disp8,
CBNE
#imm8, rel
@RW3+disp8,
CBNE
#imm8, rel
@RW2+disp8,
CBNE
#imm8, rel
@RW1+disp8,
CBNE
#imm8, rel
@RW0+disp8,
CBNE
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.6-1 ea-byte Instruction (1) (First Byte = 70H)
CM44-00203-3E
CM44-00203-3E
CALLP
@@RW1+disp8 @RL0
JMPP
CALLP
@@RW2+disp8 @RL1
JMPP
JMPP
+2 @RL1
JMPP
+3 @RL1
CALLP
@@RW4+disp8 @RL2
JMPP
CALLP
@@RW5+disp8 @RL2
JMPP
CALLP
@@RW6+disp8 @RL3
JMPP
CALLP
@@RW7+disp8 @RL3
JMPP
CALLP
@@RW0+disp16 @@RW0
JMPP
CALLP
@@RW1+disp16 @@RW1
JMPP
CALLP
@@RW2+disp16 @@RW2
JMPP
JMPP
+5 @RL2
JMPP
+6 @RL3
JMPP
+7 @RL3
JMPP
+8 @@RW0
JMPP
+9 @@RW1
JMPP
+A @@RW2
JMPP
+B @@RW3
FUJITSU MICROELECTRONICS LIMITED
INCL
JMPP
JMPP
CALLP
CALLP
INCL
+E @@RW2+ @@PC+disp16 @@RW2+ @@PC+disp16 @RW2+
INCL
@RW3+
DECL
@RW1+RW7 @RW1+
CALLP
CALLP
@@RW3+ @addr16
INCL
JMPP
JMPP
CALLP
CALLP
INCL
+D @@RW1+ @@RW1+RW7 @@RW1+ @@RW1+RW7 @RW1+
JMPP
JMPP
+F @@RW3+ @addr16
DECL
@RW0+RW7 @RW0+
INCL
addr16
DECL
@RW3+
DECL
@PC+disp16 @RW2+
INCL
DECL
@RW3+disp16 @RW3
INCL
DECL
@RW2+disp16 @RW2
INCL
DECL
@RW1+disp16 @RW1
INCL
DECL
@RW0+disp16 @RW0
INCL
DECL
@RW7+disp8 RL3
INCL
DECL
@RW6+disp8 RL3
INCL
DECL
@RW5+disp8 RL2
INCL
DECL
@RW4+disp8 RL2
INCL
DECL
@RW3+disp8 RL1
INCL
DECL
@RW2+disp8 RL1
INCL
DECL
@RW1+disp8 RL0
INCL
60
DECL
@RW0+disp8 RL0
INCL
50
JMPP
JMPP
CALLP
CALLP
INCL
+C @@RW0+ @@RW0+RW7 @@RW0+ @@RW0+RW7 @RW0+
INCL
@@RW3+disp16 @RW3
CALLP
INCL
@@RW2+disp16 @RW2
CALLP
INCL
@@RW1+disp16 @RW1
CALLP
INCL
@@RW0+disp16 @RW0
CALLP
INCL
@@RW7+disp8 RL3
CALLP
INCL
@@RW6+disp8 RL3
CALLP
INCL
@@RW5+disp8 RL2
CALLP
INCL
@@RW4+disp8 RL2
CALLP
INCL
@@RW3+disp8 RL1
CALLP
INCL
@@RW2+disp8 RL1
CALLP
INCL
@@RW1+disp8 RL0
CALLP
40
INCL
@@RW0+disp8 RL0
CALLP
30
DECL
addr16
MOVL
A,
@RW3+
MOVL
@PC+disp16 A,
@RW2+
DECL
MOVL
@RW1+RW7 A,
@RW1+
DECL
MOVL
@RW0+RW7 A,
@RW0+
DECL
MOVL
@RW3+disp16 A,
@RW3
DECL
MOVL
@RW2+disp16 A,
@RW2
DECL
MOVL
@RW1+disp16 A,
@RW1
DECL
MOVL
@RW0+disp16 A,
@RW0
DECL
MOVL
@RW7+disp8 A,
RL3
DECL
MOVL
@RW6+disp8 A,
RL3
DECL
MOVL
@RW5+disp8 A,
RL2
DECL
MOVL
@RW4+disp8 A,
RL2
DECL
MOVL
@RW3+disp8 A,
RL1
DECL
MOVL
@RW2+disp8 A,
RL1
DECL
MOVL
RL0,
A
A0
MOVL
A,
addr16
MOVL
@RW3+,
A
MOVL
@RW2+,
@PC+disp16 A
MOVL
A,
MOVL
@RW1+,
@RW1+RW7 A
MOVL
A,
MOVL
@RW0+,
@RW0+RW7 A
MOVL
A,
MOVL
@RW3,
A,
@RW3+disp16 A
MOVL
MOVL
@RW2,
@RW2+disp16 A
MOVL
A,
MOVL
@RW1,
@RW1+disp16 A
MOVL
A,
MOVL
@RW0,
@RW0+disp16 A
MOVL
A,
MOVL
RL3,
@RW7+disp8 A
MOVL
A,
MOVL
RL3,
@RW6+disp8 A
MOVL
A,
MOVL
RL2,
@RW5+disp8 A
MOVL
A,
MOVL
RL2,
@RW4+disp8 A
MOVL
A,
MOVL
RL1,
@RW3+disp8 A
MOVL
A,
MOVL
RL1,
@RW2+disp8 A
MOVL
A,
MOVL
RL0,
@RW1+disp8 A
RL0
MOVL
@RW1+disp8 A,
RL0
DECL
MOVL
A,
MOVL
A,
90
@RW0+disp8
80
MOVL
@RW0+disp8 A,
DECL
70
MOV
MOV
R1,
#imm8
MOV
MOVEA
@RW3+disp8, A,
#imm8
RW3
MOV
MOVEA
@RW4+disp8, A,
#imm8
RW4
MOV
MOVEA
@RW5+disp8, A,
#imm8
RW5
MOV
MOVEA
@RW6+disp8, A,
#imm8
RW6
MOV
MOVEA
@RW7+disp8, A,
#imm8
RW7
MOV
MOVEA
@RW0+disp16, A,
#imm8
@RW0
MOV
MOVEA
@RW1+disp16, A,
#imm8
@RW1
MOV
MOVEA
@RW2+disp16, A,
#imm8
@RW2
MOV
MOVEA
@RW3+disp16, A,
#imm8
@RW3
MOV
MOVEA
@RW0+RW7, A,
#imm8
@RW0+
MOV
MOVEA
@RW1+RW7, A,
#imm8
@RW1+
MOV
MOV
@RW3+disp8, R3,
A
#imm8
MOV
@RW4+disp8, R4,
A
#imm8
MOV
@RW5+disp8, R5,
A
#imm8
MOV
@RW6+disp8, R6,
A
#imm8
MOV
@RW7+disp8, R7,
A
#imm8
MOV
@RW0+disp16, @RW0,
A
#imm8
MOV
@RW1+disp16, @RW1,
A
#imm8
MOV
@RW2+disp16, @RW2,
A
#imm8
MOV
@RW3+disp16, @RW3,
A
#imm8
MOV
@RW0+RW7, @RW0+,
A
#imm8
MOV
@RW1+RW7, @RW1+,
A
#imm8
MOV
@PC+disp16, @RW2+,
A
#imm8
MOVL
addr16,
A
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOVL
MOV
@RW3+,
#imm8
MOVEA
@RW2+disp8, A,
#imm8
RW2
MOV
addr16,
#imm8
MOVEA
A,
@RW3+
MOVEA
@PC+disp16, A,
#imm8
@RW2+
MOV
MOVL
MOV
@RW2+disp8, R2,
A
#imm8
A
@RW1+disp8,
MOVEA
@RW1+disp8, A,
#imm8
RW1
RW0
#imm8
#imm8
MOVL
E0
MOVEA
A
MOV
D0
@RW0+disp8, A,
MOV
C0
@RW0+disp8, R0,
MOVL
B0
MOVEA
A,
addr16
@PC+disp16
MOVEA
A,
@RW1+RW7
MOVEA
A,
@RW0+RW7
MOVEA
A,
@RW3+disp16
MOVEA
A,
@RW2+disp16
MOVEA
A,
@RW1+disp16
MOVEA
A,
@RW0+disp16
MOVEA
A,
@RW7+disp8
MOVEA
A,
@RW6+disp8
MOVEA
A,
@RW5+disp8
MOVEA
A,
@RW4+disp8
MOVEA
A,
@RW3+disp8
MOVEA
A,
@RW2+disp8
MOVEA
A,
@RW1+disp8
MOVEA
A,
@RW0+disp8
MOVEA
A,
F0
F MC-16FX Family
CALLP
@@RW3+disp16 @@RW3
JMPP
JMPP
+4 @RL2
CALLP
@@RW3+disp8 @RL1
JMPP
JMPP
+1 @RL0
CALLP
20
@@RW0+disp8 @RL0
JMPP
10
+0 @RL0
JMPP
00
2
APPENDIX
APPENDIX C Instruction Maps
Table C.6-2 ea-type Instruction (2) (First Byte = 71H)
349
350
RORC
@RW1+disp8 R1
ROLC
RORC
@RW2+disp8 R2
ROLC
ROLC
+2 R2
ROLC
+3 R3
FUJITSU MICROELECTRONICS LIMITED
ROLC
RORC
@RW3+disp16 @RW3
ROLC
ROLC
+B @RW3
ROLC
+C @RW0+
RORC
@PC+disp16 @RW2+
ROLC
addr16
ROLC
+F @RW3+
RORC
@RW3+
ROLC
RORC
ROLC
+E @RW2+
ROLC
@RW1+RW7 @RW1+
+D @RW1+
ROLC
RORC
@RW2+disp16 @RW2
RORC
@RW0+RW7 @RW0+
ROLC
ROLC
+A @RW2
INC
RORC
addr16
INC
@RW3+
INC
@PC+disp16 @RW2+
RORC
@RW1+RW7 @RW1+
RORC
INC
@RW0+RW7 @RW0+
RORC
INC
@RW3+disp16 @RW3
RORC
INC
@RW2+disp16 @RW2
RORC
@RW1+disp16 @RW1
INC
RORC
RORC
ROLC
@RW1+disp16 @RW1
+9 @RW1
ROLC
INC
R6
INC
@RW7+disp8 R7
RORC
@RW6+disp8
RORC
INC
@RW0+disp16 @RW0
ROLC
ROLC
+8 @RW0
INC
@RW5+disp8 R5
RORC
INC
@RW4+disp8 R4
RORC
INC
@RW3+disp8 R3
RORC
INC
@RW2+disp8 R2
RORC
INC
@RW1+disp8 R1
RORC
40
RORC
RORC
@RW7+disp8 R7
INC
@RW0+disp8 R0
RORC
30
RORC
@RW0+disp16 @RW0
ROLC
ROLC
+7 R7
@RW6+disp8
RORC
R6
ROLC
RORC
ROLC
+6 R6
ROLC
@RW5+disp8 R5
ROLC
+5 R5
ROLC
ROLC
+4 R4
RORC
@RW4+disp8 R4
RORC
@RW3+disp8 R3
ROLC
RORC
ROLC
+1 R1
ROLC
@RW0+disp8 R0
ROLC
20
+0 R0
10
00
INC
DEC
DEC
DEC
INC
addr16
DEC
@RW3+
DEC
@PC+disp16 @RW2+
INC
@RW1+RW7 @RW1+
INC
DEC
@RW0+RW7 @RW0+
INC
DEC
@RW3+disp16 @RW3
INC
DEC
@RW2+disp16 @RW2
INC
@RW1+disp16 @RW1
INC
DEC
@RW0+disp16 @RW0
INC
DEC
@RW7+disp8 R7
INC
DEC
@RW6+disp8 R6
INC
@RW5+disp8 R5
INC
DEC
@RW4+disp8 R4
INC
DEC
@RW3+disp8 R3
INC
DEC
@RW2+disp8 R2
INC
DEC
@RW1+disp8 R1
INC
60
DEC
@RW0+disp8 R0
50
MOV
R5
MOV
@RW1
MOV
@RW1+
DEC
addr16
MOV
A,
@RW3+
MOV
@PC+disp16 A,
@RW2+
DEC
@RW1+RW7 A,
DEC
MOV
@RW0+RW7 A,
@RW0+
DEC
MOV
@RW3+disp16 A,
@RW3
DEC
MOV
@RW2+disp16 A,
@RW2
DEC
@RW1+disp16 A,
DEC
MOV
@RW0+disp16 A,
@RW0
DEC
MOV
@RW7+disp8 A,
R7
DEC
MOV
@RW6+disp8 A,
R6
DEC
@RW5+disp8 A,
DEC
MOV
@RW4+disp8 A,
R4
DEC
MOV
@RW3+disp8 A,
R3
DEC
MOV
@RW2+disp8 A,
R2
DEC
MOV
A,
addr16
MOV
@RW3+,
A
MOV
@RW2+,
@PC+disp16 A
MOV
A,
MOV
@RW1+,
@RW1+RW7 A
MOV
A,
MOV
@RW0+,
@RW0+RW7 A
MOV
A,
MOV
@RW3,
@RW3+disp16 A
MOV
A,
MOV
@RW2,
@RW2+disp16 A
MOV
A,
MOV
@RW1,
@RW1+disp16 A
MOV
A,
MOV
@RW0,
@RW0+disp16 A
MOV
A,
MOV
R7,
@RW7+disp8 A
MOV
A,
MOV
R6,
@RW6+disp8 A
MOV
A,
MOV
R5,
@RW5+disp8 A
MOV
A,
MOV
R4,
@RW4+disp8 A
MOV
A,
MOV
R3,
@RW3+disp8 A
MOV
A,
MOV
R2,
@RW2+disp8 A
MOV
A,
MOV
R1,
@RW1+disp8 A
MOV
A,
R0
MOV
@RW1+disp8 A,
R1
DEC
A0
MOV
R0,
MOV
A,
90
@RW0+disp8 A
80
MOV
@RW0+disp8 A,
DEC
70
D0
MOVX
A,
C0
MOVX
A
MOVX
MOVX
A,
XCH
A,
@RW3+disp8 R3
MOVX
A,
MOVX
A,
MOVX
@RW3+disp8, A,
A
R3
MOVX
@RW4+disp8, A,
A
R4
MOVX
MOVX
A,
XCH
A,
@RW7+disp8 R7
MOVX
A,
MOVX
A,
MOVX
@RW7+disp8, A,
A
R7
MOVX
@RW0+disp16, A,
A
@RW0
MOVX
XCH
A,
@RW3+disp16 @RW3
MOVX
A,
MOVX
@RW0+RW7, A,
A
@RW0+
MOV
addr16,
A
MOV
@RW1+
MOVX
A,
@RW3+
MOVX
@PC+disp16, A,
A
@RW2+
A
@RW1+RW7, A,
MOV
MOV
MOVX
MOVX
A,
MOVX
@RW3+disp16, A,
A
@RW3
MOV
MOVX
A,
addr16
XCH
A,
@RW3+
XCH
A,
@PC+disp16 @RW2+
MOVX
A,
XCH
A,
@RW1+RW7 @RW1+
MOVX
A,
XCH
A,
@RW0+RW7 @RW0+
XCH
A,
@RW2+disp16 @RW2
MOV
MOVX
A,
@RW1
XCH
A,
@RW1+disp16 @RW1
MOVX
@RW2+disp16, A,
A
@RW2
A
@RW1+disp16, A,
MOV
MOV
MOV
XCH
A,
@RW0+disp16 @RW0
XCH
A,
@RW6+disp8 R6
MOV
MOVX
A,
R5
XCH
A,
@RW5+disp8 R5
MOVX
@RW6+disp8, A,
A
R6
A
@RW5+disp8, A,
MOV
MOV
MOV
XCH
A,
@RW4+disp8 R4
XCH
A,
@RW2+disp8 R2
R1
MOVX
A,
MOV
MOVX
@RW2+disp8, A,
A
R2
A
XCH
A,
@RW1+disp8 R1
MOVX
A,
R0
@RW1+disp8, A,
MOV
E0
XCH
A,
@RW0+disp8 R0
@RW0+disp8, A,
MOV
B0
XCH
A,
addr16
@PC+disp16
XCH
A,
@RW1+RW7
XCH
A,
@RW0+RW7
XCH
A,
@RW3+disp16
XCH
A,
@RW2+disp16
XCH
A,
@RW1+disp16
XCH
A,
@RW0+disp16
XCH
A,
@RW7+disp8
XCH
A,
@RW6+disp8
XCH
A,
@RW5+disp8
XCH
A,
@RW4+disp8
XCH
A,
@RW3+disp8
XCH
A,
@RW2+disp8
XCH
A,
@RW1+disp8
XCH
A,
@RW0+disp8
XCH
A,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.6-3 ea-type Instruction (3) (First Byte = 72H)
CM44-00203-3E
CM44-00203-3E
CALL
@@RW1+disp8 @RW1
JMP
CALL
@@RW2+disp8 @RW2
JMP
JMP
+2 @RW2
JMP
+3 @RW3
CALL
@@RW4+disp8 @RW4
JMP
CALL
@@RW5+disp8 @RW5
JMP
CALL
@@RW6+disp8 @RW6
JMP
CALL
@@RW7+disp8 @RW7
JMP
CALL
@@RW0+disp16 @@RW0
JMP
CALL
@@RW1+disp16 @@RW1
JMP
CALL
@@RW2+disp16 @@RW2
JMP
JMP
+5 @RW5
JMP
+6 @RW6
JMP
+7 @RW7
JMP
+8 @@RW0
JMP
+9 @@RW1
JMP
+A @@RW2
JMP
+B @@RW3
INCW
40
FUJITSU MICROELECTRONICS LIMITED
DECW
60
DECW
@RW1+RW7 @RW1+
INCW
DECW
@PC+disp16 @RW2+
INCW
addr16
JMP
JMP
CALL
CALL
INCW
+E @@RW2+ @@PC+disp16 @@RW2+ @@PC+disp16 @RW2+
JMP
JMP
+F @@RW3+ @addr16
DECW
@RW3+
INCW
JMP
JMP
CALL
CALL
INCW
+D @@RW1+ @@RW1+RW7 @@RW1+ @@RW1+RW7 @RW1+
INCW
@RW3+
DECW
@RW0+RW7 @RW0+
CALL
CALL
@@RW3+ @addr16
INCW
DECW
@RW3+disp16 @RW3
INCW
DECW
@RW2+disp16 @RW2
INCW
DECW
@RW1+disp16 @RW1
INCW
DECW
@RW0+disp16 @RW0
INCW
DECW
@RW7+disp8 RW7
INCW
DECW
@RW6+disp8 RW6
INCW
DECW
@RW5+disp8 RW5
INCW
DECW
@RW4+disp8 RW4
INCW
DECW
@RW3+disp8 RW3
INCW
DECW
@RW2+disp8 RW2
INCW
DECW
@RW1+disp8 RW1
INCW
@RW0+disp8 RW0
INCW
50
JMP
JMP
CALL
CALL
INCW
+C @@RW0+ @@RW0+RW7 @@RW0+ @@RW0+RW7 @RW0+
INCW
@@RW3+disp16 @RW3
CALL
INCW
@@RW2+disp16 @RW2
CALL
INCW
@@RW1+disp16 @RW1
CALL
INCW
@@RW0+disp16 @RW0
CALL
INCW
@@RW7+disp8 RW7
CALL
INCW
@@RW6+disp8 RW6
CALL
INCW
@@RW5+disp8 RW5
CALL
INCW
@@RW4+disp8 RW4
CALL
INCW
@@RW3+disp8 RW3
CALL
INCW
@@RW2+disp8 RW2
CALL
INCW
@@RW1+disp8 RW1
CALL
@@RW0+disp8 RW0
CALL
30
RW0
@RW0+
@RW1+
DECW
addr16
@RW3+
MOVW
A,
@RW2+
MOVW
@PC+disp16 A,
DECW
MOVW
@RW1+RW7 A,
DECW
MOVW
@RW0+RW7 A,
DECW
MOVW
@RW3+disp16 A,
@RW3
DECW
MOVW
@RW2+disp16 A,
@RW2
DECW
MOVW
@RW1+disp16 A,
@RW1
DECW
MOVW
@RW0+disp16 A,
@RW0
DECW
MOVW
@RW7+disp8 A,
RW7
DECW
MOVW
@RW6+disp8 A,
RW6
DECW
MOVW
@RW5+disp8 A,
RW5
DECW
MOVW
@RW4+disp8 A,
RW4
DECW
MOVW
@RW3+disp8 A,
RW3
DECW
MOVW
@RW2+disp8 A,
RW2
DECW
MOVW
@RW1+disp8 A,
RW1
DECW
80
MOVW
@RW0+disp8 A,
DECW
70
A0
MOVW
@RW0,
A
MOVW
A,
addr16
MOVW
@RW3+,
A
MOVW
@RW2+,
@PC+disp16 A
MOVW
A,
MOVW
@RW1+,
@RW1+RW7 A
MOVW
A,
MOVW
@RW0+,
@RW0+RW7 A
MOVW
A,
MOVW
@RW3,
@RW3+disp16 A
MOVW
A,
MOVW
@RW2,
@RW2+disp16 A
MOVW
A,
MOVW
@RW1,
@RW1+disp16 A
MOVW
A,
@RW0+disp16
MOVW
A,
MOVW
RW7,
@RW7+disp8 A
MOVW
A,
MOVW
RW6,
@RW6+disp8 A
MOVW
A,
MOVW
RW5,
@RW5+disp8 A
MOVW
A,
MOVW
RW4,
@RW4+disp8 A
MOVW
A,
MOVW
RW3,
@RW3+disp8 A
MOVW
A,
MOVW
RW2,
@RW2+disp8 A
MOVW
A,
MOVW
RW1,
@RW1+disp8 A
MOVW
A,
MOVW
RW0,
@RW0+disp8 A
MOVW
A,
90
MOVW
XCHW
@RW0+disp16, A,
#imm16
@RW0
MOVW
XCHW
@RW1+disp16, A,
#imm16
@RW1
MOVW
XCHW
@RW2+disp16, A,
#imm16
@RW2
MOVW
XCHW
@RW3+disp16, A,
#imm16
@RW3
MOVW
XCHW
@RW0+RW7, A,
#imm16
@RW0+
MOVW
XCHW
@RW1+RW7, A,
#imm16
@RW1+
MOVW
MOVW
@RW0+disp16, @RW0,
A
#imm16
MOVW
@RW1+disp16, @RW1,
A
#imm16
MOVW
@RW2+disp16, @RW2,
A
#imm16
MOVW
@RW3+disp16, @RW3,
A
#imm16
MOVW
@RW0+RW7, @RW0+,
A
#imm16
MOVW
@RW1+RW7, @RW1+,
A
#imm16
MOVW
@PC+disp16, @RW2+,
A
#imm16
MOVW
addr16,
A
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
@RW3+,
#imm16
XCHW
@RW7+disp8, A,
#imm16
RW7
MOVW
addr16,
#imm16
XCHW
A,
@RW3+
XCHW
@PC+disp16, A,
#imm16
@RW2+
MOVW
MOVW
MOVW
MOVW
@RW7+disp8, RW7,
A
#imm16
XCHW
A,
RW5
XCHW
A,
RW4
XCHW
A,
RW3
XCHW
A,
RW2
XCHW
A,
RW1
XCHW
@RW6+disp8, A,
#imm16
RW6
#imm16
@RW5+disp8,
MOVW
#imm16
@RW4+disp8,
MOVW
#imm16
@RW3+disp8,
MOVW
#imm16
@RW2+disp8,
MOVW
#imm16
@RW1+disp8,
MOVW
#imm16
XCHW
A,
RW0
E0
MOVW
MOVW
RW5,
#imm16
MOVW
RW4,
#imm16
MOVW
RW3,
#imm16
MOVW
RW2,
#imm16
MOVW
RW1,
#imm16
MOVW
MOVW
RW0,
#imm16
@RW0+disp8,
D0
C0
MOVW
@RW6+disp8, RW6,
A
#imm16
A
@RW5+disp8,
MOVW
A
@RW4+disp8,
MOVW
A
@RW3+disp8,
MOVW
A
@RW2+disp8,
MOVW
A
@RW1+disp8,
MOVW
A
@RW0+disp8,
MOVW
B0
XCHW
A,
addr16
@PC+disp16
XCHW
A,
@RW1+RW7
XCHW
A,
@RW0+RW7
XCHW
A,
@RW3+disp16
XCHW
A,
@RW2+disp16
XCHW
A,
@RW1+disp16
XCHW
A,
@RW0+disp16
XCHW
A,
@RW7+disp8
XCHW
A,
@RW6+disp8
XCHW
A,
@RW5+disp8
XCHW
A,
@RW4+disp8
XCHW
A,
@RW3+disp8
XCHW
A,
@RW2+disp8
XCHW
A,
@RW1+disp8
XCHW
A,
@RW0+disp8
XCHW
A,
F0
F MC-16FX Family
CALL
@@RW3+disp16 @@RW3
JMP
JMP
+4 @RW4
CALL
@@RW3+disp8 @RW3
JMP
JMP
+1 @RW1
CALL
20
@@RW0+disp8 @RW0
JMP
10
+0 @RW0
JMP
00
2
APPENDIX
APPENDIX C Instruction Maps
Table C.6-4 ea-type Instruction (4) (First Byte = 73H)
351
352
ADD
A,
R0
FUJITSU MICROELECTRONICS LIMITED
SUB
A,
@RW1+disp8 R1
ADD
A,
SUB
A,
@RW2+disp8 R2
ADD
A,
SUB
A,
@RW3+disp8 R3
ADD
A,
SUB
A,
@RW4+disp8 R4
ADD
A,
SUB
A,
@RW5+disp8 R5
ADD
A,
SUB
A,
@RW6+disp8 R6
ADD
A,
SUB
A,
@RW7+disp8 R7
ADD
A,
SUB
A,
@RW0+disp16 @RW0
ADD
A,
SUB
A,
@RW1+disp16 @RW1
ADD
A,
SUB
A,
@RW2+disp16 @RW2
ADD
A,
SUB
A,
@RW3+disp16 @RW3
ADD
A,
ADD
+2 A,
R2
ADD
+3 A,
R3
ADD
+4 A,
R4
ADD
+5 A,
R5
ADD
+6 A,
R6
ADD
+7 A,
R7
ADD
+8 A,
@RW0
ADD
+9 A,
@RW1
ADD
+A A,
@RW2
ADD
+B A,
@RW3
ADD
+C A,
@RW0+
SUB
A,
@RW1+RW7 @RW1+
ADD
A,
SUB
A,
@PC+disp16 @RW2+
ADD
A,
addr16
ADD
+E A,
@RW2+
ADD
+F A,
@RW3+
SUB
A,
@RW3+
ADD
A,
ADD
+D A,
@RW1+
SUB
A,
@RW0+RW7 @RW0+
ADD
A,
SUB
A,
R0
20
ADD
+1 A,
R1
+0 A,
@RW0+disp8
10
ADD
00
ADDC
A,
R0
40
SUB
A,
addr16
ADDC
A,
@RW3+
ADDC
A,
@PC+disp16 @RW2+
SUB
A,
ADDC
A,
@RW1+RW7 @RW1+
SUB
A,
ADDC
A,
@RW0+RW7 @RW0+
SUB
A,
ADDC
A,
@RW3+disp16 @RW3
SUB
A,
ADDC
A,
@RW2+disp16 @RW2
SUB
A,
ADDC
A,
@RW1+disp16 @RW1
SUB
A,
ADDC
A,
@RW0+disp16 @RW0
SUB
A,
ADDC
A,
@RW7+disp8 R7
SUB
A,
ADDC
A,
@RW6+disp8 R6
SUB
A,
ADDC
A,
@RW5+disp8 R5
SUB
A,
ADDC
A,
@RW4+disp8 R4
SUB
A,
ADDC
A,
@RW3+disp8 R3
SUB
A,
ADDC
A,
@RW2+disp8 R2
SUB
A,
ADDC
A,
@RW1+disp8 R1
SUB
A,
@RW0+disp8
SUB
A,
30
CMP
A,
R0
60
ADDC
A,
addr16
CMP
A,
@RW3+
CMP
A,
@PC+disp16 @RW2+
ADDC
A,
CMP
A,
@RW1+RW7 @RW1+
ADDC
A,
CMP
A,
@RW0+RW7 @RW0+
ADDC
A,
CMP
A,
@RW3+disp16 @RW3
ADDC
A,
CMP
A,
@RW2+disp16 @RW2
ADDC
A,
CMP
A,
@RW1+disp16 @RW1
ADDC
A,
CMP
A,
@RW0+disp16 @RW0
ADDC
A,
CMP
A,
@RW7+disp8 R7
ADDC
A,
CMP
A,
@RW6+disp8 R6
ADDC
A,
CMP
A,
@RW5+disp8 R5
ADDC
A,
CMP
A,
@RW4+disp8 R4
ADDC
A,
CMP
A,
@RW3+disp8 R3
ADDC
A,
CMP
A,
@RW2+disp8 R2
ADDC
A,
CMP
A,
@RW1+disp8 R1
ADDC
A,
@RW0+disp8
ADDC
A,
50
AND
A,
R0
80
CMP
A,
addr16
AND
A,
@RW3+
AND
A,
@PC+disp16 @RW2+
CMP
A,
AND
A,
@RW1+RW7 @RW1+
CMP
A,
AND
A,
@RW0+RW7 @RW0+
CMP
A,
AND
A,
@RW3+disp16 @RW3
CMP
A,
AND
A,
@RW2+disp16 @RW2
CMP
A,
AND
A,
@RW1+disp16 @RW1
CMP
A,
AND
A,
@RW0+disp16 @RW0
CMP
A,
AND
A,
@RW7+disp8 R7
CMP
A,
AND
A,
@RW6+disp8 R6
CMP
A,
AND
A,
@RW5+disp8 R5
CMP
A,
AND
A,
@RW4+disp8 R4
CMP
A,
AND
A,
@RW3+disp8 R3
CMP
A,
AND
A,
@RW2+disp8 R2
CMP
A,
AND
A,
@RW1+disp8 R1
CMP
A,
@RW0+disp8
CMP
A,
70
OR
A,
R0
A0
AND
A,
addr16
OR
A,
@RW3+
OR
A,
@PC+disp16 @RW2+
AND
A,
OR
A,
@RW1+RW7 @RW1+
AND
A,
OR
A,
@RW0+RW7 @RW0+
AND
A,
OR
A,
@RW3+disp16 @RW3
AND
A,
OR
A,
@RW2+disp16 @RW2
AND
A,
OR
A,
@RW1+disp16 @RW1
AND
A,
OR
A,
@RW0+disp16 @RW0
AND
A,
OR
A,
@RW7+disp8 R7
AND
A,
OR
A,
@RW6+disp8 R6
AND
A,
OR
A,
@RW5+disp8 R5
AND
A,
OR
A,
@RW4+disp8 R4
AND
A,
OR
A,
@RW3+disp8 R3
AND
A,
OR
A,
@RW2+disp8 R2
AND
A,
OR
A,
@RW1+disp8 R1
AND
A,
@RW0+disp8
AND
A,
90
XOR
A,
R0
C0
OR
A,
addr16
XOR
A,
@RW3+
XOR
A,
@PC+disp16 @RW2+
OR
A,
XOR
A,
@RW1+RW7 @RW1+
OR
A,
XOR
A,
@RW0+RW7 @RW0+
OR
A,
XOR
A,
@RW3+disp16 @RW3
OR
A,
XOR
A,
@RW2+disp16 @RW2
OR
A,
XOR
A,
@RW1+disp16 @RW1
OR
A,
XOR
A,
@RW0+disp16 @RW0
OR
A,
XOR
A,
@RW7+disp8 R7
OR
A,
XOR
A,
@RW6+disp8 R6
OR
A,
XOR
A,
@RW5+disp8 R5
OR
A,
XOR
A,
@RW4+disp8 R4
OR
A,
XOR
A,
@RW3+disp8 R3
OR
A,
XOR
A,
@RW2+disp8 R2
OR
A,
XOR
A,
@RW1+disp8 R1
OR
A,
@RW0+disp8
OR
A,
B0
DBNZ
R1,
rel
DBNZ
R0,
rel
E0
XOR
A,
addr16
DBNZ
@RW3+,
rel
DBNZ
@RW2+,
@PC+disp16 rel
XOR
A,
DBNZ
@RW1+,
@RW1+RW7 rel
XOR
A,
DBNZ
@RW0+,
@RW0+RW7 rel
XOR
A,
DBNZ
@RW3,
@RW3+disp16 rel
XOR
A,
DBNZ
@RW2,
@RW2+disp16 rel
XOR
A,
DBNZ
@RW1,
@RW1+disp16 rel
XOR
A,
DBNZ
@RW0,
@RW0+disp16 rel
XOR
A,
DBNZ
R7,
@RW7+disp8 rel
XOR
A,
DBNZ
R6,
@RW6+disp8 rel
XOR
A,
DBNZ
R5,
@RW5+disp8 rel
XOR
A,
DBNZ
R4,
@RW4+disp8 rel
XOR
A,
DBNZ
R3,
@RW3+disp8 rel
XOR
A,
DBNZ
R2,
@RW2+disp8 rel
XOR
A,
@RW1+disp8
XOR
A,
@RW0+disp8
XOR
A,
D0
DBNZ
addr16,
rel
rel
@PC+disp16,
DBNZ
rel
@RW1+RW7,
DBNZ
rel
@RW0+RW7,
DBNZ
rel
@RW3+disp16,
DBNZ
rel
@RW2+disp16,
DBNZ
rel
@RW1+disp16,
DBNZ
rel
@RW0+disp16,
DBNZ
rel
@RW7+disp8,
DBNZ
rel
@RW6+disp8,
DBNZ
rel
@RW5+disp8,
DBNZ
rel
@RW4+disp8,
DBNZ
rel
@RW3+disp8,
DBNZ
rel
@RW2+disp8,
DBNZ
rel
@RW1+disp8,
DBNZ
rel
@RW0+disp8,
DBNZ
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.6-5 ea-type Instruction (5) (First Byte = 74H)
CM44-00203-3E
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
ADD
SUB
SUB
ADD
A
SUB
A
SUB
A
ADD
A
SUB
A
SUB
A
ADD
A
SUB
A
SUB
A
ADD
A
SUB
A
SUB
A
ADD
A
SUB
A
SUB
A
ADD
A
SUB
@RW3+,
A
SUB
addr16,
A
ADD
addr16,
A
ADD
+F @RW3+,
SUBC
A,
@RW3+
@RW2+
A
A
A
A
@PC+disp16, A,
SUBC
@RW1+
@RW1+RW7, A,
@RW1+RW7, @RW1+,
SUBC
@RW0+
@RW0+RW7, A,
@RW0+RW7, @RW0+,
SUBC
@RW3
@RW3+disp16, A,
@RW3+disp16, @RW3,
SUBC
@RW2
@RW2+disp16, A,
@RW2+disp16, @RW2,
SUBC
@RW1
@RW1+disp16, A,
@RW1+disp16, @RW1,
SUBC
@RW0
A
A
A
SUBC
@RW0+disp16, A,
@RW0+disp16, @RW0,
@PC+disp16, @RW2+,
+E @RW2+,
ADD
A
+D @RW1+,
ADD
A
+C @RW0+,
ADD
A
+B @RW3,
SUB
SUB
ADD
R7
A
A
A
SUBC
A,
addr16
@PC+disp16
SUBC
A,
@RW1+RW7
SUBC
A,
@RW0+RW7
SUBC
A,
@RW3+disp16
SUBC
A,
@RW2+disp16
SUBC
A,
@RW1+disp16
SUBC
A,
@RW0+disp16
SUBC
A,
@RW7+disp8
SUBC
A,
@RW6+disp8
SUBC
A,
@RW5+disp8
SUBC
A,
@RW4+disp8
SUBC
A,
@RW3+disp8
SUBC
A,
@RW2+disp8
SUBC
A,
@RW1+disp8
SUBC
A,
@RW0+disp8
SUBC
A,
50
NEG
@RW3+
NEG
@RW2+
NEG
@RW1+
NEG
@RW0+
NEG
@RW3
NEG
@RW2
NEG
@RW1
NEG
@RW0
NEG
R7
NEG
R6
NEG
R5
NEG
R4
NEG
R3
NEG
R2
NEG
R1
NEG
R0
60
AND
AND
R1,
A
AND
A
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
AND
NEG
addr16
AND
@RW3+,
A
A
@PC+disp16 @RW2+,
NEG
A
@RW1+RW7 @RW1+,
NEG
A
@RW0+RW7 @RW0+,
NEG
A
@RW3+disp16 @RW3,
NEG
A
@RW2+disp16 @RW2,
NEG
A
@RW1+disp16 @RW1,
NEG
A
@RW0+disp16 @RW0,
NEG
A
@RW7+disp8 R7,
NEG
A
@RW6+disp8 R6,
NEG
A
@RW5+disp8 R5,
NEG
A
@RW4+disp8 R4,
NEG
A
@RW3+disp8 R3,
NEG
80
AND
R0,
A
@RW2+disp8 R2,
NEG
@RW1+disp8
NEG
@RW0+disp8
NEG
70
OR
OR
A
OR
A
OR
A
OR
A
OR
A
OR
A
OR
A
OR
A
A0
OR
A
OR
A
OR
A
OR
A
OR
A
OR
A
AND
addr16,
A
A
OR
@RW3+,
A
A
@PC+disp16, @RW2+,
AND
A
@RW1+RW7, @RW1+,
AND
A
@RW0+RW7, @RW0+,
AND
A
@RW3+disp16, @RW3,
AND
A
@RW2+disp16, @RW2,
AND
A
@RW1+disp16, @RW1,
AND
A
@RW0+disp16, @RW0,
AND
A
@RW7+disp8, R7,
AND
A
@RW6+disp8, R6,
AND
A
@RW5+disp8, R5,
AND
A
@RW4+disp8, R4,
AND
A
@RW3+disp8, R3,
AND
A
@RW2+disp8, R2,
AND
A
@RW1+disp8, R1,
AND
A
@RW0+disp8, R0,
AND
90
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
XOR
A
OR
addr16,
A
A
XOR
@RW3+,
A
A
@PC+disp16, @RW2+,
OR
A
@RW1+RW7, @RW1+,
OR
A
@RW0+RW7, @RW0+,
OR
A
@RW3+disp16, @RW3,
OR
A
@RW2+disp16, @RW2,
OR
A
@RW1+disp16, @RW1,
OR
A
@RW0+disp16, @RW0,
OR
A
@RW7+disp8, R7,
OR
A
@RW6+disp8, R6,
OR
A
@RW5+disp8, R5,
OR
A
@RW4+disp8, R4,
OR
A
@RW3+disp8, R3,
OR
A
@RW2+disp8, R2,
OR
A
@RW1+disp8, R1,
OR
A
C0
XOR
@RW0+disp8, R0,
OR
B0
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
NOT
XOR
addr16,
A
A
NOT
@RW3+
@PC+disp16, @RW2+
XOR
A
@RW1+RW7, @RW1+
XOR
A
@RW0+RW7, @RW0+
XOR
A
@RW3+disp16, @RW3
XOR
A
@RW2+disp16, @RW2
XOR
A
@RW1+disp16, @RW1
XOR
A
@RW0+disp16, @RW0
XOR
A
@RW7+disp8, R7
XOR
A
@RW6+disp8, R6
XOR
A
@RW5+disp8, R5
XOR
A
@RW4+disp8, R4
XOR
A
@RW3+disp8, R3
XOR
A
@RW2+disp8, R2
XOR
A
@RW1+disp8, R1
XOR
A
E0
NOT
@RW0+disp8, R0
XOR
D0
NOT
addr16
@PC+disp16
NOT
@RW1+RW7
NOT
@RW0+RW7
NOT
@RW3+disp16
NOT
@RW2+disp16
NOT
@RW1+disp16
NOT
@RW0+disp16
NOT
@RW7+disp8
NOT
@RW6+disp8
NOT
@RW5+disp8
NOT
@RW4+disp8
NOT
@RW3+disp8
NOT
@RW2+disp8
NOT
@RW1+disp8
NOT
@RW0+disp8
NOT
F0
F MC-16FX Family
A
+A @RW2,
ADD
A
+9 @RW1,
ADD
A
+8 @RW0,
ADD
A
SUBC
@RW7+disp8, A,
SUB
@RW7+disp8, R7,
SUB
ADD
ADD
+7 R7,
R6
A
A
A
A
SUBC
@RW6+disp8, A,
SUB
@RW6+disp8, R6,
SUB
ADD
ADD
+6 R6,
R5
A
A
A
A
SUBC
@RW5+disp8, A,
SUB
@RW5+disp8, R5,
SUB
ADD
R4
ADD
+5 R5,
A
A
SUBC
A
SUB
A
SUB
@RW4+disp8, A,
ADD
R3
A
A
A
@RW4+disp8, R4,
+4 R4,
ADD
A
SUBC
@RW3+disp8, A,
SUB
@RW3+disp8, R3,
SUB
ADD
ADD
+3 R3,
R2
A
A
A
A
SUBC
@RW2+disp8, A,
SUB
@RW2+disp8, R2,
SUB
ADD
ADD
+2 R2,
R1
A
A
A
A
SUBC
@RW1+disp8, A,
SUB
@RW1+disp8, R1,
SUB
ADD
ADD
+1 R1,
R0
A
A
40
SUBC
A
SUB
30
A
SUB
20
@RW0+disp8, A,
ADD
10
@RW0+disp8, R0,
+0 R0,
ADD
00
2
APPENDIX
APPENDIX C Instruction Maps
Table C.6-6 ea-type Instruction (6) (First Byte = 75H)
353
354
RW0
ADDW
A,
SUBW
A,
@RW2+disp8 RW2
ADDW
A,
SUBW
A,
@RW3+disp8 RW3
ADDW
A,
SUBW
A,
@RW4+disp8 RW4
ADDW
A,
SUBW
A,
@RW5+disp8 RW5
ADDW
A,
SUBW
A,
@RW6+disp8 RW6
ADDW
A,
SUBW
A,
@RW7+disp8 RW7
ADDW
A,
ADDW
A,
ADDW
+2 A,
RW2
ADDW
+3 A,
RW3
ADDW
+4 A,
RW4
ADDW
+5 A,
RW5
ADDW
+6 A,
RW6
ADDW
+7 A,
RW7
ADDW
+8 A,
@RW0
ADDW
FUJITSU MICROELECTRONICS LIMITED
SUBW
A,
@RW2+disp16 @RW2
ADDW
A,
SUBW
A,
@RW3+disp16 @RW3
ADDW
A,
ADDW
+B A,
@RW3
ADDW
+C A,
@RW0+
SUBW
A,
@RW1+RW7 @RW1+
ADDW
A,
SUBW
A,
@PC+disp16 @RW2+
ADDW
A,
addr16
ADDW
+E A,
@RW2+
ADDW
+F A,
@RW3+
SUBW
A,
@RW3+
ADDW
A,
ADDW
+D A,
@RW1+
SUBW
A,
@RW0+RW7 @RW0+
ADDW
A,
SUBW
A,
@RW1+disp16 @RW1
ADDW
+A A,
@RW2
@RW1
+9 A,
SUBW
A,
@RW1+disp8 RW1
SUBW
A,
@RW0+disp16 @RW0
ADDW
A,
ADDW
+1 A,
RW1
SUBW
A,
ADDW
A,
@RW0+disp8 RW0
+0 A,
ADDW
20
10
00
ADDCW
A,
40
SUBW
A,
addr16
ADDCW
A,
@RW3+
ADDCW
A,
@PC+disp16 @RW2+
SUBW
A,
ADDCW
A,
@RW1+RW7 @RW1+
SUBW
A,
ADDCW
A,
@RW0+RW7 @RW0+
SUBW
A,
ADDCW
A,
@RW3+disp16 @RW3
SUBW
A,
ADDCW
A,
@RW2+disp16 @RW2
SUBW
A,
ADDCW
A,
@RW1+disp16 @RW1
SUBW
A,
ADDCW
A,
@RW0+disp16 @RW0
SUBW
A,
ADDCW
A,
@RW7+disp8 RW7
SUBW
A,
ADDCW
A,
@RW6+disp8 RW6
SUBW
A,
ADDCW
A,
@RW5+disp8 RW5
SUBW
A,
ADDCW
A,
@RW4+disp8 RW4
SUBW
A,
ADDCW
A,
@RW3+disp8 RW3
SUBW
A,
ADDCW
A,
@RW2+disp8 RW2
SUBW
A,
ADDCW
A,
@RW1+disp8 RW1
SUBW
A,
@RW0+disp8 RW0
SUBW
A,
30
CMPW
A,
60
ADDCW
A,
addr16
CMPW
A,
@RW3+
CMPW
A,
@PC+disp16 @RW2+
ADDCW
A,
CMPW
A,
@RW1+RW7 @RW1+
ADDCW
A,
CMPW
A,
@RW0+RW7 @RW0+
ADDCW
A,
CMPW
A,
@RW3+disp16 @RW3
ADDCW
A,
CMPW
A,
@RW2+disp16 @RW2
ADDCW
A,
CMPW
A,
@RW1+disp16 @RW1
ADDCW
A,
CMPW
A,
@RW0+disp16 @RW0
ADDCW
A,
CMPW
A,
@RW7+disp8 RW7
ADDCW
A,
CMPW
A,
@RW6+disp8 RW6
ADDCW
A,
CMPW
A,
@RW5+disp8 RW5
ADDCW
A,
CMPW
A,
@RW4+disp8 RW4
ADDCW
A,
CMPW
A,
@RW3+disp8 RW3
ADDCW
A,
CMPW
A,
@RW2+disp8 RW2
ADDCW
A,
CMPW
A,
@RW1+disp8 RW1
ADDCW
A,
@RW0+disp8 RW0
ADDCW
A,
50
ANDW
A,
80
CMPW
A,
addr16
ANDW
A,
@RW3+
ANDW
A,
@PC+disp16 @RW2+
CMPW
A,
ANDW
A,
@RW1+RW7 @RW1+
CMPW
A,
ANDW
A,
@RW0+RW7 @RW0+
CMPW
A,
ANDW
A,
@RW3+disp16 @RW3
CMPW
A,
ANDW
A,
@RW2+disp16 @RW2
CMPW
A,
ANDW
A,
@RW1+disp16 @RW1
CMPW
A,
ANDW
A,
@RW0+disp16 @RW0
CMPW
A,
ANDW
A,
@RW7+disp8 RW7
CMPW
A,
ANDW
A,
@RW6+disp8 RW6
CMPW
A,
ANDW
A,
@RW5+disp8 RW5
CMPW
A,
ANDW
A,
@RW4+disp8 RW4
CMPW
A,
ANDW
A,
@RW3+disp8 RW3
CMPW
A,
ANDW
A,
@RW2+disp8 RW2
CMPW
A,
ANDW
A,
@RW1+disp8 RW1
CMPW
A,
@RW0+disp8 RW0
CMPW
A,
70
ORW
A,
A0
ANDW
A,
addr16
ORW
A,
@RW3+
ORW
A,
@PC+disp16 @RW2+
ANDW
A,
ORW
A,
@RW1+RW7 @RW1+
ANDW
A,
ORW
A,
@RW0+RW7 @RW0+
ANDW
A,
ORW
A,
@RW3+disp16 @RW3
ANDW
A,
ORW
A,
@RW2+disp16 @RW2
ANDW
A,
ORW
A,
@RW1+disp16 @RW1
ANDW
A,
ORW
A,
@RW0+disp16 @RW0
ANDW
A,
ORW
A,
@RW7+disp8 RW7
ANDW
A,
ORW
A,
@RW6+disp8 RW6
ANDW
A,
ORW
A,
@RW5+disp8 RW5
ANDW
A,
ORW
A,
@RW4+disp8 RW4
ANDW
A,
ORW
A,
@RW3+disp8 RW3
ANDW
A,
ORW
A,
@RW2+disp8 RW2
ANDW
A,
ORW
A,
@RW1+disp8 RW1
ANDW
A,
@RW0+disp8 RW0
ANDW
A,
90
XORW
A,
C0
ORW
A,
addr16
XORW
A,
@RW3+
XORW
A,
@PC+disp16 @RW2+
ORW
A,
XORW
A,
@RW1+RW7 @RW1+
ORW
A,
XORW
A,
@RW0+RW7 @RW0+
ORW
A,
XORW
A,
@RW3+disp16 @RW3
ORW
A,
XORW
A,
@RW2+disp16 @RW2
ORW
A,
XORW
A,
@RW1+disp16 @RW1
ORW
A,
XORW
A,
@RW0+disp16 @RW0
ORW
A,
XORW
A,
@RW7+disp8 RW7
ORW
A,
XORW
A,
@RW6+disp8 RW6
ORW
A,
XORW
A,
@RW5+disp8 RW5
ORW
A,
XORW
A,
@RW4+disp8 RW4
ORW
A,
XORW
A,
@RW3+disp8 RW3
ORW
A,
XORW
A,
@RW2+disp8 RW2
ORW
A,
XORW
A,
@RW1+disp8 RW1
ORW
A,
@RW0+disp8 RW0
ORW
A,
B0
XORW
A,
addr16
DWBNZ
@RW3+,
rel
DWBNZ
@RW2+,
@PC+disp16 rel
XORW
A,
DWBNZ
@RW1+,
@RW1+RW7 rel
XORW
A,
DWBNZ
@RW0+,
@RW0+RW7 rel
XORW
A,
DWBNZ
@RW3,
@RW3+disp16 rel
XORW
A,
DWBNZ
@RW2,
@RW2+disp16 rel
XORW
A,
DWBNZ
@RW1,
@RW1+disp16 rel
XORW
A,
DWBNZ
@RW0,
@RW0+disp16 rel
XORW
A,
DWBNZ
RW7,
@RW7+disp8 rel
XORW
A,
DWBNZ
RW6,
@RW6+disp8 rel
XORW
A,
DWBNZ
RW5,
@RW5+disp8 rel
XORW
A,
DWBNZ
RW4,
@RW4+disp8 rel
XORW
A,
DWBNZ
RW3,
@RW3+disp8 rel
XORW
A,
DWBNZ
RW2,
@RW2+disp8 rel
XORW
A,
DWBNZ
RW1,
@RW1+disp8 rel
XORW
A,
E0
DWBNZ
RW0,
@RW0+disp8 rel
XORW
A,
D0
DWBNZ
addr16,
rel
rel
@PC+disp16,
DWBNZ
rel
@RW1+RW7,
DWBNZ
rel
@RW0+RW7,
DWBNZ
rel
@RW3+disp16,
DWBNZ
rel
@RW2+disp16,
DWBNZ
rel
@RW1+disp16,
DWBNZ
@RW0+disp16,
rel
DWBNZ
rel
@RW7+disp8,
DWBNZ
rel
@RW6+disp8,
DWBNZ
rel
@RW5+disp8,
DWBNZ
rel
@RW4+disp8,
DWBNZ
rel
@RW3+disp8,
DWBNZ
rel
@RW2+disp8,
DWBNZ
rel
@RW1+disp8,
DWBNZ
rel
@RW0+disp8,
DWBNZ
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.6-7 ea-type Instruction (7) (First Byte = 76H)
CM44-00203-3E
ADDW
ADDW
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
355
A
+F @RW3+,
ADDW
A
+E @RW2+,
ADDW
A
+D @RW1+,
ADDW
A
+C @RW0+,
ADDW
A
+B @RW3,
ADDW
A
SUBW
ADDW
ADDW
ADDW
addr16,
A
A
@PC+disp16,
ADDW
A
@RW1+RW7,
SUBW
@RW3+,
A
SUBW
@RW2+,
A
SUBW
@RW1+,
A
SUBW
addr16,
A
A
@PC+disp16,
SUBW
A
@RW1+RW7,
SUBW
A
@RW0+RW7,
SUBW
SUBW
@RW0+,
A
ADDW
A
@RW0+RW7,
SUBCW
A,
@RW3+
SUBCW
A,
@RW2+
SUBCW
A,
@RW1+
SUBCW
A,
@RW0+
@RW3
A
A
A
SUBCW
@RW3+disp16, A,
@RW3+disp16, @RW3,
SUBW
SUBW
ADDW
@RW2
A
A
A
SUBCW
@RW2+disp16, A,
@RW2+disp16, @RW2,
SUBW
SUBW
ADDW
@RW1
A
A
A
SUBCW
@RW1+disp16, A,
@RW1+disp16, @RW1,
SUBW
A
@RW0
A
A
SUBCW
@RW0+disp16, A,
@RW0+disp16, @RW0,
SUBW
SUBW
ADDW
RW7
A
A
A
SUBCW
A,
addr16
@PC+disp16
SUBCW
A,
@RW1+RW7
SUBCW
A,
@RW0+RW7
SUBCW
A,
@RW3+disp16
SUBCW
A,
@RW2+disp16
SUBCW
A,
@RW1+disp16
SUBCW
A,
@RW0+disp16
SUBCW
A,
@RW7+disp8
SUBCW
A,
@RW6+disp8
SUBCW
A,
@RW5+disp8
SUBCW
A,
@RW4+disp8
SUBCW
A,
@RW3+disp8
SUBCW
A,
@RW2+disp8
SUBCW
A,
@RW1+disp8
SUBCW
A,
@RW0+disp8
SUBCW
A,
50
NEGW
@RW3+
NEGW
@RW2+
NEGW
@RW1+
NEGW
@RW0+
NEGW
@RW3
NEGW
@RW2
NEGW
@RW1
NEGW
@RW0
NEGW
RW7
NEGW
RW6
NEGW
RW5
NEGW
RW4
NEGW
RW3
NEGW
RW2
NEGW
RW1
NEGW
RW0
60
ANDW
ANDW
RW7,
A
ANDW
RW6,
A
ANDW
RW5,
A
ANDW
RW4,
A
ANDW
RW3,
A
ANDW
RW2,
A
ANDW
RW1,
A
ANDW
RW0,
A
80
ANDW
ANDW
ANDW
NEGW
addr16
@PC+disp16
NEGW
@RW1+RW7
NEGW
@RW0+RW7
NEGW
ANDW
@RW3+,
A
ANDW
@RW2+,
A
ANDW
@RW1+,
A
ANDW
@RW0+,
A
A
@RW3+disp16 @RW3,
NEGW
A
@RW2+disp16 @RW2,
NEGW
A
@RW1+disp16 @RW1,
NEGW
A
@RW0+disp16 @RW0,
NEGW
@RW7+disp8
NEGW
@RW6+disp8
NEGW
@RW5+disp8
NEGW
@RW4+disp8
NEGW
@RW3+disp8
NEGW
@RW2+disp8
NEGW
@RW1+disp8
NEGW
@RW0+disp8
NEGW
70
ORW
A0
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ORW
A
ANDW
addr16,
A
A
@PC+disp16,
ANDW
A
@RW1+RW7,
ANDW
A
@RW0+RW7,
ANDW
A
ORW
@RW3+,
A
ORW
@RW2+,
A
ORW
@RW1+,
A
ORW
@RW0+,
A
A
@RW3+disp16, @RW3,
ANDW
A
@RW2+disp16, @RW2,
ANDW
A
@RW1+disp16, @RW1,
ANDW
A
@RW0+disp16, @RW0,
ANDW
A
@RW7+disp8, RW7,
ANDW
A
@RW6+disp8, RW6,
ANDW
A
@RW5+disp8, RW5,
ANDW
A
@RW4+disp8, RW4,
ANDW
A
@RW3+disp8, RW3,
ANDW
A
@RW2+disp8, RW2,
ANDW
A
@RW1+disp8, RW1,
ANDW
A
@RW0+disp8, RW0,
ANDW
90
XORW
C0
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
XORW
A
ORW
addr16,
A
A
@PC+disp16,
ORW
A
@RW1+RW7,
ORW
A
@RW0+RW7,
ORW
A
XORW
@RW3+,
A
XORW
@RW2+,
A
XORW
@RW1+,
A
XORW
@RW0+,
A
A
@RW3+disp16, @RW3,
ORW
A
@RW2+disp16, @RW2,
ORW
A
@RW1+disp16, @RW1,
ORW
A
@RW0+disp16, @RW0,
ORW
A
@RW7+disp8, RW7,
ORW
A
@RW6+disp8, RW6,
ORW
A
@RW5+disp8, RW5,
ORW
A
@RW4+disp8, RW4,
ORW
A
@RW3+disp8, RW3,
ORW
A
@RW2+disp8, RW2,
ORW
A
@RW1+disp8, RW1,
ORW
A
@RW0+disp8, RW0,
ORW
B0
NOTW
E0
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
NOTW
XORW
addr16,
A
A
@PC+disp16,
XORW
A
@RW1+RW7,
XORW
A
@RW0+RW7,
XORW
A
NOTW
@RW3+
NOTW
@RW2+
NOTW
@RW1+
NOTW
@RW0+
@RW3+disp16, @RW3
XORW
A
@RW2+disp16, @RW2
XORW
A
@RW1+disp16, @RW1
XORW
A
@RW0+disp16, @RW0
XORW
A
@RW7+disp8, RW7
XORW
A
@RW6+disp8, RW6
XORW
A
@RW5+disp8, RW5
XORW
A
@RW4+disp8, RW4
XORW
A
@RW3+disp8, RW3
XORW
A
@RW2+disp8, RW2
XORW
A
@RW1+disp8, RW1
XORW
A
@RW0+disp8, RW0
XORW
D0
NOTW
addr16
@PC+disp16
NOTW
@RW1+RW7
NOTW
@RW0+RW7
NOTW
@RW3+disp16
NOTW
@RW2+disp16
NOTW
@RW1+disp16
NOTW
@RW0+disp16
NOTW
@RW7+disp8
NOTW
@RW6+disp8
NOTW
@RW5+disp8
NOTW
@RW4+disp8
NOTW
@RW3+disp8
NOTW
@RW2+disp8
NOTW
@RW1+disp8
NOTW
@RW0+disp8
NOTW
F0
F MC-16FX Family
+A @RW2,
ADDW
A
+9 @RW1,
ADDW
A
+8 @RW0,
ADDW
A
SUBCW
@RW7+disp8, A,
SUBW
@RW7+disp8, RW7,
SUBW
ADDW
ADDW
+7 RW7,
RW6
A
A
A
A
SUBCW
@RW6+disp8, A,
SUBW
@RW6+disp8, RW6,
SUBW
ADDW
ADDW
+6 RW6,
RW5
A
A
A
A
SUBCW
@RW5+disp8, A,
SUBW
@RW5+disp8, RW5,
SUBW
ADDW
ADDW
+5 RW5,
RW4
A
A
A
SUBCW
@RW4+disp8, A,
A
SUBW
@RW4+disp8, RW4,
SUBW
ADDW
ADDW
+4 RW4,
RW3
A
A
A
A
SUBCW
@RW3+disp8, A,
SUBW
@RW3+disp8, RW3,
SUBW
ADDW
ADDW
+3 RW3,
RW2
A
A
A
A
SUBCW
@RW2+disp8, A,
SUBW
@RW2+disp8, RW2,
SUBW
ADDW
ADDW
+2 RW2,
RW1
A
A
A
A
SUBCW
@RW1+disp8, A,
SUBW
@RW1+disp8, RW1,
SUBW
ADDW
ADDW
+1 RW1,
A
RW0
A
A
40
SUBCW
@RW0+disp8, A,
SUBW
30
A
SUBW
20
@RW0+disp8, RW0,
+0 RW0,
10
00
2
APPENDIX
APPENDIX C Instruction Maps
Table C.6-8 ea-type Instruction (8) (First Byte = 77H)
356
MULU
A,
R0
MULU
MULU
A,
MULUW
A,
@RW3+disp8 RW3
MULU
A,
MULU
A,
MULU
+3 A,
R3
MULU
+4 A,
R4
MULU
MULU
A,
MULUW
A,
@RW7+disp8 RW7
MULU
A,
MULU
A,
MULU
+7 A,
R7
MULU
+8 A,
@RW0
MULU
FUJITSU MICROELECTRONICS LIMITED
MULU
A,
MULUW
A,
@RW3+disp16 @RW3
MULU
A,
MULU
+B A,
@RW3
MULU
+C A,
@RW0+
@RW1+RW7
@RW1+
@PC+disp16
MULU
A,
addr16
MULU
+E A,
@RW2+
MULU
+F A,
@RW3+
MULU
A,
MULU
A,
+D A,
MULU
@RW0+RW7
MULUW
A,
@RW2+disp16 @RW2
MULUW
A,
@RW3+
MULUW
A,
@RW2+
MULUW
A,
@RW1+
MULUW
A,
@RW0+
MULU
A,
MULUW
A,
@RW1+disp16 @RW1
MULU
+A A,
@RW2
@RW1
+9 A,
MULUW
A,
@RW6+disp8 RW6
MULUW
A,
@RW0+disp16 @RW0
MULU
A,
MULUW
A,
@RW5+disp8 RW5
MULU
+6 A,
R6
R5
+5 A,
MULUW
A,
@RW2+disp8 RW2
MULUW
A,
@RW4+disp8 RW4
MULU
A,
MULU
+2 A,
R2
R1
+1 A,
MULUW
A,
RW0
20
MULUW
A,
@RW1+disp8 RW1
MULU
A,
@RW0+disp8
+0 A,
MULU
10
00
MUL
A,
R0
40
MULUW
A,
addr16
@PC+disp16
MULUW
A,
@RW1+RW7
MULUW
A,
@RW0+RW7
MULUW
A,
MUL
A,
@RW3+
MUL
A,
@RW2+
MUL
A,
@RW1+
MUL
A,
@RW0+
MUL
A,
@RW3+disp16 @RW3
MULUW
A,
MUL
A,
@RW2+disp16 @RW2
MULUW
A,
MUL
A,
@RW1+disp16 @RW1
MULUW
A,
MUL
A,
@RW0+disp16 @RW0
MULUW
A,
MUL
A,
@RW7+disp8 R7
MULUW
A,
MUL
A,
@RW6+disp8 R6
MULUW
A,
MUL
A,
@RW5+disp8 R5
MULUW
A,
MUL
A,
@RW4+disp8 R4
MULUW
A,
MUL
A,
@RW3+disp8 R3
MULUW
A,
MUL
A,
@RW2+disp8 R2
MULUW
A,
MUL
A,
@RW1+disp8 R1
MULUW
A,
@RW0+disp8
MULUW
A,
30
MULW
A,
RW0
60
MUL
A,
addr16
@PC+disp16
MUL
A,
@RW1+RW7
MUL
A,
@RW0+RW7
MUL
A,
MULW
A,
@RW3+
MULW
A,
@RW2+
MULW
A,
@RW1+
MULW
A,
@RW0+
MULW
A,
@RW3+disp16 @RW3
MUL
A,
MULW
A,
@RW2+disp16 @RW2
MUL
A,
MULW
A,
@RW1+disp16 @RW1
MUL
A,
MULW
A,
@RW0+disp16 @RW0
MUL
A,
MULW
A,
@RW7+disp8 RW7
MUL
A,
MULW
A,
@RW6+disp8 RW6
MUL
A,
MULW
A,
@RW5+disp8 RW5
MUL
A,
MULW
A,
@RW4+disp8 RW4
MUL
A,
MULW
A,
@RW3+disp8 RW3
MUL
A,
MULW
A,
@RW2+disp8 RW2
MUL
A,
MULW
A,
@RW1+disp8 RW1
MUL
A,
@RW0+disp8
MUL
A,
50
DIVU
A,
R0
80
MULW
A,
addr16
@PC+disp16
MULW
A,
@RW1+RW7
MULW
A,
@RW0+RW7
MULW
A,
DIVU
A,
@RW3+
DIVU
A,
@RW2+
DIVU
A,
@RW1+
DIVU
A,
@RW0+
DIVU
A,
@RW3+disp16 @RW3
MULW
A,
DIVU
A,
@RW2+disp16 @RW2
MULW
A,
DIVU
A,
@RW1+disp16 @RW1
MULW
A,
DIVU
A,
@RW0+disp16 @RW0
MULW
A,
DIVU
A,
@RW7+disp8 R7
MULW
A,
DIVU
A,
@RW6+disp8 R6
MULW
A,
DIVU
A,
@RW5+disp8 R5
MULW
A,
DIVU
A,
@RW4+disp8 R4
MULW
A,
DIVU
A,
@RW3+disp8 R3
MULW
A,
DIVU
A,
@RW2+disp8 R2
MULW
A,
DIVU
A,
@RW1+disp8 R1
MULW
A,
@RW0+disp8
MULW
A,
70
DIVUW
A,
RW0
A0
DIVU
A,
addr16
@PC+disp16
DIVU
A,
@RW1+RW7
DIVU
A,
@RW0+RW7
DIVU
A,
DIVUW
A,
@RW3+
DIVUW
A,
@RW2+
DIVUW
A,
@RW1+
DIVUW
A,
@RW0+
DIVUW
A,
@RW3+disp16 @RW3
DIVU
A,
DIVUW
A,
@RW2+disp16 @RW2
DIVU
A,
DIVUW
A,
@RW1+disp16 @RW1
DIVU
A,
DIVUW
A,
@RW0+disp16 @RW0
DIVU
A,
DIVUW
A,
@RW7+disp8 RW7
DIVU
A,
DIVUW
A,
@RW6+disp8 RW6
DIVU
A,
DIVUW
A,
@RW5+disp8 RW5
DIVU
A,
DIVUW
A,
@RW4+disp8 RW4
DIVU
A,
DIVUW
A,
@RW3+disp8 RW3
DIVU
A,
DIVUW
A,
@RW2+disp8 RW2
DIVU
A,
DIVUW
A,
@RW1+disp8 RW1
DIVU
A,
@RW0+disp8
DIVU
A,
90
DIV
A,
R0
C0
DIVUW
A,
addr16
@PC+disp16
DIVUW
A,
@RW1+RW7
DIVUW
A,
@RW0+RW7
DIVUW
A,
DIV
A,
@RW3+
DIV
A,
@RW2+
DIV
A,
@RW1+
DIV
A,
@RW0+
DIV
A,
@RW3+disp16 @RW3
DIVUW
A,
DIV
A,
@RW2+disp16 @RW2
DIVUW
A,
DIV
A,
@RW1+disp16 @RW1
DIVUW
A,
DIV
A,
@RW0+disp16 @RW0
DIVUW
A,
DIV
A,
@RW7+disp8 R7
DIVUW
A,
DIV
A,
@RW6+disp8 R6
DIVUW
A,
DIV
A,
@RW5+disp8 R5
DIVUW
A,
DIV
A,
@RW4+disp8 R4
DIVUW
A,
DIV
A,
@RW3+disp8 R3
DIVUW
A,
DIV
A,
@RW2+disp8 R2
DIVUW
A,
DIV
A,
@RW1+disp8 R1
DIVUW
A,
@RW0+disp8
DIVUW
A,
B0
DIV
A,
DIVW
A,
RW0
E0
DIV
A,
addr16
@PC+disp16
DIV
A,
@RW1+RW7
DIV
A,
@RW0+RW7
DIV
A,
DIVW
A,
@RW3+
DIVW
A,
@RW2+
DIVW
A,
@RW1+
DIVW
A,
@RW0+
DIVW
A,
@RW3+disp16 @RW3
DIV
A,
DIVW
A,
@RW2+disp16 @RW2
DIV
A,
DIVW
A,
@RW1+disp16 @RW1
DIV
A,
DIVW
A,
@RW0+disp16 @RW0
DIV
A,
DIVW
A,
@RW7+disp8 RW7
DIV
A,
DIVW
A,
@RW6+disp8 RW6
DIV
A,
DIVW
A,
@RW5+disp8 RW5
DIV
A,
DIVW
A,
@RW4+disp8 RW4
DIV
A,
DIVW
A,
@RW3+disp8 RW3
DIV
A,
DIVW
A,
@RW2+disp8 RW2
DIV
A,
DIVW
A,
@RW1+disp8 RW1
DIV
A,
@RW0+disp8
D0
DIVW
A,
addr16
@PC+disp16
DIVW
A,
@RW1+RW7
DIVW
A,
@RW0+RW7
DIVW
A,
@RW3+disp16
DIVW
A,
@RW2+disp16
DIVW
A,
@RW1+disp16
DIVW
A,
@RW0+disp16
DIVW
A,
@RW7+disp8
DIVW
A,
@RW6+disp8
DIVW
A,
@RW5+disp8
DIVW
A,
@RW4+disp8
DIVW
A,
@RW3+disp8
DIVW
A,
@RW2+disp8
DIVW
A,
@RW1+disp8
DIVW
A,
@RW0+disp8
DIVW
A,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.6-9 ea-type Instruction (9) (First Byte = 78H)
CM44-00203-3E
2
F MC-16FX Family
C.7 MOVEA RWi, ea Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.7-1 lists MOVEA RWi, ea instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
357
358
MOVEA
RW0,
RW0
MOVEA
MOVEA
RW0,
MOVEA
RW1,
@RW3+disp8 RW3
MOVEA
RW0,
MOVEA
RW0,
MOVEA
+3 RW0,
RW3
MOVEA
+4 RW0,
RW4
MOVEA
MOVEA
RW0,
MOVEA
RW1,
@RW7+disp8 RW7
MOVEA
RW0,
MOVEA
RW0,
MOVEA
+7 RW0,
RW7
MOVEA
+8 RW0,
@RW0
MOVEA
FUJITSU MICROELECTRONICS LIMITED
MOVEA
RW0,
MOVEA
RW1,
@RW3+disp16 @RW3
MOVEA
RW0,
MOVEA
+B RW0,
@RW3
MOVEA
+C RW0,
@RW0+
@RW1+RW7
@RW1+
@PC+disp16
MOVEA
RW0,
addr16
MOVEA
+E RW0,
@RW2+
MOVEA
+F RW0,
@RW3+
MOVEA
RW0,
MOVEA
RW0,
+D RW0,
MOVEA
@RW0+RW7
MOVEA
RW1,
@RW2+disp16 @RW2
MOVEA
RW1,
@RW3+
MOVEA
RW1,
@RW2+
MOVEA
RW1,
@RW1+
MOVEA
RW1,
@RW0+
MOVEA
RW0,
MOVEA
RW1,
@RW1+disp16 @RW1
MOVEA
+A RW0,
@RW2
@RW1
+9 RW0,
MOVEA
RW1,
@RW6+disp8 RW6
MOVEA
RW1,
@RW0+disp16 @RW0
MOVEA
RW0,
MOVEA
RW1,
@RW5+disp8 RW5
MOVEA
+6 RW0,
RW6
RW5
+5 RW0,
MOVEA
RW1,
@RW2+disp8 RW2
MOVEA
RW1,
@RW4+disp8 RW4
MOVEA
RW0,
MOVEA
+2 RW0,
RW2
RW1
+1 RW0,
MOVEA
RW1,
RW0
20
MOVEA
RW1,
@RW1+disp8 RW1
MOVEA
RW0,
@RW0+disp8
+0 RW0,
MOVEA
10
00
MOVEA
RW2,
RW0
40
MOVEA
RW1,
addr16
@PC+disp16
MOVEA
RW1,
@RW1+RW7
MOVEA
RW1,
@RW0+RW7
MOVEA
RW1,
MOVEA
RW2,
@RW3+
MOVEA
RW2,
@RW2+
MOVEA
RW2,
@RW1+
MOVEA
RW2,
@RW0+
MOVEA
RW2,
@RW3+disp16 @RW3
MOVEA
RW1,
MOVEA
RW2,
@RW2+disp16 @RW2
MOVEA
RW1,
MOVEA
RW2,
@RW1+disp16 @RW1
MOVEA
RW1,
MOVEA
RW2,
@RW0+disp16 @RW0
MOVEA
RW1,
MOVEA
RW2,
@RW7+disp8 RW7
MOVEA
RW1,
MOVEA
RW2,
@RW6+disp8 RW6
MOVEA
RW1,
MOVEA
RW2,
@RW5+disp8 RW5
MOVEA
RW1,
MOVEA
RW2,
@RW4+disp8 RW4
MOVEA
RW1,
MOVEA
RW2,
@RW3+disp8 RW3
MOVEA
RW1,
MOVEA
RW2,
@RW2+disp8 RW2
MOVEA
RW1,
MOVEA
RW2,
@RW1+disp8 RW1
MOVEA
RW1,
@RW0+disp8
MOVEA
RW1,
30
MOVEA
RW3,
RW0
60
MOVEA
RW2,
addr16
@PC+disp16
MOVEA
RW2,
@RW1+RW7
MOVEA
RW2,
@RW0+RW7
MOVEA
RW2,
MOVEA
RW3,
@RW3+
MOVEA
RW3,
@RW2+
MOVEA
RW3,
@RW1+
MOVEA
RW3,
@RW0+
MOVEA
RW3,
@RW3+disp16 @RW3
MOVEA
RW2,
MOVEA
RW3,
@RW2+disp16 @RW2
MOVEA
RW2,
MOVEA
RW3,
@RW1+disp16 @RW1
MOVEA
RW2,
MOVEA
RW3,
@RW0+disp16 @RW0
MOVEA
RW2,
MOVEA
RW3,
@RW7+disp8 RW7
MOVEA
RW2,
MOVEA
RW3,
@RW6+disp8 RW6
MOVEA
RW2,
MOVEA
RW3,
@RW5+disp8 RW5
MOVEA
RW2,
MOVEA
RW3,
@RW4+disp8 RW4
MOVEA
RW2,
MOVEA
RW3,
@RW3+disp8 RW3
MOVEA
RW2,
MOVEA
RW3,
@RW2+disp8 RW2
MOVEA
RW2,
MOVEA
RW3,
@RW1+disp8 RW1
MOVEA
RW2,
@RW0+disp8
MOVEA
RW2,
50
MOVEA
RW4,
RW0
80
MOVEA
RW3,
addr16
@PC+disp16
MOVEA
RW3,
@RW1+RW7
MOVEA
RW3,
@RW0+RW7
MOVEA
RW3,
MOVEA
RW4,
@RW3+
MOVEA
RW4,
@RW2+
MOVEA
RW4,
@RW1+
MOVEA
RW4,
@RW0+
MOVEA
RW4,
@RW3+disp16 @RW3
MOVEA
RW3,
MOVEA
RW4,
@RW2+disp16 @RW2
MOVEA
RW3,
MOVEA
RW4,
@RW1+disp16 @RW1
MOVEA
RW3,
MOVEA
RW4,
@RW0+disp16 @RW0
MOVEA
RW3,
MOVEA
RW4,
@RW7+disp8 RW7
MOVEA
RW3,
MOVEA
RW4,
@RW6+disp8 RW6
MOVEA
RW3,
MOVEA
RW4,
@RW5+disp8 RW5
MOVEA
RW3,
MOVEA
RW4,
@RW4+disp8 RW4
MOVEA
RW3,
MOVEA
RW4,
@RW3+disp8 RW3
MOVEA
RW3,
MOVEA
RW4,
@RW2+disp8 RW2
MOVEA
RW3,
MOVEA
RW4,
@RW1+disp8 RW1
MOVEA
RW3,
@RW0+disp8
MOVEA
RW3,
70
MOVEA
RW5,
RW0
A0
MOVEA
RW4,
addr16
@PC+disp16
MOVEA
RW4,
@RW1+RW7
MOVEA
RW4,
@RW0+RW7
MOVEA
RW4,
MOVEA
RW5,
@RW3+
MOVEA
RW5,
@RW2+
MOVEA
RW5,
@RW1+
MOVEA
RW5,
@RW0+
MOVEA
RW5,
@RW3+disp16 @RW3
MOVEA
RW4,
MOVEA
RW5,
@RW2+disp16 @RW2
MOVEA
RW4,
MOVEA
RW5,
@RW1+disp16 @RW1
MOVEA
RW4,
MOVEA
RW5,
@RW0+disp16 @RW0
MOVEA
RW4,
MOVEA
RW5,
@RW7+disp8 RW7
MOVEA
RW4,
MOVEA
RW5,
@RW6+disp8 RW6
MOVEA
RW4,
MOVEA
RW5,
@RW5+disp8 RW5
MOVEA
RW4,
MOVEA
RW5,
@RW4+disp8 RW4
MOVEA
RW4,
MOVEA
RW5,
@RW3+disp8 RW3
MOVEA
RW4,
MOVEA
RW5,
@RW2+disp8 RW2
MOVEA
RW4,
MOVEA
RW5,
@RW1+disp8 RW1
MOVEA
RW4,
@RW0+disp8
MOVEA
RW4,
90
MOVEA
RW6,
RW0
C0
MOVEA
RW5,
addr16
@PC+disp16
MOVEA
RW5,
@RW1+RW7
MOVEA
RW5,
@RW0+RW7
MOVEA
RW5,
MOVEA
RW6,
@RW3+
MOVEA
RW6,
@RW2+
MOVEA
RW6,
@RW1+
MOVEA
RW6,
@RW0+
MOVEA
RW6,
@RW3+disp16 @RW3
MOVEA
RW5,
MOVEA
RW6,
@RW2+disp16 @RW2
MOVEA
RW5,
MOVEA
RW6,
@RW1+disp16 @RW1
MOVEA
RW5,
MOVEA
RW6,
@RW0+disp16 @RW0
MOVEA
RW5,
MOVEA
RW6,
@RW7+disp8 RW7
MOVEA
RW5,
MOVEA
RW6,
@RW6+disp8 RW6
MOVEA
RW5,
MOVEA
RW6,
@RW5+disp8 RW5
MOVEA
RW5,
MOVEA
RW6,
@RW4+disp8 RW4
MOVEA
RW5,
MOVEA
RW6,
@RW3+disp8 RW3
MOVEA
RW5,
MOVEA
RW6,
@RW2+disp8 RW2
MOVEA
RW5,
MOVEA
RW6,
@RW1+disp8 RW1
MOVEA
RW5,
@RW0+disp8
MOVEA
RW5,
B0
MOVEA
RW7,
RW0
E0
MOVEA
RW6,
addr16
@PC+disp16
MOVEA
RW6,
@RW1+RW7
MOVEA
RW6,
@RW0+RW7
MOVEA
RW6,
MOVEA
RW7,
@RW3+
MOVEA
RW7,
@RW2+
MOVEA
RW7,
@RW1+
MOVEA
RW7,
@RW0+
MOVEA
RW7,
@RW3+disp16 @RW3
MOVEA
RW6,
MOVEA
RW7,
@RW2+disp16 @RW2
MOVEA
RW6,
MOVEA
RW7,
@RW1+disp16 @RW1
MOVEA
RW6,
MOVEA
RW7,
@RW0+disp16 @RW0
MOVEA
RW6,
MOVEA
RW7,
@RW7+disp8 RW7
MOVEA
RW6,
MOVEA
RW7,
@RW6+disp8 RW6
MOVEA
RW6,
MOVEA
RW7,
@RW5+disp8 RW5
MOVEA
RW6,
MOVEA
RW7,
@RW4+disp8 RW4
MOVEA
RW6,
MOVEA
RW7,
@RW3+disp8 RW3
MOVEA
RW6,
MOVEA
RW7,
@RW2+disp8 RW2
MOVEA
RW6,
MOVEA
RW7,
@RW1+disp8 RW1
MOVEA
RW6,
@RW0+disp8
MOVEA
RW6,
D0
MOVEA
RW7,
addr16
@PC+disp16
MOVEA
RW7,
@RW1+RW7
MOVEA
RW7,
@RW0+RW7
MOVEA
RW7,
@RW3+disp16
MOVEA
RW7,
@RW2+disp16
MOVEA
RW7,
@RW1+disp16
MOVEA
RW7,
@RW0+disp16
MOVEA
RW7,
@RW7+disp8
MOVEA
RW7,
@RW6+disp8
MOVEA
RW7,
@RW5+disp8
MOVEA
RW7,
@RW4+disp8
MOVEA
RW7,
@RW3+disp8
MOVEA
RW7,
@RW2+disp8
MOVEA
RW7,
@RW1+disp8
MOVEA
RW7,
@RW0+disp8
MOVEA
RW7,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.7-1 MOVEA RWi, ea Instruction (First Byte = 79H)
CM44-00203-3E
2
F MC-16FX Family
C.8 MOV Ri, ea Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.8-1 lists MOV Ri, ea instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
359
360
MOV
R0,
R0
MOV
MOV
R0,
MOV
R1,
@RW3+disp8 R3
MOV
R0,
MOV
R0,
MOV
+3 R0,
R3
MOV
+4 R0,
R4
MOV
MOV
R0,
MOV
R1,
@RW7+disp8 R7
MOV
R0,
MOV
+7 R0,
R7
MOV
+8 R0,
@RW0
FUJITSU MICROELECTRONICS LIMITED
MOV
R0,
MOV
R1,
@RW3+disp16 @RW3
MOV
R0,
MOV
+B R0,
@RW3
MOV
+C R0,
@RW0+
@RW1+RW7
@RW1+
@PC+disp16
MOV
R0,
addr16
MOV
+E R0,
@RW2+
MOV
+F R0,
@RW3+
MOV
R0,
MOV
R0,
+D R0,
MOV
@RW0+RW7
MOV
R1,
@RW2+disp16 @RW2
MOV
R1,
@RW3+
MOV
R1,
@RW2+
MOV
R1,
@RW1+
MOV
R1,
@RW0+
MOV
R0,
MOV
R1,
@RW1+disp16 @RW1
MOV
R0,
MOV
+A R0,
@RW2
@RW1
+9 R0,
MOV
MOV
R1,
@RW6+disp8 R6
MOV
R1,
@RW0+disp16 @RW0
MOV
R0,
MOV
R1,
@RW5+disp8 R5
MOV
+6 R0,
R6
R5
+5 R0,
MOV
R1,
@RW2+disp8 R2
MOV
R1,
@RW4+disp8 R4
MOV
R0,
MOV
+2 R0,
R2
R1
+1 R0,
MOV
R1,
R0
20
MOV
R1,
@RW1+disp8 R1
MOV
R0,
+0 R0,
@RW0+disp8
10
MOV
00
MOV
R2,
R0
40
MOV
R1,
addr16
@PC+disp16
MOV
R1,
@RW1+RW7
MOV
R1,
@RW0+RW7
MOV
R1,
MOV
R2,
@RW3+
MOV
R2,
@RW2+
MOV
R2,
@RW1+
MOV
R2,
@RW0+
MOV
R2,
@RW3+disp16 @RW3
MOV
R1,
MOV
R2,
@RW2+disp16 @RW2
MOV
R1,
MOV
R2,
@RW1+disp16 @RW1
MOV
R1,
MOV
R2,
@RW0+disp16 @RW0
MOV
R1,
MOV
R2,
@RW7+disp8 R7
MOV
R1,
MOV
R2,
@RW6+disp8 R6
MOV
R1,
MOV
R2,
@RW5+disp8 R5
MOV
R1,
MOV
R2,
@RW4+disp8 R4
MOV
R1,
MOV
R2,
@RW3+disp8 R3
MOV
R1,
MOV
R2,
@RW2+disp8 R2
MOV
R1,
MOV
R2,
@RW1+disp8 R1
MOV
R1,
@RW0+disp8
MOV
R1,
30
MOV
R3,
R0
60
MOV
R2,
addr16
@PC+disp16
MOV
R2,
@RW1+RW7
MOV
R2,
@RW0+RW7
MOV
R2,
MOV
R3,
@RW3+
MOV
R3,
@RW2+
MOV
R3,
@RW1+
MOV
R3,
@RW0+
MOV
R3,
@RW3+disp16 @RW3
MOV
R2,
MOV
R3,
@RW2+disp16 @RW2
MOV
R2,
MOV
R3,
@RW1+disp16 @RW1
MOV
R2,
MOV
R3,
@RW0+disp16 @RW0
MOV
R2,
MOV
R3,
@RW7+disp8 R7
MOV
R2,
MOV
R3,
@RW6+disp8 R6
MOV
R2,
MOV
R3,
@RW5+disp8 R5
MOV
R2,
MOV
R3,
@RW4+disp8 R4
MOV
R2,
MOV
R3,
@RW3+disp8 R3
MOV
R2,
MOV
R3,
@RW2+disp8 R2
MOV
R2,
MOV
R3,
@RW1+disp8 R1
MOV
R2,
@RW0+disp8
MOV
R2,
50
MOV
R4,
R0
80
MOV
R3,
addr16
@PC+disp16
MOV
R3,
@RW1+RW7
MOV
R3,
@RW0+RW7
MOV
R3,
MOV
R4,
@RW3+
MOV
R4,
@RW2+
MOV
R4,
@RW1+
MOV
R4,
@RW0+
MOV
R4,
@RW3+disp16 @RW3
MOV
R3,
MOV
R4,
@RW2+disp16 @RW2
MOV
R3,
MOV
R4,
@RW1+disp16 @RW1
MOV
R3,
MOV
R4,
@RW0+disp16 @RW0
MOV
R3,
MOV
R4,
@RW7+disp8 R7
MOV
R3,
MOV
R4,
@RW6+disp8 R6
MOV
R3,
MOV
R4,
@RW5+disp8 R5
MOV
R3,
MOV
R4,
@RW4+disp8 R4
MOV
R3,
MOV
R4,
@RW3+disp8 R3
MOV
R3,
MOV
R4,
@RW2+disp8 R2
MOV
R3,
MOV
R4,
@RW1+disp8 R1
MOV
R3,
@RW0+disp8
MOV
R3,
70
MOV
R5,
R0
A0
MOV
R4,
addr16
@PC+disp16
MOV
R4,
@RW1+RW7
MOV
R4,
@RW0+RW7
MOV
R4,
MOV
R5,
@RW3+
MOV
R5,
@RW2+
MOV
R5,
@RW1+
MOV
R5,
@RW0+
MOV
R5,
@RW3+disp16 @RW3
MOV
R4,
MOV
R5,
@RW2+disp16 @RW2
MOV
R4,
MOV
R5,
@RW1+disp16 @RW1
MOV
R4,
MOV
R5,
@RW0+disp16 @RW0
MOV
R4,
MOV
R5,
@RW7+disp8 R7
MOV
R4,
MOV
R5,
@RW6+disp8 R6
MOV
R4,
MOV
R5,
@RW5+disp8 R5
MOV
R4,
MOV
R5,
@RW4+disp8 R4
MOV
R4,
MOV
R5,
@RW3+disp8 R3
MOV
R4,
MOV
R5,
@RW2+disp8 R2
MOV
R4,
MOV
R5,
@RW1+disp8 R1
MOV
R4,
@RW0+disp8
MOV
R4,
90
MOV
R6,
R0
C0
MOV
R5,
addr16
@PC+disp16
MOV
R5,
@RW1+RW7
MOV
R5,
@RW0+RW7
MOV
R5,
MOV
R6,
@RW3+
MOV
R6,
@RW2+
MOV
R6,
@RW1+
MOV
R6,
@RW0+
MOV
R6,
@RW3+disp16 @RW3
MOV
R5,
MOV
R6,
@RW2+disp16 @RW2
MOV
R5,
MOV
R6,
@RW1+disp16 @RW1
MOV
R5,
MOV
R6,
@RW0+disp16 @RW0
MOV
R5,
MOV
R6,
@RW7+disp8 R7
MOV
R5,
MOV
R6,
@RW6+disp8 R6
MOV
R5,
MOV
R6,
@RW5+disp8 R5
MOV
R5,
MOV
R6,
@RW4+disp8 R4
MOV
R5,
MOV
R6,
@RW3+disp8 R3
MOV
R5,
MOV
R6,
@RW2+disp8 R2
MOV
R5,
MOV
R6,
@RW1+disp8 R1
MOV
R5,
@RW0+disp8
MOV
R5,
B0
MOV
R7,
R0
E0
MOV
R6,
addr16
@PC+disp16
MOV
R6,
@RW1+RW7
MOV
R6,
@RW0+RW7
MOV
R6,
MOV
R7,
@RW3+
MOV
R7,
@RW2+
MOV
R7,
@RW1+
MOV
R7,
@RW0+
MOV
R7,
@RW3+disp16 @RW3
MOV
R6,
MOV
R7,
@RW2+disp16 @RW2
MOV
R6,
MOV
R7,
@RW1+disp16 @RW1
MOV
R6,
MOV
R7,
@RW0+disp16 @RW0
MOV
R6,
MOV
R7,
@RW7+disp8 R7
MOV
R6,
MOV
R7,
@RW6+disp8 R6
MOV
R6,
MOV
R7,
@RW5+disp8 R5
MOV
R6,
MOV
R7,
@RW4+disp8 R4
MOV
R6,
MOV
R7,
@RW3+disp8 R3
MOV
R6,
MOV
R7,
@RW2+disp8 R2
MOV
R6,
MOV
R7,
@RW1+disp8 R1
MOV
R6,
@RW0+disp8
MOV
R6,
D0
MOV
R7,
addr16
@PC+disp16
MOV
R7,
@RW1+RW7
MOV
R7,
@RW0+RW7
MOV
R7,
@RW3+disp16
MOV
R7,
@RW2+disp16
MOV
R7,
@RW1+disp16
MOV
R7,
@RW0+disp16
MOV
R7,
@RW7+disp8
MOV
R7,
@RW6+disp8
MOV
R7,
@RW5+disp8
MOV
R7,
@RW4+disp8
MOV
R7,
@RW3+disp8
MOV
R7,
@RW2+disp8
MOV
R7,
@RW1+disp8
MOV
R7,
@RW0+disp8
MOV
R7,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.8-1 MOV Ri, ea Instruction (First Byte = 7AH)
CM44-00203-3E
2
F MC-16FX Family
C.9 MOVW RWi, ea Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.9-1 lists MOVW RWi, ea instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
361
362
MOVW
RW0,
RW0
MOVW
MOVW
RW0,
MOVW
RW1,
@RW3+disp8 RW3
MOVW
RW0,
MOVW
RW0,
MOVW
+3 RW0,
RW3
MOVW
+4 RW0,
RW4
MOVW
MOVW
RW0,
MOVW
RW1,
@RW7+disp8 RW7
MOVW
RW0,
MOVW
RW0,
MOVW
+7 RW0,
RW7
MOVW
+8 RW0,
@RW0
MOVW
FUJITSU MICROELECTRONICS LIMITED
MOVW
RW0,
MOVW
RW1,
@RW3+disp16 @RW3
MOVW
RW0,
MOVW
+B RW0,
@RW3
MOVW
+C RW0,
@RW0+
@RW1+RW7
@RW1+
@PC+disp16
MOVW
RW0,
addr16
MOVW
+E RW0,
@RW2+
MOVW
+F RW0,
@RW3+
MOVW
RW0,
MOVW
RW0,
+D RW0,
MOVW
@RW0+RW7
MOVW
RW1,
@RW2+disp16 @RW2
MOVW
RW1,
@RW3+
MOVW
RW1,
@RW2+
MOVW
RW1,
@RW1+
MOVW
RW1,
@RW0+
MOVW
RW0,
MOVW
RW1,
@RW1+disp16 @RW1
MOVW
+A RW0,
@RW2
@RW1
+9 RW0,
MOVW
RW1,
@RW6+disp8 RW6
MOVW
RW1,
@RW0+disp16 @RW0
MOVW
RW0,
MOVW
RW1,
@RW5+disp8 RW5
MOVW
+6 RW0,
RW6
RW5
+5 RW0,
MOVW
RW1,
@RW2+disp8 RW2
MOVW
RW1,
@RW4+disp8 RW4
MOVW
RW0,
MOVW
+2 RW0,
RW2
RW1
+1 RW0,
MOVW
RW1,
RW0
20
MOVW
RW1,
@RW1+disp8 RW1
MOVW
RW0,
@RW0+disp8
+0 RW0,
MOVW
10
00
MOVW
RW2,
RW0
40
MOVW
RW1,
addr16
@PC+disp16
MOVW
RW1,
@RW1+RW7
MOVW
RW1,
@RW0+RW7
MOVW
RW1,
MOVW
RW2,
@RW3+
MOVW
RW2,
@RW2+
MOVW
RW2,
@RW1+
MOVW
RW2,
@RW0+
MOVW
RW2,
@RW3+disp16 @RW3
MOVW
RW1,
MOVW
RW2,
@RW2+disp16 @RW2
MOVW
RW1,
MOVW
RW2,
@RW1+disp16 @RW1
MOVW
RW1,
MOVW
RW2,
@RW0+disp16 @RW0
MOVW
RW1,
MOVW
RW2,
@RW7+disp8 RW7
MOVW
RW1,
MOVW
RW2,
@RW6+disp8 RW6
MOVW
RW1,
MOVW
RW2,
@RW5+disp8 RW5
MOVW
RW1,
MOVW
RW2,
@RW4+disp8 RW4
MOVW
RW1,
MOVW
RW2,
@RW3+disp8 RW3
MOVW
RW1,
MOVW
RW2,
@RW2+disp8 RW2
MOVW
RW1,
MOVW
RW2,
@RW1+disp8 RW1
MOVW
RW1,
@RW0+disp8
MOVW
RW1,
30
MOVW
RW3,
RW0
60
MOVW
RW2,
addr16
@PC+disp16
MOVW
RW2,
@RW1+RW7
MOVW
RW2,
@RW0+RW7
MOVW
RW2,
MOVW
RW3,
@RW3+
MOVW
RW3,
@RW2+
MOVW
RW3,
@RW1+
MOVW
RW3,
@RW0+
MOVW
RW3,
@RW3+disp16 @RW3
MOVW
RW2,
MOVW
RW3,
@RW2+disp16 @RW2
MOVW
RW2,
MOVW
RW3,
@RW1+disp16 @RW1
MOVW
RW2,
MOVW
RW3,
@RW0+disp16 @RW0
MOVW
RW2,
MOVW
RW3,
@RW7+disp8 RW7
MOVW
RW2,
MOVW
RW3,
@RW6+disp8 RW6
MOVW
RW2,
MOVW
RW3,
@RW5+disp8 RW5
MOVW
RW2,
MOVW
RW3,
@RW4+disp8 RW4
MOVW
RW2,
MOVW
RW3,
@RW3+disp8 RW3
MOVW
RW2,
MOVW
RW3,
@RW2+disp8 RW2
MOVW
RW2,
MOVW
RW3,
@RW1+disp8 RW1
MOVW
RW2,
@RW0+disp8
MOVW
RW2,
50
MOVW
RW4,
RW0
80
MOVW
RW3,
addr16
@PC+disp16
MOVW
RW3,
@RW1+RW7
MOVW
RW3,
@RW0+RW7
MOVW
RW3,
MOVW
RW4,
@RW3+
MOVW
RW4,
@RW2+
MOVW
RW4,
@RW1+
MOVW
RW4,
@RW0+
MOVW
RW4,
@RW3+disp16 @RW3
MOVW
RW3,
MOVW
RW4,
@RW2+disp16 @RW2
MOVW
RW3,
MOVW
RW4,
@RW1+disp16 @RW1
MOVW
RW3,
MOVW
RW4,
@RW0+disp16 @RW0
MOVW
RW3,
MOVW
RW4,
@RW7+disp8 RW7
MOVW
RW3,
MOVW
RW4,
@RW6+disp8 RW6
MOVW
RW3,
MOVW
RW4,
@RW5+disp8 RW5
MOVW
RW3,
MOVW
RW4,
@RW4+disp8 RW4
MOVW
RW3,
MOVW
RW4,
@RW3+disp8 RW3
MOVW
RW3,
MOVW
RW4,
@RW2+disp8 RW2
MOVW
RW3,
MOVW
RW4,
@RW1+disp8 RW1
MOVW
RW3,
@RW0+disp8
MOVW
RW3,
70
MOVW
RW5,
RW0
A0
MOVW
RW4,
addr16
@PC+disp16
MOVW
RW4,
@RW1+RW7
MOVW
RW4,
@RW0+RW7
MOVW
RW4,
MOVW
RW5,
@RW3+
MOVW
RW5,
@RW2+
MOVW
RW5,
@RW1+
MOVW
RW5,
@RW0+
MOVW
RW5,
@RW3+disp16 @RW3
MOVW
RW4,
MOVW
RW5,
@RW2+disp16 @RW2
MOVW
RW4,
MOVW
RW5,
@RW1+disp16 @RW1
MOVW
RW4,
MOVW
RW5,
@RW0+disp16 @RW0
MOVW
RW4,
MOVW
RW5,
@RW7+disp8 RW7
MOVW
RW4,
MOVW
RW5,
@RW6+disp8 RW6
MOVW
RW4,
MOVW
RW5,
@RW5+disp8 RW5
MOVW
RW4,
MOVW
RW5,
@RW4+disp8 RW4
MOVW
RW4,
MOVW
RW5,
@RW3+disp8 RW3
MOVW
RW4,
MOVW
RW5,
@RW2+disp8 RW2
MOVW
RW4,
MOVW
RW5,
@RW1+disp8 RW1
MOVW
RW4,
@RW0+disp8
MOVW
RW4,
90
MOVW
RW6,
RW0
C0
MOVW
RW5,
addr16
@PC+disp16
MOVW
RW5,
@RW1+RW7
MOVW
RW5,
@RW0+RW7
MOVW
RW5,
MOVW
RW6,
@RW3+
MOVW
RW6,
@RW2+
MOVW
RW6,
@RW1+
MOVW
RW6,
@RW0+
MOVW
RW6,
@RW3+disp16 @RW3
MOVW
RW5,
MOVW
RW6,
@RW2+disp16 @RW2
MOVW
RW5,
MOVW
RW6,
@RW1+disp16 @RW1
MOVW
RW5,
MOVW
RW6,
@RW0+disp16 @RW0
MOVW
RW5,
MOVW
RW6,
@RW7+disp8 RW7
MOVW
RW5,
MOVW
RW6,
@RW6+disp8 RW6
MOVW
RW5,
MOVW
RW6,
@RW5+disp8 RW5
MOVW
RW5,
MOVW
RW6,
@RW4+disp8 RW4
MOVW
RW5,
MOVW
RW6,
@RW3+disp8 RW3
MOVW
RW5,
MOVW
RW6,
@RW2+disp8 RW2
MOVW
RW5,
MOVW
RW6,
@RW1+disp8 RW1
MOVW
RW5,
@RW0+disp8
MOVW
RW5,
B0
MOVW
RW7,
RW0
E0
MOVW
RW6,
addr16
@PC+disp16
MOVW
RW6,
@RW1+RW7
MOVW
RW6,
@RW0+RW7
MOVW
RW6,
MOVW
RW7,
@RW3+
MOVW
RW7,
@RW2+
MOVW
RW7,
@RW1+
MOVW
RW7,
@RW0+
MOVW
RW7,
@RW3+disp16 @RW3
MOVW
RW6,
MOVW
RW7,
@RW2+disp16 @RW2
MOVW
RW6,
MOVW
RW7,
@RW1+disp16 @RW1
MOVW
RW6,
MOVW
RW7,
@RW0+disp16 @RW0
MOVW
RW6,
MOVW
RW7,
@RW7+disp8 RW7
MOVW
RW6,
MOVW
RW7,
@RW6+disp8 RW6
MOVW
RW6,
MOVW
RW7,
@RW5+disp8 RW5
MOVW
RW6,
MOVW
RW7,
@RW4+disp8 RW4
MOVW
RW6,
MOVW
RW7,
@RW3+disp8 RW3
MOVW
RW6,
MOVW
RW7,
@RW2+disp8 RW2
MOVW
RW6,
MOVW
RW7,
@RW1+disp8 RW1
MOVW
RW6,
@RW0+disp8
MOVW
RW6,
D0
MOVW
RW7,
addr16
@PC+disp16
MOVW
RW7,
@RW1+RW7
MOVW
RW7,
@RW0+RW7
MOVW
RW7,
@RW3+disp16
MOVW
RW7,
@RW2+disp16
MOVW
RW7,
@RW1+disp16
MOVW
RW7,
@RW0+disp16
MOVW
RW7,
@RW7+disp8
MOVW
RW7,
@RW6+disp8
MOVW
RW7,
@RW5+disp8
MOVW
RW7,
@RW4+disp8
MOVW
RW7,
@RW3+disp8
MOVW
RW7,
@RW2+disp8
MOVW
RW7,
@RW1+disp8
MOVW
RW7,
@RW0+disp8
MOVW
RW7,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.9-1 MOVW RWi, ea Instruction (First Byte = 7BH)
CM44-00203-3E
2
F MC-16FX Family
C.10 MOV ea, Ri Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.10-1 lists MOV ea, Ri instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
363
364
FUJITSU MICROELECTRONICS LIMITED
MOV
@RW1+disp8, R1,
R0
R1
MOV
MOV
@RW2+disp8, R2,
R0
R1
MOV
MOV
@RW3+disp8, R3,
R0
R1
MOV
MOV
@RW4+disp8, R4,
R0
R1
MOV
MOV
@RW5+disp8, R5,
R0
R1
MOV
MOV
@RW6+disp8, R6,
R0
R1
MOV
MOV
@RW7+disp8, R7,
R0
R1
MOV
MOV
@RW0+disp16, @RW0,
R0
R1
MOV
MOV
@RW1+disp16, @RW1,
R0
R1
MOV
MOV
@RW2+disp16, @RW2,
R0
R1
MOV
MOV
@RW3+disp16, @RW3,
R0
R1
MOV
MOV
+2 R2,
R0
MOV
+3 R3,
R0
MOV
+4 R4,
R0
MOV
+5 R5,
R0
MOV
+6 R6,
R0
MOV
+7 R7,
R0
MOV
+8 @RW0,
R0
MOV
+9 @RW1,
R0
MOV
+A @RW2,
R0
MOV
+B @RW3,
R0
MOV
+C @RW0+,
R0
MOV
@RW1+RW7, @RW1+,
R0
R1
MOV
MOV
@PC+disp16, @RW2+,
R0
R1
MOV
addr16,
R0
MOV
+E @RW2+,
R0
MOV
+F @RW3+,
R0
MOV
@RW3+,
R1
MOV
MOV
+D @RW1+,
R0
MOV
@RW0+RW7, @RW0+,
R0
R1
MOV
MOV
addr16,
R1
MOV
@RW3+,
R2
MOV
@PC+disp16, @RW2+,
R1
R2
MOV
MOV
@RW1+RW7, @RW1+,
R1
R2
MOV
MOV
@RW0+RW7, @RW0+,
R1
R2
MOV
MOV
@RW3+disp16, @RW3,
R1
R2
MOV
MOV
@RW2+disp16, @RW2,
R1
R2
MOV
MOV
@RW1+disp16, @RW1,
R1
R2
MOV
MOV
@RW0+disp16, @RW0,
R1
R2
MOV
MOV
@RW7+disp8, R7,
R1
R2
MOV
MOV
@RW6+disp8, R6,
R1
R2
MOV
MOV
@RW5+disp8, R5,
R1
R2
MOV
MOV
@RW4+disp8, R4,
R1
R2
MOV
MOV
@RW3+disp8, R3,
R1
R2
MOV
MOV
@RW2+disp8, R2,
R1
R2
MOV
MOV
@RW1+disp8, R1,
R1
R2
MOV
R2
R1
R1
40
MOV
@RW0+disp8, R0,
MOV
30
R0
MOV
20
@RW0+disp8, R0,
MOV
10
MOV
+1 R1,
R0
R0
+0 R0,
MOV
00
MOV
60
R3
MOV
addr16,
R2
MOV
@RW3+,
R3
MOV
@PC+disp16, @RW2+,
R2
R3
MOV
MOV
@RW1+RW7, @RW1+,
R2
R3
MOV
MOV
@RW0+RW7, @RW0+,
R2
R3
MOV
MOV
@RW3+disp16, @RW3,
R2
R3
MOV
MOV
@RW2+disp16, @RW2,
R2
R3
MOV
MOV
@RW1+disp16, @RW1,
R2
R3
MOV
MOV
@RW0+disp16, @RW0,
R2
R3
MOV
MOV
@RW7+disp8, R7,
R2
R3
MOV
MOV
@RW6+disp8, R6,
R2
R3
MOV
MOV
@RW5+disp8, R5,
R2
R3
MOV
MOV
@RW4+disp8, R4,
R2
R3
MOV
MOV
@RW3+disp8, R3,
R2
R3
MOV
MOV
@RW2+disp8, R2,
R2
R3
MOV
MOV
@RW1+disp8, R1,
R2
R3
MOV
R2
@RW0+disp8, R0,
MOV
50
MOV
80
R4
MOV
addr16,
R3
MOV
@RW3+,
R4
MOV
@PC+disp16, @RW2+,
R3
R4
MOV
MOV
@RW1+RW7, @RW1+,
R3
R4
MOV
MOV
@RW0+RW7, @RW0+,
R3
R4
MOV
MOV
@RW3+disp16, @RW3,
R3
R4
MOV
MOV
@RW2+disp16, @RW2,
R3
R4
MOV
MOV
@RW1+disp16, @RW1,
R3
R4
MOV
MOV
@RW0+disp16, @RW0,
R3
R4
MOV
MOV
@RW7+disp8, R7,
R3
R4
MOV
MOV
@RW6+disp8, R6,
R3
R4
MOV
MOV
@RW5+disp8, R5,
R3
R4
MOV
MOV
@RW4+disp8, R4,
R3
R4
MOV
MOV
@RW3+disp8, R3,
R3
R4
MOV
MOV
@RW2+disp8, R2,
R3
R4
MOV
MOV
@RW1+disp8, R1,
R3
R4
MOV
R3
@RW0+disp8, R0,
MOV
70
MOV
A0
R5
MOV
addr16,
R4
MOV
@RW3+,
R5
MOV
@PC+disp16, @RW2+,
R4
R5
MOV
MOV
@RW1+RW7, @RW1+,
R4
R5
MOV
MOV
@RW0+RW7, @RW0+,
R4
R5
MOV
MOV
@RW3+disp16, @RW3,
R4
R5
MOV
MOV
@RW2+disp16, @RW2,
R4
R5
MOV
MOV
@RW1+disp16, @RW1,
R4
R5
MOV
MOV
@RW0+disp16, @RW0,
R4
R5
MOV
MOV
@RW7+disp8, R7,
R4
R5
MOV
MOV
@RW6+disp8, R6,
R4
R5
MOV
MOV
@RW5+disp8, R5,
R4
R5
MOV
MOV
@RW4+disp8, R4,
R4
R5
MOV
MOV
@RW3+disp8, R3,
R4
R5
MOV
MOV
@RW2+disp8, R2,
R4
R5
MOV
MOV
@RW1+disp8, R1,
R4
R5
MOV
R4
@RW0+disp8, R0,
MOV
90
MOV
C0
R6
MOV
addr16,
R5
MOV
@RW3+,
R6
MOV
@PC+disp16, @RW2+,
R5
R6
MOV
MOV
@RW1+RW7, @RW1+,
R5
R6
MOV
MOV
@RW0+RW7, @RW0+,
R5
R6
MOV
MOV
@RW3+disp16, @RW3,
R5
R6
MOV
MOV
@RW2+disp16, @RW2,
R5
R6
MOV
MOV
@RW1+disp16, @RW1,
R5
R6
MOV
MOV
@RW0+disp16, @RW0,
R5
R6
MOV
MOV
@RW7+disp8, R7,
R5
R6
MOV
MOV
@RW6+disp8, R6,
R5
R6
MOV
MOV
@RW5+disp8, R5,
R5
R6
MOV
MOV
@RW4+disp8, R4,
R5
R6
MOV
MOV
@RW3+disp8, R3,
R5
R6
MOV
MOV
@RW2+disp8, R2,
R5
R6
MOV
MOV
@RW1+disp8, R1,
R5
R6
MOV
R5
@RW0+disp8, R0,
MOV
B0
MOV
E0
R7
MOV
addr16,
R6
MOV
@RW3+,
R7
MOV
@PC+disp16, @RW2+,
R6
R7
MOV
MOV
@RW1+RW7, @RW1+,
R6
R7
MOV
MOV
@RW0+RW7, @RW0+,
R6
R7
MOV
MOV
@RW3+disp16, @RW3,
R6
R7
MOV
MOV
@RW2+disp16, @RW2,
R6
R7
MOV
MOV
@RW1+disp16, @RW1,
R6
R7
MOV
MOV
@RW0+disp16, @RW0,
R6
R7
MOV
MOV
@RW7+disp8, R7,
R6
R7
MOV
MOV
@RW6+disp8, R6,
R6
R7
MOV
MOV
@RW5+disp8, R5,
R6
R7
MOV
MOV
@RW4+disp8, R4,
R6
R7
MOV
MOV
@RW3+disp8, R3,
R6
R7
MOV
MOV
@RW2+disp8, R2,
R6
R7
MOV
MOV
@RW1+disp8, R1,
R6
R7
MOV
R6
@RW0+disp8, R0,
MOV
D0
MOV
addr16,
R7
R7
@PC+disp16,
MOV
R7
@RW1+RW7,
MOV
R7
@RW0+RW7,
MOV
R7
@RW3+disp16,
MOV
R7
@RW2+disp16,
MOV
R7
@RW1+disp16,
MOV
R7
@RW0+disp16,
MOV
R7
@RW7+disp8,
MOV
R7
@RW6+disp8,
MOV
R7
@RW5+disp8,
MOV
R7
@RW4+disp8,
MOV
R7
@RW3+disp8,
MOV
R7
@RW2+disp8,
MOV
R7
@RW1+disp8,
MOV
R7
@RW0+disp8,
MOV
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.10-1 MOV ea, Ri Instruction (First Byte = 7CH)
CM44-00203-3E
2
F MC-16FX Family
C.11 MOVW ea, RWi Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.11-1 lists MOVW ea, RWi instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
365
366
FUJITSU MICROELECTRONICS LIMITED
MOVW
@RW1+disp8, RW1,
RW0
RW1
MOVW
MOVW
@RW2+disp8, RW2,
RW0
RW1
MOVW
MOVW
@RW3+disp8, RW3,
RW0
RW1
MOVW
MOVW
@RW4+disp8, RW4,
RW0
RW1
MOVW
MOVW
@RW5+disp8, RW5,
RW0
RW1
MOVW
MOVW
@RW6+disp8, RW6,
RW0
RW1
MOVW
MOVW
@RW7+disp8, RW7,
RW0
RW1
MOVW
MOVW
@RW0+disp16, @RW0,
RW0
RW1
MOVW
MOVW
@RW1+disp16, @RW1,
RW0
RW1
MOVW
MOVW
@RW2+disp16, @RW2,
RW0
RW1
MOVW
MOVW
@RW3+disp16, @RW3,
RW0
RW1
MOVW
MOVW
+2 RW2,
RW0
MOVW
+3 RW3,
RW0
MOVW
+4 RW4,
RW0
MOVW
+5 RW5,
RW0
MOVW
+6 RW6,
RW0
MOVW
+7 RW7,
RW0
MOVW
+8 @RW0,
RW0
MOVW
+9 @RW1,
RW0
MOVW
+A @RW2,
RW0
MOVW
+B @RW3,
RW0
MOVW
+C @RW0+,
RW0
MOVW
@RW1+RW7, @RW1+,
RW0
RW1
MOVW
MOVW
@PC+disp16, @RW2+,
RW0
RW1
MOVW
addr16,
RW0
MOVW
+E @RW2+,
RW0
MOVW
+F @RW3+,
RW0
MOVW
@RW3+,
RW1
MOVW
MOVW
+D @RW1+,
RW0
MOVW
@RW0+RW7, @RW0+,
RW0
RW1
MOVW
RW1
MOVW
+1 RW1,
RW0
RW0
MOVW
MOVW
addr16,
RW1
MOVW
@RW3+,
RW2
MOVW
@PC+disp16, @RW2+,
RW1
RW2
MOVW
MOVW
@RW1+RW7, @RW1+,
RW1
RW2
MOVW
MOVW
@RW0+RW7, @RW0+,
RW1
RW2
MOVW
MOVW
@RW3+disp16, @RW3,
RW1
RW2
MOVW
MOVW
@RW2+disp16, @RW2,
RW1
RW2
MOVW
MOVW
@RW1+disp16, @RW1,
RW1
RW2
MOVW
MOVW
@RW0+disp16, @RW0,
RW1
RW2
MOVW
MOVW
@RW7+disp8, RW7,
RW1
RW2
MOVW
MOVW
@RW6+disp8, RW6,
RW1
RW2
MOVW
MOVW
@RW5+disp8, RW5,
RW1
RW2
MOVW
MOVW
@RW4+disp8, RW4,
RW1
RW2
MOVW
MOVW
@RW3+disp8, RW3,
RW1
RW2
MOVW
MOVW
@RW2+disp8, RW2,
RW1
RW2
MOVW
MOVW
@RW1+disp8, RW1,
RW1
RW2
MOVW
RW2
RW1
MOVW
40
@RW0+disp8, RW0,
MOVW
30
RW0
MOVW
20
@RW0+disp8, RW0,
MOVW
+0 RW0,
10
00
MOVW
60
RW3
MOVW
addr16,
RW2
MOVW
@RW3+,
RW3
MOVW
@PC+disp16, @RW2+,
RW2
RW3
MOVW
MOVW
@RW1+RW7, @RW1+,
RW2
RW3
MOVW
MOVW
@RW0+RW7, @RW0+,
RW2
RW3
MOVW
MOVW
@RW3+disp16, @RW3,
RW2
RW3
MOVW
MOVW
@RW2+disp16, @RW2,
RW2
RW3
MOVW
MOVW
@RW1+disp16, @RW1,
RW2
RW3
MOVW
MOVW
@RW0+disp16, @RW0,
RW2
RW3
MOVW
MOVW
@RW7+disp8, RW7,
RW2
RW3
MOVW
MOVW
@RW6+disp8, RW6,
RW2
RW3
MOVW
MOVW
@RW5+disp8, RW5,
RW2
RW3
MOVW
MOVW
@RW4+disp8, RW4,
RW2
RW3
MOVW
MOVW
@RW3+disp8, RW3,
RW2
RW3
MOVW
MOVW
@RW2+disp8, RW2,
RW2
RW3
MOVW
MOVW
@RW1+disp8, RW1,
RW2
RW3
MOVW
RW2
@RW0+disp8, RW0,
MOVW
50
MOVW
80
RW4
MOVW
addr16,
RW3
MOVW
@RW3+,
RW4
MOVW
@PC+disp16, @RW2+,
RW3
RW4
MOVW
MOVW
@RW1+RW7, @RW1+,
RW3
RW4
MOVW
MOVW
@RW0+RW7, @RW0+,
RW3
RW4
MOVW
MOVW
@RW3+disp16, @RW3,
RW3
RW4
MOVW
MOVW
@RW2+disp16, @RW2,
RW3
RW4
MOVW
MOVW
@RW1+disp16, @RW1,
RW3
RW4
MOVW
MOVW
@RW0+disp16, @RW0,
RW3
RW4
MOVW
MOVW
@RW7+disp8, RW7,
RW3
RW4
MOVW
MOVW
@RW6+disp8, RW6,
RW3
RW4
MOVW
MOVW
@RW5+disp8, RW5,
RW3
RW4
MOVW
MOVW
@RW4+disp8, RW4,
RW3
RW4
MOVW
MOVW
@RW3+disp8, RW3,
RW3
RW4
MOVW
MOVW
@RW2+disp8, RW2,
RW3
RW4
MOVW
MOVW
@RW1+disp8, RW1,
RW3
RW4
MOVW
RW3
@RW0+disp8, RW0,
MOVW
70
MOVW
A0
RW5
MOVW
addr16,
RW4
MOVW
@RW3+,
RW5
MOVW
@PC+disp16, @RW2+,
RW4
RW5
MOVW
MOVW
@RW1+RW7, @RW1+,
RW4
RW5
MOVW
MOVW
@RW0+RW7, @RW0+,
RW4
RW5
MOVW
MOVW
@RW3+disp16, @RW3,
RW4
RW5
MOVW
MOVW
@RW2+disp16, @RW2,
RW4
RW5
MOVW
MOVW
@RW1+disp16, @RW1,
RW4
RW5
MOVW
MOVW
@RW0+disp16, @RW0,
RW4
RW5
MOVW
MOVW
@RW7+disp8, RW7,
RW4
RW5
MOVW
MOVW
@RW6+disp8, RW6,
RW4
RW5
MOVW
MOVW
@RW5+disp8, RW5,
RW4
RW5
MOVW
MOVW
@RW4+disp8, RW4,
RW4
RW5
MOVW
MOVW
@RW3+disp8, RW3,
RW4
RW5
MOVW
MOVW
@RW2+disp8, RW2,
RW4
RW5
MOVW
MOVW
@RW1+disp8, RW1,
RW4
RW5
MOVW
RW4
@RW0+disp8, RW0,
MOVW
90
MOVW
C0
RW6
MOVW
addr16,
RW5
MOVW
@RW3+,
RW6
MOVW
@PC+disp16, @RW2+,
RW5
RW6
MOVW
MOVW
@RW1+RW7, @RW1+,
RW5
RW6
MOVW
MOVW
@RW0+RW7, @RW0+,
RW5
RW6
MOVW
MOVW
@RW3+disp16, @RW3,
RW5
RW6
MOVW
MOVW
@RW2+disp16, @RW2,
RW5
RW6
MOVW
MOVW
@RW1+disp16, @RW1,
RW5
RW6
MOVW
MOVW
@RW0+disp16, @RW0,
RW5
RW6
MOVW
MOVW
@RW7+disp8, RW7,
RW5
RW6
MOVW
MOVW
@RW6+disp8, RW6,
RW5
RW6
MOVW
MOVW
@RW5+disp8, RW5,
RW5
RW6
MOVW
MOVW
@RW4+disp8, RW4,
RW5
RW6
MOVW
MOVW
@RW3+disp8, RW3,
RW5
RW6
MOVW
MOVW
@RW2+disp8, RW2,
RW5
RW6
MOVW
MOVW
@RW1+disp8, RW1,
RW5
RW6
MOVW
RW5
@RW0+disp8, RW0,
MOVW
B0
MOVW
E0
RW7
MOVW
addr16,
RW6
MOVW
@RW3+,
RW7
MOVW
@PC+disp16, @RW2+,
RW6
RW7
MOVW
MOVW
@RW1+RW7, @RW1+,
RW6
RW7
MOVW
MOVW
@RW0+RW7, @RW0+,
RW6
RW7
MOVW
MOVW
@RW3+disp16, @RW3,
RW6
RW7
MOVW
MOVW
@RW2+disp16, @RW2,
RW6
RW7
MOVW
MOVW
@RW1+disp16, @RW1,
RW6
RW7
MOVW
MOVW
@RW0+disp16, @RW0,
RW6
RW7
MOVW
MOVW
@RW7+disp8, RW7,
RW6
RW7
MOVW
MOVW
@RW6+disp8, RW6,
RW6
RW7
MOVW
MOVW
@RW5+disp8, RW5,
RW6
RW7
MOVW
MOVW
@RW4+disp8, RW4,
RW6
RW7
MOVW
MOVW
@RW3+disp8, RW3,
RW6
RW7
MOVW
MOVW
@RW2+disp8, RW2,
RW6
RW7
MOVW
MOVW
@RW1+disp8, RW1,
RW6
RW7
MOVW
RW6
@RW0+disp8, RW0,
MOVW
D0
MOVW
addr16,
RW7
RW7
@PC+disp16,
MOVW
RW7
@RW1+RW7,
MOVW
RW7
@RW0+RW7,
MOVW
RW7
@RW3+disp16,
MOVW
RW7
@RW2+disp16,
MOVW
RW7
@RW1+disp16,
MOVW
RW7
@RW0+disp16,
MOVW
RW7
@RW7+disp8,
MOVW
RW7
@RW6+disp8,
MOVW
RW7
@RW5+disp8,
MOVW
RW7
@RW4+disp8,
MOVW
RW7
@RW3+disp8,
MOVW
RW7
@RW2+disp8,
MOVW
RW7
@RW1+disp8,
MOVW
RW7
@RW0+disp8,
MOVW
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.11-1 MOVW ea, RWi Instruction (First Byte = 7DH)
CM44-00203-3E
2
F MC-16FX Family
C.12 XCH Ri, ea Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.12-1 lists XCH Ri, ea instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
367
368
XCH
XCH
R0,
XCH
R1,
@RW3+disp8 R3
XCH
R0,
XCH
R0,
XCH
+3 R0,
R3
XCH
+4 R0,
R4
XCH
XCH
R0,
XCH
R1,
@RW7+disp8 R7
XCH
R0,
XCH
+7 R0,
R7
XCH
+8 R0,
@RW0
FUJITSU MICROELECTRONICS LIMITED
XCH
R0,
XCH
R1,
@RW3+disp16 @RW3
XCH
R0,
XCH
+B R0,
@RW3
XCH
+C R0,
@RW0+
XCH
R1,
@PC+disp16 @RW2+
XCH
R0,
addr16
XCH
+F R0,
@RW3+
XCH
R1,
@RW3+
XCH
R0,
XCH
R1,
@RW1+RW7 @RW1+
XCH
R0,
XCH
+E R0,
@RW2+
@RW1+
+D R0,
XCH
XCH
R1,
@RW2+disp16 @RW2
XCH
R1,
@RW0+RW7 @RW0+
XCH
R0,
XCH
R1,
@RW1+disp16 @RW1
XCH
R0,
XCH
+A R0,
@RW2
@RW1
+9 R0,
XCH
XCH
R1,
@RW6+disp8 R6
XCH
R1,
@RW0+disp16 @RW0
XCH
R0,
XCH
R1,
@RW5+disp8 R5
XCH
+6 R0,
R6
R5
+5 R0,
XCH
R1,
@RW2+disp8 R2
XCH
R1,
@RW4+disp8 R4
XCH
R0,
XCH
+2 R0,
R2
R1
+1 R0,
XCH
R1,
@RW1+disp8 R1
XCH
R0,
R0
20
XCH
R1,
XCH
R0,
+0 R0,
@RW0+disp8 R0
10
XCH
00
XCH
R1,
addr16
XCH
R2,
@RW3+
XCH
R2,
@PC+disp16 @RW2+
XCH
R1,
XCH
R2,
@RW1+RW7 @RW1+
XCH
R1,
XCH
R2,
@RW0+RW7 @RW0+
XCH
R1,
XCH
R2,
@RW3+disp16 @RW3
XCH
R1,
XCH
R2,
@RW2+disp16 @RW2
XCH
R1,
XCH
R2,
@RW1+disp16 @RW1
XCH
R1,
XCH
R2,
@RW0+disp16 @RW0
XCH
R1,
XCH
R2,
@RW7+disp8 R7
XCH
R1,
XCH
R2,
@RW6+disp8 R6
XCH
R1,
XCH
R2,
@RW5+disp8 R5
XCH
R1,
XCH
R2,
@RW4+disp8 R4
XCH
R1,
XCH
R2,
@RW3+disp8 R3
XCH
R1,
XCH
R2,
@RW2+disp8 R2
XCH
R1,
XCH
R2,
@RW1+disp8 R1
XCH
R1,
40
XCH
R2,
@RW0+disp8 R0
XCH
R1,
30
XCH
R2,
addr16
XCH
R3,
@RW3+
XCH
R3,
@PC+disp16 @RW2+
XCH
R2,
XCH
R3,
@RW1+RW7 @RW1+
XCH
R2,
XCH
R3,
@RW0+RW7 @RW0+
XCH
R2,
XCH
R3,
@RW3+disp16 @RW3
XCH
R2,
XCH
R3,
@RW2+disp16 @RW2
XCH
R2,
XCH
R3,
@RW1+disp16 @RW1
XCH
R2,
XCH
R3,
@RW0+disp16 @RW0
XCH
R2,
XCH
R3,
@RW7+disp8 R7
XCH
R2,
XCH
R3,
@RW6+disp8 R6
XCH
R2,
XCH
R3,
@RW5+disp8 R5
XCH
R2,
XCH
R3,
@RW4+disp8 R4
XCH
R2,
XCH
R3,
@RW3+disp8 R3
XCH
R2,
XCH
R3,
@RW2+disp8 R2
XCH
R2,
XCH
R3,
@RW1+disp8 R1
XCH
R2,
60
XCH
R3,
@RW0+disp8 R0
XCH
R2,
50
XCH
R3,
addr16
XCH
R4,
@RW3+
XCH
R4,
@PC+disp16 @RW2+
XCH
R3,
XCH
R4,
@RW1+RW7 @RW1+
XCH
R3,
XCH
R4,
@RW0+RW7 @RW0+
XCH
R3,
XCH
R4,
@RW3+disp16 @RW3
XCH
R3,
XCH
R4,
@RW2+disp16 @RW2
XCH
R3,
XCH
R4,
@RW1+disp16 @RW1
XCH
R3,
XCH
R4,
@RW0+disp16 @RW0
XCH
R3,
XCH
R4,
@RW7+disp8 R7
XCH
R3,
XCH
R4,
@RW6+disp8 R6
XCH
R3,
XCH
R4,
@RW5+disp8 R5
XCH
R3,
XCH
R4,
@RW4+disp8 R4
XCH
R3,
XCH
R4,
@RW3+disp8 R3
XCH
R3,
XCH
R4,
@RW2+disp8 R2
XCH
R3,
XCH
R4,
@RW1+disp8 R1
XCH
R3,
80
XCH
R4,
@RW0+disp8 R0
XCH
R3,
70
XCH
R4,
addr16
XCH
R5,
@RW3+
XCH
R5,
@PC+disp16 @RW2+
XCH
R4,
XCH
R5,
@RW1+RW7 @RW1+
XCH
R4,
XCH
R5,
@RW0+RW7 @RW0+
XCH
R4,
XCH
R5,
@RW3+disp16 @RW3
XCH
R4,
XCH
R5,
@RW2+disp16 @RW2
XCH
R4,
XCH
R5,
@RW1+disp16 @RW1
XCH
R4,
XCH
R5,
@RW0+disp16 @RW0
XCH
R4,
XCH
R5,
@RW7+disp8 R7
XCH
R4,
XCH
R5,
@RW6+disp8 R6
XCH
R4,
XCH
R5,
@RW5+disp8 R5
XCH
R4,
XCH
R5,
@RW4+disp8 R4
XCH
R4,
XCH
R5,
@RW3+disp8 R3
XCH
R4,
XCH
R5,
@RW2+disp8 R2
XCH
R4,
XCH
R5,
@RW1+disp8 R1
XCH
R4,
A0
XCH
R5,
@RW0+disp8 R0
XCH
R4,
90
XCH
R5,
addr16
XCH
R6,
@RW3+
XCH
R6,
@PC+disp16 @RW2+
XCH
R5,
XCH
R6,
@RW1+RW7 @RW1+
XCH
R5,
XCH
R6,
@RW0+RW7 @RW0+
XCH
R5,
XCH
R6,
@RW3+disp16 @RW3
XCH
R5,
XCH
R6,
@RW2+disp16 @RW2
XCH
R5,
XCH
R6,
@RW1+disp16 @RW1
XCH
R5,
XCH
R6,
@RW0+disp16 @RW0
XCH
R5,
XCH
R6,
@RW7+disp8 R7
XCH
R5,
XCH
R6,
@RW6+disp8 R6
XCH
R5,
XCH
R6,
@RW5+disp8 R5
XCH
R5,
XCH
R6,
@RW4+disp8 R4
XCH
R5,
XCH
R6,
@RW3+disp8 R3
XCH
R5,
XCH
R6,
@RW2+disp8 R2
XCH
R5,
XCH
R6,
@RW1+disp8 R1
XCH
R5,
C0
XCH
R6,
@RW0+disp8 R0
XCH
R5,
B0
XCH
R6,
addr16
XCH
R7,
@RW3+
XCH
R7,
@PC+disp16 @RW2+
XCH
R6,
XCH
R7,
@RW1+RW7 @RW1+
XCH
R6,
XCH
R7,
@RW0+RW7 @RW0+
XCH
R6,
XCH
R7,
@RW3+disp16 @RW3
XCH
R6,
XCH
R7,
@RW2+disp16 @RW2
XCH
R6,
XCH
R7,
@RW1+disp16 @RW1
XCH
R6,
XCH
R7,
@RW0+disp16 @RW0
XCH
R6,
XCH
R7,
@RW7+disp8 R7
XCH
R6,
XCH
R7,
@RW6+disp8 R6
XCH
R6,
XCH
R7,
@RW5+disp8 R5
XCH
R6,
XCH
R7,
@RW4+disp8 R4
XCH
R6,
XCH
R7,
@RW3+disp8 R3
XCH
R6,
XCH
R7,
@RW2+disp8 R2
XCH
R6,
XCH
R7,
@RW1+disp8 R1
XCH
R6,
E0
XCH
R7,
@RW0+disp8 R0
XCH
R6,
D0
XCH
R7,
addr16
@PC+disp16
XCH
R7,
@RW1+RW7
XCH
R7,
@RW0+RW7
XCH
R7,
@RW3+disp16
XCH
R7,
@RW2+disp16
XCH
R7,
@RW1+disp16
XCH
R7,
@RW0+disp16
XCH
R7,
@RW7+disp8
XCH
R7,
@RW6+disp8
XCH
R7,
@RW5+disp8
XCH
R7,
@RW4+disp8
XCH
R7,
@RW3+disp8
XCH
R7,
@RW2+disp8
XCH
R7,
@RW1+disp8
XCH
R7,
@RW0+disp8
XCH
R7,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.12-1 XCH Ri, ea Instruction (First Byte = 7EH)
CM44-00203-3E
2
F MC-16FX Family
C.13 XCHW RWi, ea Instruction Map
APPENDIX
APPENDIX C Instruction Maps
Table C.13-1 lists XCHW RWi, ea instruction map.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
369
370
XCHW
RW0,
RW0
XCHW
XCHW
RW0,
XCHW
RW1,
@RW3+disp8 RW3
XCHW
RW0,
XCHW
RW0,
XCHW
+3 RW0,
RW3
XCHW
+4 RW0,
RW4
XCHW
XCHW
RW0,
XCHW
RW1,
@RW7+disp8 RW7
XCHW
RW0,
XCHW
RW0,
XCHW
+7 RW0,
RW7
XCHW
+8 RW0,
@RW0
XCHW
FUJITSU MICROELECTRONICS LIMITED
XCHW
RW0,
XCHW
RW1,
@RW3+disp16 @RW3
XCHW
RW0,
XCHW
+B RW0,
@RW3
XCHW
+C RW0,
@RW0+
@RW1+RW7
@RW1+
@PC+disp16
XCHW
RW0,
addr16
XCHW
+E RW0,
@RW2+
XCHW
+F RW0,
@RW3+
XCHW
RW0,
XCHW
RW0,
+D RW0,
XCHW
@RW0+RW7
XCHW
RW1,
@RW2+disp16 @RW2
XCHW
RW1,
@RW3+
XCHW
RW1,
@RW2+
XCHW
RW1,
@RW1+
XCHW
RW1,
@RW0+
XCHW
RW0,
XCHW
RW1,
@RW1+disp16 @RW1
XCHW
+A RW0,
@RW2
@RW1
+9 RW0,
XCHW
RW1,
@RW6+disp8 RW6
XCHW
RW1,
@RW0+disp16 @RW0
XCHW
RW0,
XCHW
RW1,
@RW5+disp8 RW5
XCHW
+6 RW0,
RW6
RW5
+5 RW0,
XCHW
RW1,
@RW2+disp8 RW2
XCHW
RW1,
@RW4+disp8 RW4
XCHW
RW0,
XCHW
+2 RW0,
RW2
RW1
+1 RW0,
XCHW
RW1,
RW0
20
XCHW
RW1,
@RW1+disp8 RW1
XCHW
RW0,
@RW0+disp8
+0 RW0,
XCHW
10
00
XCHW
RW2,
RW0
40
XCHW
RW1,
addr16
@PC+disp16
XCHW
RW1,
@RW1+RW7
XCHW
RW1,
@RW0+RW7
XCHW
RW1,
XCHW
RW2,
@RW3+
XCHW
RW2,
@RW2+
XCHW
RW2,
@RW1+
XCHW
RW2,
@RW0+
XCHW
RW2,
@RW3+disp16 @RW3
XCHW
RW1,
XCHW
RW2,
@RW2+disp16 @RW2
XCHW
RW1,
XCHW
RW2,
@RW1+disp16 @RW1
XCHW
RW1,
XCHW
RW2,
@RW0+disp16 @RW0
XCHW
RW1,
XCHW
RW2,
@RW7+disp8 RW7
XCHW
RW1,
XCHW
RW2,
@RW6+disp8 RW6
XCHW
RW1,
XCHW
RW2,
@RW5+disp8 RW5
XCHW
RW1,
XCHW
RW2,
@RW4+disp8 RW4
XCHW
RW1,
XCHW
RW2,
@RW3+disp8 RW3
XCHW
RW1,
XCHW
RW2,
@RW2+disp8 RW2
XCHW
RW1,
XCHW
RW2,
@RW1+disp8 RW1
XCHW
RW1,
@RW0+disp8
XCHW
RW1,
30
XCHW
RW3,
RW0
60
XCHW
RW2,
addr16
@PC+disp16
XCHW
RW2,
@RW1+RW7
XCHW
RW2,
@RW0+RW7
XCHW
RW2,
XCHW
RW3,
@RW3+
XCHW
RW3,
@RW2+
XCHW
RW3,
@RW1+
XCHW
RW3,
@RW0+
XCHW
RW3,
@RW3+disp16 @RW3
XCHW
RW2,
XCHW
RW3,
@RW2+disp16 @RW2
XCHW
RW2,
XCHW
RW3,
@RW1+disp16 @RW1
XCHW
RW2,
XCHW
RW3,
@RW0+disp16 @RW0
XCHW
RW2,
XCHW
RW3,
@RW7+disp8 RW7
XCHW
RW2,
XCHW
RW3,
@RW6+disp8 RW6
XCHW
RW2,
XCHW
RW3,
@RW5+disp8 RW5
XCHW
RW2,
XCHW
RW3,
@RW4+disp8 RW4
XCHW
RW2,
XCHW
RW3,
@RW3+disp8 RW3
XCHW
RW2,
XCHW
RW3,
@RW2+disp8 RW2
XCHW
RW2,
XCHW
RW3,
@RW1+disp8 RW1
XCHW
RW2,
@RW0+disp8
XCHW
RW2,
50
XCHW
RW4,
RW0
80
XCHW
RW3,
addr16
@PC+disp16
XCHW
RW3,
@RW1+RW7
XCHW
RW3,
@RW0+RW7
XCHW
RW3,
XCHW
RW4,
@RW3+
XCHW
RW4,
@RW2+
XCHW
RW4,
@RW1+
XCHW
RW4,
@RW0+
XCHW
RW4,
@RW3+disp16 @RW3
XCHW
RW3,
XCHW
RW4,
@RW2+disp16 @RW2
XCHW
RW3,
XCHW
RW4,
@RW1+disp16 @RW1
XCHW
RW3,
XCHW
RW4,
@RW0+disp16 @RW0
XCHW
RW3,
XCHW
RW4,
@RW7+disp8 RW7
XCHW
RW3,
XCHW
RW4,
@RW6+disp8 RW6
XCHW
RW3,
XCHW
RW4,
@RW5+disp8 RW5
XCHW
RW3,
XCHW
RW4,
@RW4+disp8 RW4
XCHW
RW3,
XCHW
RW4,
@RW3+disp8 RW3
XCHW
RW3,
XCHW
RW4,
@RW2+disp8 RW2
XCHW
RW3,
XCHW
RW4,
@RW1+disp8 RW1
XCHW
RW3,
@RW0+disp8
XCHW
RW3,
70
XCHW
RW5,
RW0
A0
XCHW
RW4,
addr16
@PC+disp16
XCHW
RW4,
@RW1+RW7
XCHW
RW4,
@RW0+RW7
XCHW
RW4,
XCHW
RW5,
@RW3+
XCHW
RW5,
@RW2+
XCHW
RW5,
@RW1+
XCHW
RW5,
@RW0+
XCHW
RW5,
@RW3+disp16 @RW3
XCHW
RW4,
XCHW
RW5,
@RW2+disp16 @RW2
XCHW
RW4,
XCHW
RW5,
@RW1+disp16 @RW1
XCHW
RW4,
XCHW
RW5,
@RW0+disp16 @RW0
XCHW
RW4,
XCHW
RW5,
@RW7+disp8 RW7
XCHW
RW4,
XCHW
RW5,
@RW6+disp8 RW6
XCHW
RW4,
XCHW
RW5,
@RW5+disp8 RW5
XCHW
RW4,
XCHW
RW5,
@RW4+disp8 RW4
XCHW
RW4,
XCHW
RW5,
@RW3+disp8 RW3
XCHW
RW4,
XCHW
RW5,
@RW2+disp8 RW2
XCHW
RW4,
XCHW
RW5,
@RW1+disp8 RW1
XCHW
RW4,
@RW0+disp8
XCHW
RW4,
90
XCHW
RW6,
RW0
C0
XCHW
RW5,
addr16
@PC+disp16
XCHW
RW5,
@RW1+RW7
XCHW
RW5,
@RW0+RW7
XCHW
RW5,
XCHW
RW6,
@RW3+
XCHW
RW6,
@RW2+
XCHW
RW6,
@RW1+
XCHW
RW6,
@RW0+
XCHW
RW6,
@RW3+disp16 @RW3
XCHW
RW5,
XCHW
RW6,
@RW2+disp16 @RW2
XCHW
RW5,
XCHW
RW6,
@RW1+disp16 @RW1
XCHW
RW5,
XCHW
RW6,
@RW0+disp16 @RW0
XCHW
RW5,
XCHW
RW6,
@RW7+disp8 RW7
XCHW
RW5,
XCHW
RW6,
@RW6+disp8 RW6
XCHW
RW5,
XCHW
RW6,
@RW5+disp8 RW5
XCHW
RW5,
XCHW
RW6,
@RW4+disp8 RW4
XCHW
RW5,
XCHW
RW6,
@RW3+disp8 RW3
XCHW
RW5,
XCHW
RW6,
@RW2+disp8 RW2
XCHW
RW5,
XCHW
RW6,
@RW1+disp8 RW1
XCHW
RW5,
@RW0+disp8
XCHW
RW5,
B0
XCHW
RW7,
RW0
E0
XCHW
RW6,
addr16
@PC+disp16
XCHW
RW6,
@RW1+RW7
XCHW
RW6,
@RW0+RW7
XCHW
RW6,
XCHW
RW7,
@RW3+
XCHW
RW7,
@RW2+
XCHW
RW7,
@RW1+
XCHW
RW7,
@RW0+
XCHW
RW7,
@RW3+disp16 @RW3
XCHW
RW6,
XCHW
RW7,
@RW2+disp16 @RW2
XCHW
RW6,
XCHW
RW7,
@RW1+disp16 @RW1
XCHW
RW6,
XCHW
RW7,
@RW0+disp16 @RW0
XCHW
RW6,
XCHW
RW7,
@RW7+disp8 RW7
XCHW
RW6,
XCHW
RW7,
@RW6+disp8 RW6
XCHW
RW6,
XCHW
RW7,
@RW5+disp8 RW5
XCHW
RW6,
XCHW
RW7,
@RW4+disp8 RW4
XCHW
RW6,
XCHW
RW7,
@RW3+disp8 RW3
XCHW
RW6,
XCHW
RW7,
@RW2+disp8 RW2
XCHW
RW6,
XCHW
RW7,
@RW1+disp8 RW1
XCHW
RW6,
@RW0+disp8
XCHW
RW6,
D0
XCHW
RW7,
addr16
@PC+disp16
XCHW
RW7,
@RW1+RW7
XCHW
RW7,
@RW0+RW7
XCHW
RW7,
@RW3+disp16
XCHW
RW7,
@RW2+disp16
XCHW
RW7,
@RW1+disp16
XCHW
RW7,
@RW0+disp16
XCHW
RW7,
@RW7+disp8
XCHW
RW7,
@RW6+disp8
XCHW
RW7,
@RW5+disp8
XCHW
RW7,
@RW4+disp8
XCHW
RW7,
@RW3+disp8
XCHW
RW7,
@RW2+disp8
XCHW
RW7,
@RW1+disp8
XCHW
RW7,
@RW0+disp8
XCHW
RW7,
F0
APPENDIX
APPENDIX C Instruction Maps
F2MC-16FX Family
Table C.13-1 XCHW RWi, ea Instruction (First Byte = 7FH)
CM44-00203-3E
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
CM44-00203-3E
FUJITSU MICROELECTRONICS LIMITED
371
INDEX
Index
A
B
A
B
Accumulator (A).........................................20
ADD (Add Byte Data of Destination and Source
to Destination) ...............................83
ADDC (Add Byte Data of Accumulator and
Effective Address with Carry to
Accumulator).................................86
ADDC (Add Byte Data of AL and AH with Carry
to AL) ...........................................85
ADDCW (Add Word Data of Accumulator and
Effective Address with Carry to
Accumulator).................................88
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)..................................90
ADDL (Add Long Word Data of Destination and
Source to Destination) ....................91
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack
Pointer) .........................................93
ADDW (Add Word Data of AL and
AH to AL).....................................94
ADDW (Add Word Data of Destination and
Source to Destination) ....................95
AND (And Byte Data of Destination and Source
to Destination) ...............................97
AND (And Byte Data of Immediate Data and
Condition Code Register)................99
ANDL (And Long Word Data of Destination and
Source to Destination) ..................101
ANDW (And Word Data of AH and
AL to AL) ...................................103
ANDW (And Word Data of Destination and
Source to Destination) ..................104
ASR (Arithmetic Shift Byte Data of
Accumulator to Right) ..................106
ASRL (Arithmetic Shift Long Word Data of Accumulator to Right) ......................108
ASRW (Arithmetic Shift Word Data of
Accumulator to Right) ..........110, 112
Accumulator
Accumulator (A).........................................20
Addressing
Bank Addressing Mode ...............................12
Direct Addressing .......................................73
Indirect Addressing .....................................75
Linear Addressing Mode..............................11
BBcc (Branch if Bit Condition
satisfied)..................................... 114
Bcc (Branch relative if Condition
satisfied)..................................... 116
Bank Addressing
Bank Addressing Mode............................... 12
Bank Select Prefix
Bank Select Prefix...................................... 38
Banks
Memory Space Divided into Banks and Values in
Each Register Bank ....................... 14
372
C
C
CALL (Call Subroutine) ........................... 118
CALLP (Call Physical Address) ................ 120
CALLV (Call Vectored Subroutine)........... 122
CBNE (Compare Byte Data and Branch if not
Equal) ........................................ 124
CLRB (Clear Bit) ..................................... 126
CMP (Compare Byte Data of Destination and
Source)....................................... 127
CMPL (Compare Long Word Data of
Destination and Source) ............... 129
CMPW (Compare Word Data of Destination and
Source)....................................... 131
CWBNE (Compare Word Data and Branch if not
Equal) ........................................ 133
CCR
Condition Code Register (CCR)................... 25
CMR
Common Register Bank Prefix (CMR) ......... 40
Common Register Bank Prefix
Common Register Bank Prefix (CMR) ......... 40
Condition Code Register
Condition Code Register (CCR)................... 25
Correction Address
Odd Address Correction.............................. 82
CPU
CPU Memory Space ................................... 10
Hardware Configuration of the F2MC-16FX
CPU............................................... 4
Overview of CPU......................................... 2
Cycle
Execution Cycles........................................ 82
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CM44-00203-3E
INDEX
D
G
D
General-purpose Registers
Calling General-purpose Registers in
RAM............................................ 36
DBNZ (Decrement Byte Data and Branch if not
Zero)...........................................135
DEC (Decrement Byte Data) ......................137
DECL (Decrement Long Word Data)..........138
DECW (Decrement Word Data) .................139
DIV (Divide Word Data by Byte Data) .......141
DIVU (Divide unsigned Word Data by unsigned
Byte Data) ...................................145
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data)....................147
DIVW (Divide Long Word Data by Word
Data)...........................................143
DWBNZ (Decrement Word Data and Branch if
not Zero) .....................................149
Direct Addressing
Direct Addressing .......................................73
Direct Memory Access
Direct Memory Access (DMA) ....................47
Direct Page Register
Direct Page Register (DPR) .........................30
DMA
Direct Memory Access (DMA) ....................47
DPR
Direct Page Register (DPR) .........................30
H
Hardware
Hardware Configuration of the F2MC-16FX
CPU............................................... 4
Hardware Exceptions (Non Maskable
Interrupts)..................................... 67
Hardware Interrupt Operation...................... 59
Hardware Interrupt Processing Time ............ 60
Hardware Interrupts.............................. 46, 57
Multiple Hardware Interrupts ...................... 63
Sample Hardware configuration of F2MC-16FX
Family MCU................................... 6
Structure of the Hardware Interrupt
System ......................................... 57
I
I
INC (Increment Byte Data (Address
Specification)) ............................ 157
INCL (Increment Long Word Data) ........... 158
INCW (Increment Word Data)................... 159
INT (Software Interrupt (Vector
Specification)) ............................ 163
INT (Software Interrupt) ........................... 161
INT9 (Software Interrupt) ......................... 165
INTP (Software Interrupt) ......................... 167
E
E
EXT (Sign Extend from Byte Data to
Word Data) .................................151
EXTW (Sign Extend from Word Data to Long
Word Data) .................................152
Effective Address
Effective Address Field ...............................72
Exception
Exceptions..................................................47
Hardware Exceptions (Non Maskable
Interrupts) .....................................67
Software Exceptions (Op-Code) ...................66
Execution cycle
Execution cycle count................................316
F
F
FILS, FILSI (Fill String Byte) ....................153
FILSW, FILSWI (Fill String Word)............155
2
F MC-16FX
Hardware Configuration of the F2MC-16FX
CPU................................................4
Sample Hardware configuration of F2MC-16FX
Family MCU ...................................6
Flag Change Inhibit Prefix Code
Flag Change Inhibit Prefix Code (NCC) ........41
CM44-00203-3E
ICR
Interrupt Control Register (ICR) .................. 51
ILM
Interrupt Level Mask (ILM) ........................ 27
Indirect Addressing
Indirect Addressing .................................... 75
Instruction
Explanation of the Symbols Used in the
Instruction Lists .......................... 317
Instruction Overview .................................. 80
MOV Ri, ea Instruction Map
(First Byte = 7AH)....................... 360
Relationships between Instructions Rejecting
Interrupt Requests and Prefix
Codes ........................................... 42
Structure of the Instruction Map ................ 337
Symbols (Abbreviations) Used in Detailed
Instructions................................... 81
Instruction Map
Structure of the Instruction Map ................ 337
Interrupt
Hardware Interrupt Operation...................... 59
Hardware Interrupt Processing Time ............ 60
Hardware Interrupts.............................. 46, 57
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373
INDEX
Interrupt Acceptance Priority .......................64
Interrupt Flow.............................................55
Interrupt Vector ..........................................48
Multiple Hardware Interrupts .......................63
Multiple Software Interrupts ........................63
Relationships between Instructions Rejecting
Interrupt Requests and Prefix
Codes............................................42
Software Interrupt Operation........................62
Software Interrupts................................47, 61
Structure of the Hardware Interrupt
System ..........................................57
Structure of the Software Interrupt
System ..........................................61
Interrupt Control Register
Interrupt Control Register (ICR) ...................51
Interrupt Level Mask
Interrupt Level Mask (ILM) .........................27
J
J
JCTX (Jump Context)................................169
JMP (Jump Destination Address)................171
JMPP (Jump Destination Physical
Address)......................................172
L
L
LINK (Link and Create New Stack
Frame) ........................................173
LSL (Logical Shift Byte Data of Accumulator to
Left) ...........................................174
LSLL (Logical Shift Long Word Data of
Accumulator to Left) ....................176
LSLW (Logical Shift Word Data of Accumulator
to Left)................................178, 179
LSR (Logical Shift Byte Data of Accumulator to
Right) .........................................181
LSRL (Logical Shift Long Word Data of
Accumulator to Right) ..................183
LSRW (Logical Shift Word Data of Accumulator
to Right)..............................185, 187
Linear Addressing
Linear Addressing Mode..............................11
Linear Addressing Mode
Linear Addressing Mode..............................11
M
M
MOV (Move Byte Data from Accumulator to
Destination).................................191
MOV (Move Byte Data from AH to
Memory) .....................................197
MOV (Move Byte Data from Source to
Accumulator)...............................189
374
MOV (Move Byte Data from Source to
Destination) ................................ 195
MOV (Move Byte Immediate Data to
Destination) ................................ 193
MOVB (Move Bit Data from Accumulator to Bit
Address)..................................... 200
MOVB (Move Bit Data from Bit Address to
Accumulator).............................. 198
MOVEA (Move Effective Address to
Destination) ................................ 202
MOVL (Move Long Word Data from
Accumulator to Destination)......... 206
MOVL (Move Long Word Data from Source to
Accumulator).............................. 204
MOVN (Move Immediate Nibble Data to
Accumulator).............................. 208
MOVS, MOVSI (Move String Byte with
Increment) .................................. 209
MOVSD (Move String Byte with
Decrement)................................. 211
MOVSW, MOVSWI (Move String Word with
Increment) .................................. 212
MOVSWI (Move String Word with
Decrement)................................. 214
MOVW (Move Immediate Word Data to
Destination) ................................ 219
MOVW (Move Immediate Word Data to
io) .............................................. 223
MOVW (Move Word Data from Accumulator to
Destination) ................................ 217
MOVW (Move Word Data from AH to
Memory) .................................... 224
MOVW (Move Word Data from Source to
Accumulator).............................. 215
MOVW (Move Word Data from Source to
Destination) ................................ 221
MOVX (Move Byte Data with Sign Extension
from Source to Accumulator) ....... 225
MUL (Multiply Byte Data of Accumulator and
Effective Address)....................... 228
MUL (Multiply Byte Data of Accumulator) 227
MULU (Multiply Unsigned Byte Data of
Accumulator and Effective
Address)..................................... 232
MULU (Multiply Unsigned Byte Data of
Accumulator).............................. 231
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective
Address)..................................... 234
MULUW (Multiply Unsigned Word Data of
Accumulator).............................. 233
MULW (Multiply Word Data of Accumulator
and Effective Address)................. 230
MULW (Multiply Word Data of
Accumulator).............................. 229
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
INDEX
MCU
Sample Hardware configuration of F2MC-16FX
Family MCU ...................................6
Memory Access
Direct Memory Access (DMA) ....................47
Memory Space
CPU Memory Space....................................10
Memory Space Divided into Banks and Values in
Each Register Bank ........................14
Multi-byte Data Layout in a Memory
Space ............................................15
Mode
Bank Addressing Mode ...............................12
Linear Addressing Mode..............................11
MOV
MOV Ri, ea Instruction Map
(First Byte = 7AH)........................360
Multi-byte Data
Access to Multi-byte Data............................16
Multi-byte Data Layout in a Memory
Space ............................................15
Multiple
Multiple Hardware Interrupts .......................63
Multiple Software Interrupts ........................63
N
N
NEG (Negate Byte Data of Destination) ......235
NEGW (Negate Word Data of
Destination).................................236
NOP (No Operation) .................................237
NOT (Not Byte Data of Destination)...........238
NOTW (Not Word Data of Destination) ......240
NRML (NORMALIZE Long Word) ...........241
NCC
Flag Change Inhibit Prefix Code (NCC) ........41
NMI
NMI Control Status Register (NMI)..............53
Non Maskable Interrupt
Hardware Exceptions (Non Maskable
Interrupts) .....................................67
O
O
OR (Or Byte Data of Destination and Source to
Destination).................................242
OR (Or Byte Data of Immediate Data and
Condition Code Register to Condition
Code Register) .............................244
ORL (Or Long Word Data of Destination and
Source to Destination) ..................246
ORW (Or Word Data of AH and
AL to AL) ...................................248
ORW (Or Word Data of Destination and Source
to Destination) .............................249
CM44-00203-3E
Odd Address
Odd Address Correction.............................. 82
Op-Code
Software Exceptions (Op-Code) .................. 66
P
P
POPW (Pop Registers from Stack
Memory) .................................... 256
POPW (Pop Word Data of Accumulator from
Stack Memory) ........................... 251
POPW (Pop Word Data of AH from Stack
Memory) .................................... 253
POPW (Pop Word Data of Program Status from
Stack Memory) ........................... 254
PUSHW (Push Registers to Stack
Memory) .................................... 260
PUSHW (Push Word Data of Inherent Register
to Stack Memory)........................ 258
PC
Program Counter (PC) ................................ 29
Prefix
Bank Select Prefix...................................... 38
Common Register Bank Prefix (CMR) ......... 40
Flag Change Inhibit Prefix Code (NCC) ....... 41
If Two or More Prefix Codes Appear in
Succession .................................... 43
Relationships between Instructions Rejecting
Interrupt Requests and Prefix
Codes ........................................... 42
Priority
Interrupt Acceptance Priority....................... 64
Processor Status
Processor Status (PS).................................. 24
Program Counter
Program Counter (PC) ................................ 29
PS
Processor Status (PS).................................. 24
R
R
RET (Return from Subroutine) .................. 262
RETI (Return from Interrupt) .................... 263
RETP (Return from Physical Address) ....... 265
ROLC (Rotate Byte Data of Accumulator with
Carry to Left) .............................. 267
RORC (Rotate Byte Data of Accumulator with
Carry to Right) ............................ 269
RAM
Calling General-purpose Registers in
RAM............................................ 36
Register Banks in RAM .............................. 34
Register
Bank Register ............................................ 31
Register Bank
FUJITSU MICROELECTRONICS LIMITED
375
INDEX
Memory Space Divided into Banks and Values in
Each Register Bank ........................14
Register Bank Pointer
Register Bank Pointer (RP) ..........................26
Register Banks
Register Banks in RAM...............................34
RP
Register Bank Pointer (RP) ..........................26
S
S
SBBS (Set Bit and Branch if Bit Set) ..........271
SCEQ, SCEQI (Scan String Byte until equal with
Increment)...................................272
SCEQD (Scan String Byte until equal with
Decrement)..................................274
SCWEQ, SCWEQI (Scan String Word until
equal with Increment)...................276
SCWEQD (Scan String Word until Equal with
Decrement)..................................278
SETB (Set Bit)..........................................280
SUB (Subtract Byte Data of Source from
Destination to Destination)............281
SUBC (Subtract Byte Data of AL from AH with
Carry to AL)................................283
SUBC (Subtract Byte Data of Effective Address
from Accumulator with Carry to
Accumulator)...............................284
SUBCW (Subtract Word Data of Effective
Address from Accumulator with Carry
to Accumulator) ...........................286
SUBDC (Subtract Decimal Data of AL from AH
with Carry to AL) ........................288
SUBL (Subtract Long Word Data of Source from
Destination to Destination)............289
SUBW (Subtract Word Data of AL from AH to
AL).............................................293
SUBW (Subtract Word Data of Source from
Destination to Destination)............291
SWAP (Swap Byte Data of
Accumulator)...............................294
SWAPW (Swap Word Data of
Accumulator)...............................295
Software
Multiple Software Interrupts ........................63
Software Exceptions (Op-Code) ...................66
Software Interrupt Operation........................62
Software Interrupts................................47, 61
Structure of the Software Interrupt
System ..........................................61
SSP
User Stack Pointer (USP) and System Stack
Pointer (SSP) .................................22
Symbol
Explanation of the Symbols Used in the
Instruction Lists ...........................317
376
Symbols (Abbreviations) Used in Detailed
Instructions................................... 81
System Stack Pointer
User Stack Pointer (USP) and System Stack
Pointer (SSP) ................................ 22
U
U
UNLINK (Unlink and Create New Stack
Frame) ....................................... 296
User Stack Pointer
User Stack Pointer (USP) and System Stack
Pointer (SSP) ................................ 22
USP
User Stack Pointer (USP) and System Stack
Pointer (SSP) ................................ 22
V
Vector
Interrupt Vector.......................................... 48
W
W
WBTc (Wait until Bit Condition
Satisfied) .................................... 297
X
X
XCH (Exchange Byte Data of Source to
Destination) ................................ 299
XCHW (Exchange Word Data of Source to
Destination) ................................ 301
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ................. 303
XORL (Exclusive Or Long Word Data of
Destination and Source to
Destination) ................................ 305
XORW (Exclusive Or Word Data of AH and AL
to AL) ........................................ 307
XORW (Exclusive Or Word Data of Destination
and Source to Destination) ........... 308
Z
Z
ZEXT (Zero Extend from Byte Data to Word
Data) .......................................... 310
ZEXTW (Zero Extend from Word Data to Long
Word Data)................................. 311
FUJITSU MICROELECTRONICS LIMITED
CM44-00203-3E
CM44-00203-3E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16FX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
March 2010 the third edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Sales Promotion Dept.
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