ESD8040 D

ESD8040
ESD Protection Diode
Low Capacitance Array for High Speed
Video Interfaces
The ESD8040 is designed specifically to protect HDMI and Display
Port Interfaces with full functionality ESD protection and back drive
current protection for VCC line. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flow−through style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed TMDS
lines.
•
•
MARKING
DIAGRAM
18
1
UDFN18
CASE 517CP
8040
M
G
Features
•
•
•
•
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Full Function HDMI / Display Port Solution
Single Connect, Flow through Routing for TMDS Lines
Low Capacitance (0.35 pF Max, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4
UL Flammability Rating of 94 V−0
This is a Pb−Free Device
8040MG
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Typical Applications
Device
Package
Shipping
ESD8040MUTAG
UDFN18
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• HDMI 1.3/1.4/2.0
• Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 3
1
Publication Order Number:
ESD8040/D
ESD8040
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 7
Pin 6
Pin 8
Pin 10 Pin 11 Pin 13 Pin 15
Pin 9
Pin 17
Center Pins, Pin 12, 14, 16, 18
Note: Common GND – Only minimum of 1 GND connection required
=
=
TMDS I/O Pins 1, 2, 4, 5, 7, 8, 10, 11
Non−TMDS I/O Pins 3, 6, 9, 13, 15, 17
Figure 1. Pin Schematic
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
18 GND
GND
17 I/O
16 GND
GND
15 I/O
14 GND
GND
13 I/O
12 GND
Figure 2. Pin Configuration
Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground.
Only minimum of one pin needs to be connected to ground for functionality of all pins.
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2
ESD8040
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
Symbol
Parameter
IPP
Maximum Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
RDYN
IPP
RDYN
Working Peak Reverse Voltage
VCL VBR VRWM
V
IR
IT
Maximum Reverse Leakage Current @ VRWM
VCL
Breakdown Voltage @ IT
RDYN
Test Current
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
IPP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
IT = 1 mA, I/O Pins 1, 2, 4, 5, 7, 8, 10, 11 to GND
IT = 1 mA, I/O Pins 3, 6, 9, 13, 15, 17 to GND
IR
VRWM = 3.3 V, I/O Pin to GND
Clamping Voltage (Note 1)
VC
IEC61000−4−2, ±8 kV Contact
Clamping Voltage TLP
(Note 2)
See Figures 9 through 12
VC
IPP = 8 A
IPP = −8 A
IPP = 16 A
IPP = −16 A
RDYN
Junction Capacitance
CJ
Typ
4.0
5.5
5.5
6.5
I/O Pin to GND
Reverse Leakage Current
Dynamic Resistance
Min
Max
Unit
3.3
V
V
1.0
mA
See Figures 3 and 4
V
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
9.2
−4.5
V
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
12.0
−8.0
I/O Pin to GND
GND to I/O Pin
0.33
0.45
VR = 0 V, f = 1 MHz between I/O Pins and GND
0.30
W
0.35
pF
1. For test procedure see Figures 7 and 8 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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ESD8040
90
0
80
−10
70
−20
VOLTAGE (V)
VOLTAGE (V)
60
50
40
30
20
−50
−60
−80
0
0
20
40
60
80
100
120
−90
−20
140
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 4. IEC61000−4−2 −8 kV Contact
Clamping Voltage (TMDS I/O Pins)
90
0
80
−10
70
−20
VOLTAGE (V)
50
40
30
20
140
−30
−40
−50
−60
−70
10
−80
0
−10
−20
0
Figure 3. IEC61000−4−2 +8 kV Contact
Clamping Voltage (TMDS I/O Pins)
60
VOLTAGE (V)
−40
−70
10
−10
−20
−30
0
20
40
60
80
100
120
−90
−20
140
0
20
40
60
80
100
120
TIME (ns)
TIME (ns)
Figure 5. IEC61000−4−2 +8 kV Contact
Clamping Voltage (Non−TMDS I/O Pins)
Figure 6. IEC61000−4−2 −8 kV Contact
Clamping Voltage (Non−TMDS I/O Pins)
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140
ESD8040
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 7. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 8. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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ESD8040
20
−20
10
8
−14
14
6
12
−12
6
−10
10
4
8
6
2
4
TMDS I/O Pins
2
4
6
8
10 12
14
VC, VOLTAGE (V)
16
4
−6
−4
2
TMDS I/O Pins
−2
Non−TMDS I/O Pins
2
−8
18
Non−TMDS I/O Pins
0
0
20
0
2
Figure 9. Positive TLP I−V Curve
NOTE:
4
6
8
10 12
14
VC, VOLTAGE (V)
16
0
20
18
Figure 10. Negative TLP I−V Curve
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 11. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 12 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 11. Simplified Schematic of a Typical TLP
System
Figure 12. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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EQUIVALENT VIEC (kV)
TLP CURRENT (A)
−16
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
8
16
0
0
10
−18
18
ESD8040
Without ESD8040
With ESD8040
Figure 13. HDMI 1.3/1.4 Eye Diagram with and without ESD8040. 3.4 Gb/s
Without ESD8040
With ESD8040
Figure 14. HDMI 2.0 Eye Diagram with and without ESD8040. 6.0 Gb/s
See application note AND9075/D for further description of eye diagram testing methodology.
Figure 15. RF Insertion Loss
Table 1. RF Insertion Loss: Application Description
Interface
Data Rate
(Gb/s)
Fundamental Frequency
(GHz)
3rd Harmonic Frequency
(GHz)
ESD8040 Insertion
LossJ(dB)
HDMI 1.3/1.4
3.4
1.7 (m1)
5.1 (m3)
HDMI 2.0
6.0
3.0 (m2)
9.0 (m4)
m1 = 0.144
m2 = 0.203
m3 = 0.369
m4 = 1.067
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ESD8040
HDMI Type−A
Connector
ESD8040
D2+
GND
D2−
GND
D1+
GND
D1−
D0+
D0CLK+
GND
D0−
CLK+
CEC
GND
SCL
CLK−
CEC
N/C (or HEC_DAT)
5V
SCL
SDA
GND
5V
HPD (and HEC_DAT)
Top layer
Other layer
Figure 16. HDMI Layout Diagram
Pin Description
current region in order to better protect the sensitive low
voltage, high−speed TMDS signals. The I/O pins for lower
speed lines have a higher breakdown voltage to
accommodate the higher voltages associated with the HPD,
CEC, I2C and VCC lines as well as the optional Ethernet pin
that can be implemented in HDMI1.4/2.0 applications.
I/O pins 1, 2, 4, 5, 7, 8, 10, and 11 are to be used for high
speed differential TMDS lines whereas I/O pins 3, 6, 9, 13,
15, and 17 are to be used for lower speed lines (I2C, CEC,
HPD, etc.). The ESD8040 was designed specifically for the
HDMI application. The I/O pins for TMDS lines have a
lower breakdown voltage and faster turn−on in the low
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ESD8040
ESD Protection Device Technology
• Low voltage punch through (LVPT): The key
advatange for this technology is a very low turn-on
voltage as shown in Figure 18. This technology
provides optimized protection for chipsets with small
geometries against recoverable failures due to voltage
peaks (also known as “soft failures”).
Figure 17. LVPT Operation Description
1.00E−01
1.00E−02
SCR
1.00E−03
LVPT
1.00E−04
Zener
I (A)
1.00E−05
1.00E−06
1.00E−07
1.00E−08
1.00E−09
1.00E−10
1.00E−11
0
1
2
3
4
5
6
7
V (V)
Figure 18. Low Current, DC, IV Characteristic Technology Comparison
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8
ESD8040
PACKAGE DIMENSIONS
UDFN18, 5.5x1.5, 0.5P/0.75P
CASE 517CP
ISSUE A
PIN ONE
REFERENCE
0.10 C
2X
ÉÉ
ÉÉ
0.10 C
2X
L2
A B
D
E
D3
DETAIL A
OPTIONAL
CONSTRUCTION
TOP VIEW
A
DETAIL B
0.05 C
ÉÉ
ÇÇ
ÇÇ
0.10 C
MOLD CMPD
DIM
A
A1
A3
b
D
D2
D3
E
E2
eA
eB
eC
L
L2
DETAIL B
NOTE 4
DETAIL A
D3
DETAIL C
EXPOSED Cu
(A3)
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. EXPOSED ENDS OF TERMINALS ARE
ELECTRICALLY ACTIVE.
L
C
SIDE VIEW
OPTIONAL
CONSTRUCTION
SEATING
PLANE
D2
eA
1
11
NOTE 5
E2
L
DETAIL C
18
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
5.50 BSC
0.35
0.45
0.10 REF
1.50 BSC
0.35
0.45
0.50 BSC
0.75 BSC
1.50 BSC
0.20
0.40
0.10 REF
12
18X
eB
eC
b
0.10
M
C A B
0.05
M
C
RECOMMENDED
SOLDERING FOOTPRINT*
END VIEW
NOTE 3
6X
BOTTOM VIEW
3X
6X
0.13
3X 0.50
0.45
0.75
PITCH
0.13
0.50
18X
0.50
1.80
1
17X
0.50
PITCH
0.30
1.50
PITCH
NOTE: CENTER PADS OPTIONAL
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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ESD8040/D
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