A8835 Datasheet

A8835
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
Features and Benefits
Description
▪ Eight-level, digitally-programmable current limits from
550 mA to 1.75 A
▪ Voltage sensing feedback before output diode for low
leakage
▪ No external pull-down resistors needed
▪ Power with 1 Li+ or 2 Alkaline/NiMH/NiCAD batteries
▪ Low quiescent current draw (1 μA max in shutdown mode)
▪ Zero-voltage switching for lower loss
▪ Adjustable output voltage
▪ Integrated IGBT driver with trigger
▪ Charge complete indication
▪ >75% efficiency
▪ Low-profile (0.75 mm high) 3 mm × 3 mm TDFN
10-contact package
The A8835 is a highly integrated IC that charges photoflash
capacitors for digital and film cameras. An integrated MOSFET
switch drives the transformer in a flyback topology. It also
features an integrated IGBT driver that facilitates the flash
discharge function and saves board space.
Applications:
The A8835 can be used with two Alkaline/NiMH/NiCAD or one
single-cell Li+ battery connected to the transformer primary.
Connect the VIN pin to a 3.0 to 5.5 V supply, which can be
either the system rail or the Li+ battery, if used.
▪ Digital camera flash
▪ Film camera flash
▪ Cell phone flash
▪ Emergency strobe light
Package: 10-contact TDFN with exposed
thermal pad (suffix EJ)
The CHARGE pin enables the A8835 and starts the charging
of the output capacitor. When the designated output voltage is
reached, the A8835 stops the charging until the CHARGE pin
¯ pin is an open-drain indicator of
is toggled again. The D̄¯¯Ō¯¯N̄¯Ē
when the designated output voltage is reached.
The peak current limit can be adjusted to eight different levels
between 550 mA and 1.75 A, by clocking the CHARGE pin.
This allows the user to operate the flash even at low battery
voltages.
The A8835 is available in a very low profile (0.75 mm)
10-contact 3 mm × 3 mm TDFN package, making it ideal
for space-constrained applications. It is lead (Pb) free, with
100% matte-tin leadframe plating and has an exposed pad for
enhanced thermal dissipation.
Approximate Scale
Typical Applications
VBATT 1.5 to 5.5 V
N =10.2
+
VBIAS 3.0 to 5.5 V
R4
T1
CIN
4.7 μF
C1
0.1 μF
100 k7
D1
R1
150 k7
1%
VOUT
COUT
100 μF
330 V
R2
VIN
CHARGE
150 k7
1%
SW
A8835
T1
C1
0.1 μF
R4
IGBTDRV
VIN
GND
FB
R3
1.20 k7
DONE
Figure 1. Typical circuit with separate power supply to transformer
TRIGGER
IGBTDRV
GND
To IGBT Gate
Figure 2. Typical circuit with single power supply
VOUT
R1
150 k7
150 k7
SW
A8835
R3
To IGBT Gate
D1
R2
1.20 k7
1%
TRIGGER
CIN
4.7 μF
100 k7
CHARGE
FB
DONE
A8835-DS, Rev. 1
VBIAS 3.0 to 5.5 V
COUT
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Selection Guide
Part Number
A8835EEJTR-T
Package
Packing*
10-pin TDFN
*Contact Allegro for additional packing options
1500 pieces/ 7-in. reel
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
VSW
DC voltage. (VSW is self-clamped by an internal
active clamp and is allowed to exceed 40 V during flyback spike durations. Maximum repetitive
energy during flyback spike: 0.5 μJ at frequency
≤ 400 kHz.)
–0.3 to 40
V
VIGBTDRV
–0.3 to VIN + 0.3
V
FB pin
VFB
–0.3 to VIN
V
All other pins
VX
–0.3 to 7
V
SW pin
IGBTDRV pin
Operating Ambient Temperature
TA
–40 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range E
Package Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
On 4-layer PCB, based on JEDEC standard
Rating Units
45
ºC/W
*Additional information is available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Functional Block Diagram
SW
VIN
Control Logic
DCM
Detector
(dV/dt = 0)
18 μs
HmL
Triggered Timer
40 V
DMOS
Q
S SET Q
R
CMP2
CLR Q
ILIM
Comparator
CHARGE
Adjustable
Reference
ILIM Decoder
Enable
Q
100 kΩ
Q
SET
CLR
S
FB
R
CMP1
1.2 V
DONE
VIN
TRIGGER
One-Shot
100 kΩ
20 kΩ
IGBTDRV
GND
Terminal List Table
Device Pin-out Diagram
Number
1,10
2
NC
IGBTDRV
VIN
GND
CHARGE
10 NC
9 FB
1
2
3
4
5
PAD
8 DONE
7 TRIGGER
6 SW
Name
NC
Function
No connection.
IGBTDRV IGBT driver gate drive output.
3
VIN
Input voltage. Connect to 3 to 5.5 V bias supply. Decouple VIN
voltage with 0.1 μF ceramic capacitor placed close to this pin.
4
GND
Device ground
5
CHARGE
6
SW
7
Charge enable and current limit serial programming pin. Set this
pin low to shut down the chip.
Drain connection of internal DMOS switch. Connect to transformer primary winding.
TRIGGER Strobe signal input
8
¯N̄¯Ē¯
D̄¯Ō
9
FB
–
PAD
Open collector output, pulls low when output reaches target
value and CHARGE is high. Goes high during charging or whenever CHARGE is low.
Output voltage feedback
Exposed pad for enhanced thermal dissipation. Connect to
ground plane.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
ELECTRICAL CHARACTERISTICS Valid at VIN = 3.3 V, TA = 25°C except
indicates specifications guaranteed from
−40°C to 85°C ambient, unless otherwise specified
Characteristics
Supply Voltage*
UVLO Enable Threshold
UVLO Hysteresis
Supply Current
Primary Side Current Limit
(ILIM clock input at CHARGE pin)
SW On Resistance
SW Leakage Current*
Switch Off Timeout
Switch On Timeout
CHARGE Input Current
CHARGE Input Voltage*
ILIM Clock High Time at CHARGE Pin
ILIM Clock Low Time at CHARGE Pin
Total ILIM Setup Time
Symbol
Test Conditions
Min.
VIN
Typ. Max. Units
3
–
5.5
V
2.55
–
–
–
–
1.58
–
–
–
–
–
–
–
–
2.65
150
1.5
1
0.01
1.75
1.58
1.4
1.22
1.05
0.86
0.7
0.55
0.27
2.75
–
–
10
1
1.93
–
–
–
–
–
–
–
–
V
mV
mA
μA
μA
A
A
A
A
A
A
A
A
Ω
–
–
1
μA
tOFF(Max)
tON(Max)
ICHARGE VCHARGE = VIN
VCHARGE(H)
–
–
–
2
18
18
33
–
–
–
–
–
μs
μs
μA
V
VCHARGE(L)
–
–
0.8
V
20
0.2
0.2
–
–
–
–
54
–
–
–
–
μs
μs
μs
μs
–
–
1
μA
–
–
100
mV
VUVLO
VIN rising
VUVLOHYS
IIN
Charging
Charging done
Shutdown (VCHARGE = 0 V, VTRIGGER = 0 V)
ISWLIM1
ISWLIM2
ISWLIM3
ISWLIM4
ISWLIM5
ISWLIM6
ISWLIM7
ISWLIM8
RDS(On)SW VIN = 3.3 V, ID = 800 mA
ISWLKG
tILIM1(H)
tILIM(H)
tILIM(L)
tILIM(SU)
D̄¯Ō
¯N̄¯Ē¯ Output Leakage Current*
IDONELKG
D̄¯Ō
¯N̄¯Ē
¯ Output Low Voltage*
FB Voltage Threshold*
FB Input Current
IGBT Driver
IGBTDRV On Resistance to VIN
IGBTDRV On Resistance to GND
TRIGGER Input Current
VDONE(L)
VFB
IFB
VSW = 35 V
Initial pulse
Subsequent pulses
32 μA into D̄¯Ō
¯N̄¯Ē¯ pin
1.187 1.205 1.223
–
–120
–
VFB = 1.205 V
RDS(On)I-V VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = VIN
RDS(On)I-G VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = 0 V
ITRIGGER VTRIGGER = VIN
VTRIGGER(H)
TRIGGER Input Voltage*
VTRIGGER(L)
Propagation Delay, Rising
tDr
Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V
Propagation Delay, Falling
tDf
Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V
Output Rise Time
tr
Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V
Output Fall Time
tf
Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V
dV/dt Threshold for ZVS Comparator
dV/dt
Measured at SW pin
*Specification over the range TA = –40°C to 85°C guaranteed by design and characterization.
–
–
–
2
–
–
–
–
–
–
5
6
33
–
–
30
30
70
70
20
–
–
–
–
0.8
–
–
–
–
–
V
nA
Ω
Ω
μA
V
V
ns
ns
ns
ns
V/μs
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Operation Timing Diagram
VUVLO
VIN
CHARGE
SW
Target VOUT
VOUT
DONE
TRIGGER
IGBTDRV
A
C
B
D
E
F
Explanation of Events:
A.
Start charging by pulling CHARGE to high, provided that VIN is above the VUVLO level.
B.
Charging stops when VOUT reaches the target voltage. D̄¯Ō
¯N̄¯Ē¯ goes low, to signal the
completion of the charging process.
C.
Start a new charging process with a low-to-high transition at the CHARGE pin.
D.
Pull CHARGE to low, to put the controller in low-power standby mode.
E.
Charging does not start, because VIN is below VUVLO level when CHARGE goes high.
F.
After VIN goes above VUVLO, another low-to-high transition at the CHARGE pin is
required to start charging.
IGBT Drive Timing Definition
TRIGGER
50%
tDr
IGBTDRV
10%
50%
tr
tDf
90%
90%
tf
10%
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Performance Characteristics
IGBT Drive waveforms are measured with R-C load (12 Ω, 6800 pF)
IGBT Drive Performance
tr
Rising Signal
VIGBTDRV
Symbol
C2
C3
t
Conditions
Parameter
VIGBTDRV
VTRIGGER
time
Parameter
tDr
tr
CLOAD
Rgate
Units/Division
1V
1V
50 ns
Value
22.881 ns
63.125 ns
6800 pF
12 Ω
C2
VTRIGGER
C3
t
tf
Falling Signal
Symbol
C2
C3
t
Conditions
Parameter
VIGBTDRV
VTRIGGER
time
Parameter
tDf
tf
CLOAD
Rgate
Units/Division
1V
1V
50 ns
Value
27.427 ns
65.529 ns
6800 pF
12 Ω
C2
VIGBTDRV
C3
VTRIGGER
t
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
A8835
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
Functional Description
Overview
lower current limit at low battery voltages.
The A8835 is a photoflash capacitor charger control IC with
adjustable input current limiting. It also integrates an IGBT
driver for strobe operation of the flash tube, dramatically saving
board space in comparison to discrete solutions for strobe flash
operation. The control logic is shown in the functional block
diagram.
Figure 4 shows the ILIM clock timing scheme protocol. The
total ILIM setup time, tILIM(SU) , denotes the time needed for the
decoder circuit to receive ILIM inputs and set ISWLIM . Apply current limit pulses during tILIM(SU) (54 μs) period.
The charging operation of the A8835 is started by a low-to-high
signal on the CHARGE pin, provided that VIN is above VUVLO
level. It is strongly recommended to keep the CHARGE pin at
logic low during power-up. When VIN exceeds the UVLO level,
a low-to-high transition on the CHARGE pin is required to start
the charging. The primary peak current is set by input programming signals from the CHARGE pin. When a charging cycle is
initiated, the transformer primary side current, IPrimary, ramps up
linearly at a rate determined by the combined effect of the battery
voltage, VBATT , and the primary side inductance, LPrimary. When
IPrimary reaches the current limit, ISWLIM , the internal MOSFET
is turned off immediately, allowing the energy to be pushed into
the photoflash capacitor, COUT, from the secondary winding.
The secondary side current drops linearly as COUT charges. The
switching cycle starts again, either after the transformer flux is
reset, or after a predetermined time period, tOFF(Max) (18 μs),
whichever occurs first.
The output voltage, VOUT, is sensed by a resistor string, R1, R2 ,
and R3 (see application circuit diagrams), connected across the
transformer secondary winding. This resistor string forms a voltage divider that feeds back to the FB pin. The resistors must be
sized to achieve a desired output voltage level based on a typical
value of 1.205 V at the FB pin. As soon as VOUT reaches the
desired value, the charging process is terminated. Toggling the
CHARGE pin can start a refresh operation.
Figure 5 shows the timing definition of the primary current
limiting circuit. At the end of the setup period, tILIM(SU) , primary
current starts to ramp up to the set ISWLIM. The ISWLIM setting
remains in effect as long as the CHARGE pin is high. To reset the
ILIM counter, pull the CHARGE pin low before clocking in the
new setting.
t ILIM(H) ≥ 0.2 μs
t ILIM(L) ≥ 0.2 μs
Clock input at
CHARGE pin
t ILIM1(H) =
first pulse width
t ILIM(SU) =
ILIM setup time
Subsequent rising
edges (0 to 7)
First rising
edge
0 μs
Switching
starts
54 μs
20 μs
Figure 4. ILIM Clock Timing Definition
Start ILIM counter
Reset ILIM counter
CHARGE
Four rising edges
within t ILIM(SU)
ISWLIM4 = 1.22 A
I SW
Input Current Limiting
The peak current limit can be programmed to eight different levels, from 1.75 A down to 550 mA, by clocking the CHARGE pin.
An internal digital circuit decodes the input clock signals, which
sets the switch current limit. This flexible scheme allows the user
to operate the flash circuit according to different battery input
voltages. The battery life can be effectively extended by setting a
Switching
starts
0 μs
20 μs
Switching
stops
54 μs
Figure 5. Current Limit Programming Example (ISWLIM4 selected).
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
A8835
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
VOUT
Timer Mode
After the first start-up or an ILIM decoder reset, each new current
limit can be set by sending a burst of pulses to the CHARGE pin.
The first rising edge starts the ILIM decoder, and up to 8 rising edges will be counted to set the ISWLIM level. The first pulse
width, tILIM1(H), must be at least 20 μs long. Subsequent pulses
(up to 7 more) can be as short as 0.2 μs. The last low-to-high
edge must arrive within 54 μs from the first edge. The CHARGE
pin will stay high afterwards.
Fast Charging Mode
VBAT
IIN
Figure 4. Timer mode and Fast Charging mode: t = 200 ms/div;
VOUT = 50 V/div; VBAT = 1 V/div.; IIN = 100 mA/div., VBAT = 3.6 V;
COUT = 20 μF / 330 V; and ISWlim ≈ 0.7 A.
Switch On-Time and Off-Time Control
The A8835 implements an adaptive on-time/off-time control. Ontime duration, ton , is equal to ton = ISWlim × LP / VBAT. Off-time
duration, toff , depends on the operating conditions during switch
off-time. The A8835 applies its two charging modes, Fast Charging mode and Timer mode, according to those conditions.
VSW
VBAT
VOUT
ISW
Timer Mode and Fast Charging Mode
The A8835 achieves fast charging times and high efficiency by
operating in discontinuous conduction mode (DCM) through
most of the charging process The relationship of Timer mode and
Fast Charging mode is shown in figure 4.
Figure 5. Expanded view of Timer mode: VOUT ≤ 14 V; t = 2 μs/div;
VBAT = 3.6 V; ISWlim = 1.05 A.
The IC operates in Timer mode when beginning to charge a completely discharged photoflash capacitor, usually when the output
voltage, VOUT, is less than approximately 15 to 20 V. Timer mode
is a fixed period, 18 μs, off-time control. One advantage of having Timer mode is that it limits the initial battery current surge
and thus acts as a “soft-start.” A time-expanded view of a Timer
mode interval is shown in figure 5.
As soon as a sufficient voltage has built up at the output capacitor, the IC enters Fast-Charging mode. In this mode, the next
switching cycle starts after the secondary side current has stopped
flowing, and the switch voltage has dropped to a minimum value.
A proprietary circuit is used to allow minimum-voltage switching, even if the SW pin voltage does not drop to 0 V. This enables
Fast-Charging mode to start earlier, thereby reducing the overall
charging time. Minimum-voltage switching is shown in figure 6.
During Fast-Charging mode, when VOUT is high enough (over
50 V), true zero-voltage switching (ZVS) is achieved. This
further improves efficiency as well as reduces switching noise. A
ZVS interval is shown in figure 7.
VSW
VBAT
VOUT
ISW
Figure 6. Minimum-voltage switching: VOUT ≥ 15 V; t =1 μs/div;
VBAT = 3.6 V; and ISWlim = 1.05 A.
VOUT
VSW
VSW
VBAT
VBAT
ISW
VOUT
ISW
Figure 7. ZVS voltage switching: VOUT = 120 V, t =0.2 μs/div,
VBAT = 3.6 V, ISWlim = 1.05 A.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Applications Information
Transformer Design
Turns Ratio. The minimum transformer turns ratio, N, (Second-
ary : Primary) should be chosen based on the following formula:
N≥
VOUT + VD_Drop
40 − VBATT
(1)
where:
VOUT (V) is the required output voltage level,
VD_Drop (V) is the forward voltage drop of the output diode(s),
VBATT (V) is the transformer battery supply, and
40 (V) is the rated voltage for the internal MOSFET switch,
representing the maximum allowable reflected voltage from the
output to the SW pin.
For example, if VBATT is 3.5 V and VD_Drop is 1.7 V (which could
be the case when two high voltage diodes were in series), and the
desired VOUT is 320 V, then the turns ratio should be at least 8.9.
In a worst case, when VBATT is highest and VD_Drop and VOUT are
at their maximum tolerance limit, N will be higher. Taking VBATT
= 5.5 V, VD_Drop = 2 V, and VOUT = 320 V × 102 % = 326.4 V as
the worst case condition, N can be determined to be 9.5.
In practice, always choose a turns ratio that is higher than the
calculated value to give some safety margin. In the worst case
example, a minimum turns ratio of N = 10 is recommended.
Primary Inductance. As a loose guideline when choosing the
primary inductance, LPrimary (μH), use the following formula:
LPrimary ≥
300 × 10−9 × VOUT
N × ISWLIM
(2)
.
Ideally, the charging time is not affected by transformer primary
inductance. In practice, however, it is recommended that a
primary inductance be chosen between 10 μH and 20 μH. When
LPrimary is lower than 10 μH, the converter operates at higher frequency, which increases switching loss proportionally. This leads
to lower efficiency and longer charging time. When LPrimary is
greater than 20 μH, the rating of the transformer must be dramatically increased to handle the required power density, and the
series resistances are usually higher. A design that is optimized to
achieve a small footprint solution would have an LPrimary of 12 to
14 μH, with minimized leakage inductance and secondary capacitance, and minimized primary and secondary series resistance.
See the table Recommended Components for more information.
Leakage Inductance and Secondary Capacitance
The transformer design should minimize the leakage inductance
to ensure the turn-off voltage spike at the SW node does not
exceed the 40 V limit. An achievable minimum leakage inductance for this application, however, is usually compromised by an
increase in parasitic capacitance. Furthermore, the transformer
secondary capacitance should be minimized. Any secondary
capacitance is multiplied by N2 when reflected to the primary,
leading to high initial current swings when the switch turns on,
and to reduced efficiency.
Input Capacitor Selection
Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, CIN. During initial timer mode
the device operates with 18 μs off-time. A typical input section
for a photoflash module with input filter inductor, or a test setup
with long connecting wires is shown in figure 12. The resonant
period caused by input filter inductor and capacitor should be at
least 2 times greater or smaller than the 18 μs timer period, to
reduce input ripple current during this period. See figure 13.
IVIN
IVIN
VOUT
VOUT
LIN
+
VBAT
CIN
A8835
Figure 12. Typical input section with input inductance
(inductance, LIN, may be an input filter inductor or
inductance due to long wires in test setup)
CIN = 4.7 μF
CIN = 10 μF
Figure 13. Effects of changing the values of CIN .
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
A8835
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
VBAT
VOUT
IBAT
Figure 14. Input current waveforms with Li+ battery connected by 5-in. wire
and decoupled by 4.7 μF capacitor. t = 500 ms/div; VBAT = 2 V/div;
VOUT = 100 V/div.; IBAT = 1 A/div.
VBAT
The resonant period is given by:
Tres = 2 ×
× (LIN × CIN ) ½
It is recommended to use at least 4.7 μF / 6.3 V to decouple the
battery input, VBAT, at the primary of the transformer. Decouple
the VIN pin using a 0.1 μF / 6.3 V bypass capacitor.
Output Diode Selection
Choose the rectifying diode(s), D1, to have small parasitic capacitance (short reverse recovery time) while satisfying the reverse
voltage and forward current requirements. The peak reverse
voltage of the diode, VDPeak, occurs when the internal MOSFET
switch is closed. It can be calculated as:
VDPeak = VOUT + N × VBAT
The peak current of the rectifying diode, IDPeak, is calculated as:
IDPeak = IPrimaryPeak / N
VOUT
IBAT
Figure 15. Input current waveforms with Li+ battery connected through
10 μH inductor and 4.7 μF capacitor. t = 500 ms/div; VBAT = 2 V/div;
VOUT = 100 V/div.; IBAT = 1 A/div.
VBAT
VOUT
IBAT
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
¯ signal trace and other
and SW pin. It is important that the D̄¯¯ Ō¯¯N̄¯Ē
signal traces be routed away from the transformer and other
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
breakdown failure of the circuit board.
Avoid locating the ground plane underneath transformer secondary and diode to minimize parasitic capacitance.
It is recommended to use a single high voltage resistor to sense
output voltage. Two series resistors, R1 and R2, may be used on
the high voltage VOUT side. Referring to figure 17, a parasitic
capacitor, CP1, across the R1-R2 junction and GND, can affect
output voltage accuracy due to slow voltage sensing at the FB
pin. A parasitic capacitor, CP2, between the R1-R2 junction and
VOUT , can affect output voltage accuracy due to overshoot in the
sensed voltage at the FB pin. Very small capacitance (≈1 pF) can
cause a significant error.
Figure 16. Input current waveforms with Li+ battery connected through
10 μH inductor and 10 μF capacitor. t = 500 ms/div; VBAT = 2 V/div;
VOUT = 100 V/div.; IBAT = 500 mA/div.
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Minimize parasitic capacitors with careful layout. The center pad
between R1 and R2 should be routed away from any GND and
other traces. Avoid placing the GND plane directly underneath
the center pad.
Place R1 and R2 as close as possible in a straight line as shown in
figure 18.
D1
CP2
R1
VOUT
+
COUT
R2
SW
R1
Do not locate areas
of the GND plane
underneath this zone
CP1
R2
FB
A8835
R3
R3
FB
Figure 17. Equivalent circuit with parasitic capacitors across feedback
divider.
GND
Figure 18. Recommended layout for feedback divider.
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Recommended Layout
VIN
C4
D1
X2
CIN
COUT
R1
VIN
TRIGGER
TRIGGER
CHARGE
CHARGE
DONE
R4
A8835
SW
Xenon+
R5
C3
R2
GND
Xenon–
IGBTDRV
DONE
FB
NC
NC
PAD
Xenon
Trigger
Rg1
Q1
R3
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Recommended Components
Component
C1, Input Capacitor
CIN, Input Capacitor
Rating
0.1 μF, ±10%, 16 V, X5R or
X7R ceramic capacitor (0603)
4.7 μF, ±10%, 10 V, X5R or
X7R ceramic capacitor (0805)
Part Number
Source
GRM188R71C104KA01D Murata
LMK212BJ475KG
Taiyo Yuden
COUT, Photoflash
Capacitor
330 V 100 μF (or 19 to 180 μF) EPH-331ELL101B131S
Chemi-Con
D1, Output Diode
2 x 250 V, 225 mA, 5 pF
Philips Semiconductor,
Fairchild Semiconductor
BAV23S
Instead of two resistors,
a single 300 kΩ resistor
with 350 V rating can be
used
150 kΩ each 1/4 W, ± 1%;
R1, R2, FB Resistors 1206, 0805, or 0603 resistors
rated for 150 V
R3, FB Resistor
T1, Transformer
Remarks
10 V minimum rating can
be used
1.2 kΩ 1/10 W ±1% (0603 or
0402)
LP = 14.2 μH, IP = 2 A,
N = 10
T-15-154M
Tokyo Coil
Suitable for ILIM from
0.55 to 1.75 A
LP = 7.4 μH, IP = 2 A,
N = 10
T-16-103A
Tokyo Coil
Suitable for ILIM from
1.2 to 1.75 A only
LP = 12.8 μH, IP = 1.5 A,
N=10
T-16-024A
Tokyo Coil
Suitable for ILIM from
0.55 to 1.4 A only
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Package EJ, 10-Contact TDFN
with Exposed Thermal Pad
0.30
3.00 ±0.15
0.85
0.50
10
10
3.00 ±0.15
1.65
3.10
A
1
2
1
11X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
C
2.38
PCB Layout Reference View
0.75 ±0.05
0.50
1
For Reference Only
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
2
0.40 ±0.10
1.65
B
10
2.38
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
14
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Photoflash Capacitor Charger
with Programmable Current Limit and IGBT Driver
A8835
Revision History
Revision
Rev. 1
Revision Date
April 19, 2012
Description of Revision
Miscellaneous format changes
Copyright ©2008-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
15
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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