CCD image sensors S11850-1106 S11851-1106 Improved etaloning characteristics, Constant element temperature control The S11850/11851-1106 are back-thinned CCD image sensors designed for spectrometers. Two types consisting of a low noise type (S11850-1106) and high-speed type (S11851-1106) are available with improved etaloning characteristics. The S11850/11851-1106 offer nearly flat spectral response characteristics with high quantum efficiency from the UV to near infrared region. A thermoelectric cooler is placed inside the package to keep the element temperature constant (approx. 5 °C) during operation. Features Applications Improved etaloning characteristics Spectrometers, etc. One-stage TE-cooled type (element temperature: approx. 5 °C) High sensitivity over a wide spectral range and nearly flat spectral response characteristics High CCD node sensitivity: 6.5 μV/e- (S11850-1106) 8 μV/e- (S11851-1106) High full well capacity, wide dynamic range (with anti-blooming function) Pixel size: 14 × 14 μm Improved etaloning characteristics Etaloning characteristics (typical example) (Ta=25 °C) 110 100 Etaloning-improved type 90 Relative sensitivity (%) Etaloning is an interference phenomenon that occurs when the light incident on a CCD repeatedly reflects between the front and back surfaces of the CCD while being attenuated, and causes alternately high and low sensitivity. When long-wavelength light enters a backthinned CCD, etaloning occurs due to the relationship between the silicon substrate thickness and the absorption length. The backthinned CCDs (S11850/S11851-1106) have achieved a significant improvement in etaloning by using a unique structure that is unlikely to cause interference. 80 70 60 Previous type 50 40 30 20 10 0 900 910 920 930 940 950 960 970 980 990 1000 Wavelength (nm) KMPDB0284EB www.hamamatsu.com 1 CCD image sensors S11850-1106, S11851-1106 Structure Parameter Image size (H × V) Pixel size (H × V) Number of total pixels Numbe of effective pixels Vertical clock phase Horizontal clock phase Output circuit Package Window S11850-1106 S11851-1106 28.672 × 0.896 mm 14 × 14 μm 2068 × 70 2048 × 64 2-phase 4-phase One-stage MOSFET source follower Two-stage MOSFET source follower 28-pin ceramic DIP (refer to dimensional outline) Quartz glass*1 *1: Hermetic sealing Absolute maximum ratings (Ta=25 °C, unless otherwise noted) Parameter Operating temperature*2 Storage temperature Output transistor drain voltage Symbol Topr Tstg S11850-1106 S11851-1106 Reset drain voltage Output amplifier return voltage Overflow drain voltage Vertical input source voltage Horizontal input source voltage Overflow gate voltage Vertical input gate voltage Horizontal input gate voltage Summing gate voltage Output gate voltage Reset gate voltage Transfer gate voltage Vertical shift register clock voltage VOD VRD Vret VOFD VISV VISH VOFG VIG1V, VIG2V VIG1H, VIG2H VSG VOG VRG VTG VP1V, VP2V VP1H, VP2H VP3H, VP4H Horizontal shift register clock voltage Min. -50 -50 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -10 -10 -10 -10 -10 -10 -10 -10 Typ. - Max. +50 +70 +30 +25 +18 +18 +18 +18 +18 +15 +15 +15 +15 +15 +15 +15 +15 Unit °C °C -10 - +15 V V V V V V V V V V V V V V V *2: Chip temperature Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the product within the absolute maximum ratings. Operating conditions (MPP mode, Ta=25 °C) Parameter Symbol Output transistor drain voltage Reset drain voltage Output amplifier return voltage*3 Overflow drain voltage Input source Test point Vertical input gate Horizontal input gate Overflow gate voltage Summing gate voltage High Low Output gate voltage Reset gate voltage Transfer gate voltage Vertical shift register clock voltage High Low High Low High Low High Horizontal shift register clock voltage Low Substrate voltage External load resistance *3: Output amplifier return voltage is a positive out of the sensor. Min. 23 11 S11850-1106 Typ. Max. 24 25 12 13 Min. 12 14 11 -9 -9 0 4 -6 4 4 -6 4 -9 4 -9 S11851-1106 Typ. Max. 15 18 15 16 1 2 12 13 VRD -8 -8 13 14 6 8 -5 -4 5 6 6 8 -5 -4 6 8 -8 -7 6 8 -8 -7 VOD VRD Vret 11 12 13 VOFD VISV, VISH VRD -9 -8 VIG1V, VIG2V -9 -8 VIG1H, VIG2H 0 12 13 VOFG 4 6 8 VSGH -6 -5 -4 VSGL 4 5 6 VOG 4 6 8 VRGH -6 -5 -4 VRGL 4 6 8 VTGH -9 -8 -7 VTGL 4 6 8 VP1VH, VP2VH -9 -8 -7 VP1VL, VP2VL VP1HH, VP2HH 4 6 8 4 6 VP3HH, VP4HH VP1HL, VP2HL -6 -5 -4 -6 -5 VP3HL, VP4HL 0 0 VSS 90 100 110 2.0 2.2 RL voltage with respect to Substrate voltage, but the current flows in Unit V V V V V V V V V V V V V 8 V -4 2.4 V kΩ the direction of flow 2 CCD image sensors S11850-1106, S11851-1106 Electrical characteristics (Ta=25 °C) Parameter Signal output frequency*4 Vertical shift register capacitance Horizontal shift register capacitance Summing gate capacitance Reset gate capacitance Transfer gate capacitance Charge transfer efficiency*5 DC output level*4 Output impedance*4 Power consumption*4 *6 Symbol fc CP1V, CP2V CP1H, CP2H CP3H, CP4H CSG CRG CTG CTE Vout Zo P Min. - S11850-1106 Typ. Max. 0.25 0.5 1200 160 10 10 60 0.99995 0.99999 17 18 10 4 Min. - 19 - - S11851-1106 Typ. Max. 5 10 1200 160 10 10 60 0.99995 0.99999 7 8 0.3 75 Unit MHz pF - pF 9 - pF pF pF V kΩ mW *4: The values depend on the load resistance. (S11850-1106: VOD=24 V, RL=100 kΩ, S11851-1106: VOD=15 V, RL=2.2 kΩ) *5: Charge transfer efficiency per pixel, measured at half of the full well capacity *6: Power consumption of the on-chip amplifier plus load resistance Electrical and optical characteristics (Ta=25 °C, unless otherwise noted) Parameter Saturation output voltage Full well capacity CCD node sensitivity*7 Dark current*8 Readout noise*9 Dynamic range*10 Symbol Vsat Vertical Horizontal Line binning Spectral response range Fw Sv DS Nr DR λ 11 Photoresponse nonuniformity* PRNU S11850-1106 Min. Typ. Max. Fw × Sv 50 60 250 300 5.5 6.5 7.5 50 500 6 15 41700 50000 200 to 1100 ±3 ±10 Min. 50 150 7 6520 - S11851-1106 Typ. Max. Fw × Sv 60 200 8 9 50 500 23 28 8700 200 to 1100 ±3 ±10 Unit V keμV/ee-/pixel/s e- rms nm % *7: The values depend on the load resistance. (S11850-1106: VOD=24 V, RL=100 kΩ, S11851-1106: VOD=15 V, RL=2.2 kΩ) *8: Dark current is reduced to half for every 5 to 7 °C decrease in temperature. *9: S11850-1106: Td=-40 °C, fc=20 kHz, S11851-1106: Td=25 °C, fc=2 MHz *10: Dynamic range = Full well capacity / Readout noise *11: Measured at one-half of the saturation output (full well capacity) using LED light (peak emission wavelength: 660 nm) Fixed pattern noise (peak to peak) Photoresponse nonuniformity = × 100 [%] Signal 3 CCD image sensors S11850-1106, S11851-1106 Spectral transmittance characteristics of window material Spectral response (without window)*12 (Typ. Ta=25 °C) 100 80 Transmittance (%) Quantum efficiency (%) 80 60 40 20 0 200 (Typ. Ta=25 °C) 100 60 40 20 400 600 800 1000 1200 Wavelength (nm) 0 200 300 400 500 600 700 800 900 1000 Wavelength (nm) KMPDB0316EA KMPDB0303EA *12: Spectral response with quartz glass is decreased according to the spectral transmittance characteristics of window material. Dark current vs. temperature (Typ.) 1000 Dark current (e-/pixel/s) 100 10 1 0.1 0.01 -50 -40 -30 -20 -10 0 10 20 30 40 50 Temperature (°C) KMPDB0304EB 4 CCD image sensors S11850-1106, S11851-1106 Device structure (conceptual drawing of top view in dimensional outline) S11850-1106 Effective pixels Thinning Effective pixels 22 21 20 19 18 17 16 2-bevel 23 2n signal output Thinning 64 15 Horizontal shift register 5 4 3 2 1 2 3 4 5 14 1024 13 V=64 H=2048 4-bevel 24 1 2 3 Horizontal shift register 4 5 6 7 8 9 10 n 4 blank pixels 2 signal output 11 12 4 blank pixels 6-bevel 6-bevel Note: When viewed from the direction of the incident light, the horizontal shift register is covered with a thick silicon layer (dead layer). However, long-wavelength light passes through the silicon dead layer and may possibly be detected by the horizontal shift register. To prevent this, provide light shield on that area as needed. KMPDC0402EA S11851-1106 Effective pixels Thinning Effective pixels 22 21 20 19 18 17 16 2-bevel 23 15 5 4 3 2 1 2 3 4 5 14 1024 13 4-bevel 24 1 2 3 Horizontal shift register 2 signal output Horizontal shift register n Thinning 64 4 blank pixels 6-bevel 4 5 6 n 7 8 2 signal output 9 10 11 V=64 H=2048 12 4 blank pixels 6-bevel Note: When viewed from the direction of the incident light, the horizontal shift register is covered with a thick silicon layer (dead layer). However, long-wavelength light passes through the silicon dead layer and may possibly be detected by the horizontal shift register. To prevent this, provide light shield on that area as needed. KMPDC0403EA 5 CCD image sensors S11850-1106, S11851-1106 Timing chart (line binning) Integration time (external shutter has to be open)* Tpwv 1 P1V Readout period (external shutter has to be closed)* Vertical binning period (external shutter has to be closed)* 2 3...69 70←64 + 6 (bevel) Tovr P2V, TG 4...2067 2068 Tpwh, Tpws Tovrh 1 P1H 2 3 P2H P3H P4H, SG Tpwr RG OS D1 D2 D19 D20 D3...D10, S1...S2048, D11...D18 * An external shutter is not necessarily required. When not using an external shutter, light entering during the vertical binning period and readout period is read out as signal. KMPDC0404EA Parameter P1V, P2V, TG P1H, P2H, P3H, P4H SG RG TG-P1H Pulse width*13 Rise and fall times*13 Pulse width*13 Rise and fall times*13 Pulse overlap time Duty ratio*13 Pulse width*13 Rise and fall times*13 Pulse overlap time Duty ratio*13 Pulse width Rise and fall times Overlap time Symbol Tpwv Tprv, Tpfv Tpwh Tprh, Tpfh Tovrh Tpws Tprs, Tpfs Tovrh Tpwr Tprr, Tpfr Tovr S11850-1106 Min. Typ. Max. 6 8 20 1000 2000 10 500 1000 40 50 60 1000 2000 10 500 1000 40 50 60 100 1000 5 1 2 - S11851-1106 Min. Typ. Max. 1 8 20 50 100 10 25 50 40 50 60 50 100 10 25 50 40 50 60 5 50 5 1 2 - Unit μs ns ns ns ns % ns ns ns % ns ns μs *13: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude. 6 CCD image sensors S11850-1106, S11851-1106 Dimensional outline (unit: mm, tolerance unless otherwise noted: ±0.15) 48.0 45.5 38.0 Window 35.0 33.02 Photosensitive area 28.672 × 0.896 2.5 Photosensitive surface Window 1 Index mark TE-cooler 0.25 ± 0.05 15 5.78 ± 0.3 7.0 10.0 14 4.67 ± 0.3 0.6 ± 0.1 3.82 ± 0.3* 2.54 * Distance from package bottom to photosensitive surface 3.0 1 12.45 12.7 28 5.0 ± 0.8 2.54 1.27 0.46 ± 0.05 33.02 ± 0.2 KMPDA0285EB 7 CCD image sensors S11850-1106, S11851-1106 Pin connections S11850-1106 Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol OS OD OG SG SS RD Th1 PP4H P3H P2H P1H IG2H IG1H OFG OFD ISH ISV SS RD P+ Th2 IG2V IG1V P2V P1V TG RG Function Output transistor source Output transistor drain Output gate Summing gate Substrate Reset drain Thermistor TE-coolerCCD horizontal register clock-4 CCD horizontal register clock-3 CCD horizontal register clock-2 CCD horizontal register clock-1 Test point (horizontal input gate-2) Test point (horizontal input gate-1) Overflow gate Overflow drain Test point (horizontal input source) Test point (vertical input source) Substrate Reset drain TE-cooler+ Thermistor Test point (vertical input gate-2) Test point (vertical input gate-1) CCD vertical register clock-2 CCD vertical register clock-1 Transfer gate Reset gate Remark (standard operation) RL=100 kΩ +24 V +5 V Same pulse as P4H GND +12 V -8 V -8 V +12 V +12 V Connect to RD Connect to RD GND +12 V -8 V -8 V Same pulse as P2V S11851-1106 Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol OS OD OG SG Vret RD Th1 PP4H P3H P2H P1H IG2H IG1H OFG OFD ISH ISV SS RD P+ Th2 IG2V IG1V P2V P1V TG RG Function Output transistor source Output transistor drain Output gate Summing gate Output amplifier return Reset drain Thermistor TE-coolerCCD horizontal register clock-4 CCD horizontal register clock-3 CCD horizontal register clock-2 CCD horizontal register clock-1 Test point (horizontal input gate-2) Test point (horizontal input gate-1) Overflow gate Overflow drain Test point (horizontal input source) Test point (vertical input source) Substrate Reset drain TE-cooler+ Thermistor Test point (vertical input gate-2) Test point (vertical input gate-1) CCD vertical register clock-2 CCD vertical register clock-1 Transfer gate Reset gate Remark (standard operation) RL=2.2 kΩ +15 V +5 V Same pulse as P4H +1 V +15 V -8 V -8 V +13 V +12 V Connect to RD Connect to RD GND +15 V -8 V -8 V Same pulse as P2V 8 CCD image sensors S11850-1106, S11851-1106 Specifications of built-in TE-cooler (Typ., vacuum condition) Parameter Internal resistance Maximum current*14 *15 Maximum voltage Maximum heat absorption*18 Symbol Condition Rint Ta=25 °C Imax Tc*16=Th*17=25 °C Vmax Tc*16=Th*17=25 °C Qmax Specification 1.6 1.8 3.5 4.0 Unit Ω A V W *14: If the current greater than this value flows into the thermoelectric cooler, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not the damage threshold value. To protect the thermoelectric cooler and maintain stable operation, the supply current should be less than 60% of this maximum current. *15: To ensure stable temperature control, ΔT (temperature difference between Th and Tc) should be less than 30 °C. If ΔT exceeds 30 °C, product characteristics may deteriorate. For example, the dark current uniformity may degrade. *16: Temperature of the cooling side of thermoelectric cooler *17: Temperature of the heat radiating side of thermoelectric cooler *18: This is a theoretical heat absorption level that offsets the temperature difference in the thermoelectric cooler when the maximum current is supplied to the unit. Specifications of built-in temperature sensor A thermistor chip is built in the same package with a CCD chip, and the CCD chip temperature can be monitored with it. A relation between the thermistor resistance and absolute temperature is expressed by the following equation. RT1 = RT2 × exp BT1/T2 (1/T1 - 1/T2) RT1: Resistance at absolute temperature T1 [K] RT2: Resistance at absolute temperature T2 [K] BT1/T2: B constant [K] The characteristics of the thermistor used are as follows. R298=10 kΩ B298/323=3900 K Precautions · If the thermoelectric cooler does not radiate away sufficient heat, then the product temperature will rise and cause physical damage or deterioration to the product. Make sure there is sufficient heat dissipation during cooling. As a heat dissipation measure, we recommend applying a high heat-conductivity material (silicone grease, etc.) over the entire area between the product and the heatsink (metallic block, etc.), and screwing and securing the product to a heatsink. · Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. · Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. · Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. · Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. Related information www.hamamatsu.com/sp/ssd/doc_en.html Precautions ∙ Disclaimer ∙ Image sensors Technical information ∙ FFT-CCD area image sensor/Technical information 9 CCD image sensors S11850-1106, S11851-1106 Driver circuit C11860 (sold separately) for CCD image sensor (S11850-1106) The C11860 is a driver circuit developed for the Hamamatsu CCD image sensor S11850-1106. Features Built-in 16-bit A/D converter The sensor circuit board and interface circuit board are connected using a flexible cable. Interface: USB 2.0 External synchronization capable Single power supply: +5 VDC Sensor cooling control (approx. +5 °C) Information described in this material is current as of September, 2015. Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always contact us for the delivery specification sheet to check the latest specifications. The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product use. Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission. www.hamamatsu.com HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184 U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 08807, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, 1 int. 6, 20020 Arese (Milano), Italy, Telephone: (39) 02-93581733, Fax: (39) 02-93581741 China: Hamamatsu Photonics (China) Co., Ltd.: B1201, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866 Cat. No. KMPD1132E03 Sep. 2015 DN 10