P4C167/P4C167L ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Separate Data I/O High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Three-State Output Low Power Operation Standard Pinout (JEDEC Approved) Single 5V±10% Power Supply – 20-Pin 300 mil DIP – 20-Pin 300 mil SOJ – 20-Pin LCC TTL Compatible Output Fully TTL Compatible Inputs Data Retention with 2.0V Supply (P4C167L Military) DESCRIPTION The P4C167/L are 16,384-bit high speed static RAMs organized as 16K x 1. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 10µA. Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. CMOS reduces power consumption to low levels. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS The P4C167/L are available in 20-pin 300 mil DIP, 20-pin 300 mil SOJ, and 20-pin LCC packages providing excellent board level densities. DIP (P2, C6) SOJ (J2) SIMILAR LCC (L9) Document # SRAM106 REV A 1 Revised October 2005 P4C167 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature GND VCC 0V 0V 0V 5.0V ± 10% 5.0V ± 10% 5.0V ± 10% Military –55°C to +125°C –40°C to +85°C Industrial 0°C to +70°C Commercial Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C167 Min Max 2.2 VCC +0.5 Test Conditions VIH Input High Voltage VIL Input Low Voltage VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = –18 mA VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min. VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. –0.5(3) 0.8 P4C167L Unit Min Max 2.2 VCC +0.5 V –0.5(3) 0.8 VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5 –0.5(3) VCC = Max. Mil. Input Leakage Current ILO Output Leakage Current ISB CE ≥ VIH Mil. Standby Power Supply VCC = Max ., Ind./Com’l. Current (TTL Input Levels) f = Max., Outputs Open ISB1 Standby Power Supply Current (CMOS Input Levels) VIN = GND to VCC VCC = Max., CE = VIH, VOUT = GND to VCC Com’l. Mil. Com’l. CE ≥ VHC Mil. VCC = Max., Ind./Com’l. f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC V 0.2 V –1.2 –1.2 V 0.4 0.4 V 0.2 2.4 ILI V –0.5(3) V 2.4 –10 –5 +10 +5 –5 n/a +5 n/a µA –10 –5 ___ ___ +10 +5 –5 n/a ___ ___ +5 n/a µA 20 n/a mA ___ ___ 15 ___ ___ 1.0 n/a mA 30 20 10 n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM106 REV A 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 10 P4C167 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current* Temperature Range Commercial –10 180 –12 170 –15 160 –20 155 –25 150 –35 N/A –45 N/A Industrial N/A 180 170 160 155 150 N/A mA Military N/A N/A 170 160 155 150 145 mA Unit mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL. DATA RETENTION CHARACTERISTICS (P4C167L Military Temperature Only) Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Conditons Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 10 CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Unit 15 600 900 µA 0 ns tRC§ ns *TA = +25¹C §tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM106 REV A Page 3 of 10 P4C167 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter –12 –10 –15 –20 –35 –25 –45 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 45 ns tAC Chip Enable Access Time 10 12 15 20 25 35 45 ns tOH Output Hold from Address Change 2 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time 12 10 5 15 6 0 0 10 20 8 10 0 12 0 15 35 25 20 17 12 0 45 0 25 ns 20 0 35 ns ns 45 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) TIMING WAVEFORM OF READ CYCLE NO. 2(6) Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. Document # SRAM106 REV A 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 of 10 P4C167 AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter –10 –12 –15 –20 –35 –25 –45 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 10 12 15 20 25 35 45 ns tCW Chip Enable Time to End of Write 8 10 2 15 20 25 30 ns tAW Address Valid to End of Write 8 10 12 15 20 25 30 ns tAS Address Set-up Time Write Pulse Width 0 0 0 0 0 0 0 ns 8 10 12 15 20 25 30 ns tAH Address Hold Time from End of Write 0 0 0 0 0 0 0 ns tDW Data Valid to End of Write 6 7 10 13 15 20 25 ns tDH Data Hold Time 0 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write tWP 6 0 7 0 8 0 12 0 15 0 17 0 20 0 ns ns WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. Document # SRAM106 REV A Page 5 of 10 P4C167 CE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C167/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, Document # SRAM106 REV A proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 6 of 10 P4C167 ORDERING INFORMATION SELECTION GUIDE The P4C167/L is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Package Speed (ns) 10 12 15 20 25 35 45 Plastic DIP -10PC -12PC -15PC -20PC -25PC N/A N/A Plastic SOJ -10JC -12JC -15JC -20JC -25JC N/A N/A Plastic DIP N/A -12PI -15PI -20PI -25PI -35PI N/A Plastic SOJ N/A -12JI -15JI -20JI -25JI -35JI N/A Military Temperature Side Brazed DIP N/A N/A -15CM -20CM -25CM -35CM -45CM LCC N/A N/A -15LM -20LM -25LM -35LM -45LM Military Processed* Side Brazed DIP N/A N/A -15CMB -20CMB -25CMB -35CMB -45CMB LCC N/A N/A -15LMB -20LMB -25LMB -35LMB -45LMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Document # SRAM106 REV A Page 7 of 10 P4C167 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q C6 SIDE BRAZED DUAL IN-LINE PACKAGE 20 (300 mil) Min Max 0.200 0.014 0.026 0.045 0.065 0.008 0.018 1.060 0.220 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - J2 SOJ SMALL OUTLINE IC PACKAGE 20 (300 mil) Min Max 0.120 0.140 0.080 0.014 0.020 0.008 0.013 0.496 0.512 0.050 BSC 0.335 0.347 0.292 0.300 0.267 BSC 0.025 - Document # SRAM106 REV A Page 8 of 10 P4C167 Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α L9 RECTANGULAR LEADLESS CHIP CARRIER 20 Min Max 0.060 0.075 0.050 0.066 0.022 0.028 0.280 0.305 0.150 BSC 0.075 BSC 0.305 0.420 0.440 0.250 BSC 0.125 BSC 0.440 0.050 BSC 0.020 REF 0.010 REF 0.045 0.055 0.045 0.055 0.075 0.098 4 6 P2 PLASTIC DUAL IN-LINE PACKAGE 20 (300 mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.070 0.008 0.014 0.980 1.060 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM106 REV A Page 9 of 10 P4C167 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM106 P4C167 / P4C167L ULTRA HIGH SPEED 16K x 1 STATIC CMOS RAMS REV. ISSUE DATE ORIG. OF CHANGE OR 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid Document # SRAM106 REV A DESCRIPTION OF CHANGE Page 10 of 10