TVS Diode Arrays (SPA® Diodes) Low Capacitance ESD Protection - SP3012 Series SP3012 Series 0.5pF Diode Array RoHS Pb GREEN Description The SP3012 integrates either 4 or 6 channels of ultra low capacitance rail-to-rail diodes and an additional zener diode to provide protection for electronic equipment that may experience destructive electrostatic discharges (ESD). These robust devices can safely absorb repetitive ESD strikes above the maximum level specified in the IEC61000-4-2 international standard (±8kV contact discharge) without performance degradation. The extremely low loading capacitance also makes it ideal for protecting high speed signal lines such as USB3.0, HDMI, USB2.0, and eSATA. Pinout SP3012-04UTG 6 7 8 9 Features 10 *Pins 6, 7, 9, 10 are not internally connected but should be connected to the trace. 5 8 4 3 2 SP3012-06UTG • ESD, IEC61000-4-2, ±12kV contact, ±25kV air • Low leakage current of 1.5μA (MAX) at 5V 1 • EFT, IEC61000-4-4, 40A (tP=5/50ns) 14 • Lightning, IEC61000-4-5, 4A (tP=8/20μs) •Small form factor μDFN (JEDEC MO229) package provides flow through routing to simplify PCB layout *Pins 1, 2, 3, 4, 5, 6, 7 are not internally connected but should be connected to the opposite pin with the PCB trace. 7 1 • Low capacitance of 0.5pF (TYP) per I/O Applications Functional Block Diagram SP3012-04UTG Pin 1 Pin 2 Pin 4 Pin 5 • LCD/PDP TVs • Set Top Boxes • External Storages • Smartphones • DVD/Blu-ray Players • Ultrabooks/Notebooks • Desktops • Digital Cameras • MP3/PMP Application Example for USB3.0 GND (Pins 3,8) SP3012-06UTG USB Port USB Controller VBUS SSTX+ SSTX- Additional Information IC SSRX+ SSRXGND Datasheet Resources Samples SP3012-06UTG D+ D- Life Support Note: Not Intended for Use in Life Support or Life Saving Applications The products shown herein are not designed for use in life sustaining or life saving applications unless otherwise expressly indicated. © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 04/24/13 Signal GND TVS Diode Arrays (SPA® Diodes) Low Capacitance ESD Protection - SP3012 Series Absolute Maximum Ratings Parameter Value Peak Current (tp=8/20μs) TOP TSTOR Units 4.0 A Operating Temperature –40 to 125 °C Storage Temperature –55 to 150 °C SP3012 Symbol IPP CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Characteristics (TOP=25ºC) Parameter Symbol Test Conditions Min Typ Max Units Reverse Standoff Voltage VRWM IR ≤ 1µA 5.0 V Reverse Leakage Current ILEAK VR=5V, Any I/O to GND 1.5 µA Clamp Voltage1 Dynamic Resistance RDYN ESD Withstand Voltage1 VESD Diode Capacitance IPP=1A, tp=8/20µs, Fwd VC 1 Diode Capacitance1 6.6 V IPP=2A, tp=8/20µs, Fwd 7.0 V (VC2 - VC1) / (IPP2 - IPP1) 0.4 Ω IEC61000-4-2 (Contact) ±12 kV IEC61000-4-2 (Air) ±25 kV CI/O-GND Reverse Bias=0V, f=1 MHz 0.5 pF CI/O-/O Reverse Bias=0V, f=1 MHz 0.3 pF Note: Parameter is guaranteed by design and/or device characterization. 1 Capacitance vs. Bias Voltage Insertion Loss (S21) I/O to GND 0 1.0 -3 -6 Attenuation (dB) Capacitance (pF) 0.8 -9 -12 0.6 -15 -18 0.4 -21 -24 0.2 -27 0.0 -30 0.0 2.0 1.0 3.0 Bias Voltage (V) 4.0 Clamping Voltage vs. IPP TLP Current (A) 8.0 Clamp Voltage (V) 6.0 4.0 2.0 1 2 Frequency (MHz) 1000 Transmission Line Pulsing(TLP) Plot 10.0 0.0 100 5.0 Current (A) 3 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 TLP Voltage (V) 9 10 11 © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 04/24/13 TVS Diode Arrays (SPA® Diodes) Low Capacitance ESD Protection - SP3012 Series Pulse Waveform Power Derating Curve 110 110% 100 % of Rated Power or IPP 100% 90% Percent of IPP 80% 70% 60% 50% 40% 30% 90 80 70 60 50 40 30 20% 20 10% 10 0% 0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0 25 50 Time (μs) 75 100 Ambient Temperature-TA 125 150 (oC) Soldering Parameters Pb – Free assembly Pre Heat - Temperature Min (Ts(min)) 150°C - Temperature Max (Ts(max)) 200°C - Time (min to max) (ts) 60 – 180 secs Average ramp up rate (Liquidus) Temp (TL) to peak 3°C/second max TS(max) to TL - Ramp-up Rate 3°C/second max Reflow - Temperature (TL) (Liquidus) 217°C - Temperature (tL) 60 – 150 seconds Peak Temperature (TP) 260+0/-5 °C Time within 5°C of actual peak Temperature (tp) 20 – 40 seconds tP TP Temperature Reflow Condition Critical Zone TL to TP Ramp-up TL TS(max) tL Ramp-do Ramp-down Preheat TS(min) tS 25 time to peak temperature Time Ordering Information Ramp-down Rate 6°C/second max Part Number Package Marking Min. Order Qty. Time 25°C to peak Temperature (TP) 8 minutes Max. SP3012-04UTG µDFN-10 V*4 3000 Do not exceed 260°C SP3012-06UTG µDFN-14 V*6 3000 Part Numbering System Product Characteristics Lead Plating Pre-Plated Frame Lead Material Copper Alloy Lead Coplanarity 0.0004 inches (0.102mm) Substitute Material Silicon Body Material Molded Epoxy Flammability UL 94 V-0 Notes : 1. All dimensions are in millimeters 2. Dimensions include solder plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. Blo is facing up for mold and facing down for trim/form, i.e. reverse trim/form. 5. Package surface matte finish VDI 11-13. © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 04/24/13 SP 3012 – xx U T G TVS Diode Arrays (SPA Diodes) G= Green T= Tape & Reel Series Number of Channels Package µDFN-10 (2.5x1.0mm) µDFN-14 (3.5x1.35mm) 04 = 4 channel 06 = 6 channel Part Marking System V* * Number of Product Series Channels V = SP3012 Assembly Site 4 = 4 channel 6 = 6 channel TVS Diode Arrays (SPA® Diodes) Low Capacitance ESD Protection - SP3012 Series Application Information Signal Integrity of High-Speed Data Interfaces Figure 1: PCB Layout of the SP3012-06UTG for USB 3.0 Adding external ESD protection to a high-speed data port is not trivial for a variety of reasons. J1 1. ESD protection devices will add parasitic capacitance to each data line from line to GND and line to line causing impedance mismatches between the differential pairs. This ultimately affects the signal eye-diagram and whether or not the transceiver can distinguish a “1” from a “0”. 2. ESD devices should be placed as close as possible to the port being protected to maximize their effect (i.e. clamping capability) and minimize the effect that PCB trace inductance can have during an ESD transient. Depending on the package size and pinout this could be challenging and the bigger the package, the larger the land pattern must be, which adds more parasitic capacitance. U1 Figure 2 shows the USB 3.0 eye diagram that resulted from the PCB layout above with the SP3012-06UTG soldered on the landing pattern. 3. Stub traces can add another element of discontinuity adversely affecting signal integrity so ESD protection is best employed when it’s “overlaid” on the data lines or when the signals can simply pass underneath the device. 500 Taking all of this into account Littelfuse developed the SP3012 Series which was designed specifically for protection of high-speed data ports such as HDMI 1.3/1.4 and USB 3.0. They present less than 0.5pF from line to GND and only 0.3pF from line to line minimizing impedance mismatch between the differential pairs. Furthermore, the SP3012 is rated up to ±12kV (contact discharge) which far exceeds the maximum requirement of the IEC 61000-4-2 standard. There are two options available (4 channel and 6 channel) and both are housed in leadless µDFN packages so the data lines can pass directly underneath the device to reduce discontinuities and maintain signal integrity. 0 Wfrms:500 -500 Base: 27.0000 ns Scale:33.0 ps/div Figure 2: USB 3.0 Eye Diagram with the SP3012-06UTG Using a similar layout as above, Figure 3 shows the eye diagram that resulted using the SP3012-04UTG to protect the Super-Speed data lines and the SP3003-02UTG to protect the legacy data pair. 500 USB 3.0 Eye Diagram Data Figure 1 shows the layout used for the SP3012-06UTG in a USB 3.0 application. The traces routed toward the top are the two legacy USB 2.0 lines (D+/D-) that run at the slower speed of 480Mbps and therefore are not as critical as the 5Gbps Super-Speed traces. 0 Wfrms:850 -500 Base: 27.0000 ns Scale:33.0 ps/div Figure 3: USB 3.0 Eye Diagram with the SP3012-04UTG © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 04/24/13 TVS Diode Arrays (SPA® Diodes) Top View Low Capacitance ESD Protection - SP3012 Series A D E B Side View Package Dimensions— µDFN-10 (2.5x1.0x0.5mm) 0.05 C JEDEC Top View Symbol A D B 0.05 C 0.05 C b1 C Millimeters A 0.48 0.515 0.55 M C 0.019 0.050.020 0.021 A1 0.00 -- 0.05 0.000 Min 0.022 0.125 Ref 0.005 Ref Bottom View b 0.15 0.20 0.25 b1 0.35 0.40 0.45 0.008 0.014 R0.125 0.016 D 2.40 2.50 2.60 0.094 0.098 0.102 E 0.90 1.00 1.10 0.035 0.039 0.043 0.006 L 0.50 BSC 0.30 0.365 0.43 Millimeter C (0.034) (0.875) 0.10 M C A B G 0.008 0.20 0.05 M C P 0.020 0.50 P1 0.039 1.00 X 0.008 0.20 X1 0.016 0.40 Y 0.027 0.675 Y1 (0.061) (1.55) Z 0.061 1.55 0.012 0.018 0.020 BSC 2xR0.075mm (7x) 0.014 0.016 0.012 e Soldering Pad Layout Dimensions Inch R0.125 Inches M C A B Max 0.10Nom Max b Bottom View 0.05 C b1 Nom L A1 A3 A b Min e Side View Seating Plane C A3 E A1 A3 A µDFN-10 Seating(2.5x1.0x0.5mm) Plane MO-229 Package Recomended Soldering Pad Layout P1 P Y (Y1) Z (C) G X X1 Alternative Soldering Pad Layout L P1 P 2xR0.075mm (7x) e Y (Y1) Z (C) G Recomended Soldering Pad Layout X P1 P Embossed Carrier Tape & Reel YSpecification— µDFN-10 (Y1) Z (C) G P0 T D 0 P1 P2 E X User Feeding Direction B0 F W X1 D1 A0 K0 5º Max © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 04/24/13 5º Max Pin 1 Location Package µDFN-10 (2.5x1.0x0.5mm) Symbol Millimeters A0 1.30 ± 0.10 B0 2.83 ± 0.10 D0 Ø 1.50 + 0.10 D1 Ø 1.00 + 0.25 E 1.75 ± 0.10 F 3.50 ± 0.05 K0 0.65 ± 0.10 P0 4.00 ± 0.10 P1 4.00 ± 0.10 P2 2.00 ± 0.05 T 0.254 ± 0.02 W 8.00 + 0.30 /- 0.10 X1 TVS Diode Arrays (SPA® Diodes) Low Capacitance ESD Protection - SP3012 Series Package Dimensions — µDFN-14 (3.5x1.35x0.5mm) µDFN-14 (3.5x1.35x0.5mm) Top View A D JEDEC MO-229 Millimeters E PIN 1 Index Area Symbol 1 2 3 4 Seating Plane A1 A C Nom Max Min Nom Max A 0.45 0.50 0.55 0.018 0.020 0.022 A1 0.00 0.02 0.05 0.000 0.001 0.002 B Side View A2 0.203 Ref A2 b Bottom View 0.008 Ref b 0.15 0.20 0.25 0.006 0.008 0.012 D 3.40 3.50 3.60 0.134 0.138 0.142 D2 - - - - - - E 1.25 1.35 1.45 0.050 0.054 0.058 E1 - - - - - - 0.500 BSC e L Pin 1 Identification Chamfer 0.10X45º Inches Min 0.25 0.020 BSC 0.30 0.35 0.010 0.012 0.014 Notes: 1. Dimension and tolerancing comform to ASME Y14.5M-1994. 2. Controlling dimensions: Millimeter. Converted Inch dimensions are not necessarily exact. Recomended Soldering Pad Layout Soldering Pad Layout Dimensions Symbol Inches Millimeters Millimeter Symbol D Inches Min Nom Max Min Nom Max 3.29 3.30 3.31 0.1295 0.1299 0.1303 E 1.44 1.45 1.46 0.0567 0.0571 0.0575 b 0.29 0.30 0.31 0.0114 0.0118 0.0122 L 0.39 0.40 0.41 0.0154 0.0158 0.0161 0.50 typ e 0.020 typ s 0.19 0.20 0.21 0.0075 0.0078 0.0083 s1 0.64 0.65 0.66 0.0252 0.0256 0.0260 Embossed Carrier Tape & Reel Specification — µDFN-14 P1 P2 P0 D0 User Feeding Direction E F W Pin 1 Location D1 A0 T K0 B0 Symbol Millimeters A0 1.58 ± 0.10 B0 3.73 ± 0.10 D0 0.60 + 0.05 D1 Ø 0.60 + 0.05 E 1.75 ± 0.10 F 5.50 ± 0.05 K0 0.68 ± 0.10 P0 2.00 ± 0.05 P1 4.00 ± 0.10 P2 4.00 ± 0.10 T 0.28 ± 0.02 W 12.00 + 0.30 /- 0.10 © 2013 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 04/24/13