E12702A2Z

SP12T Antenna Switch Module for 7TRx/2Tx/3Rx
CXM3583AUR
Description
The CXM3583AUR is a SP12T antenna switch module for GSM/UMTS/CDMA/LTE multi-mode handset.
The CXM3583AUR has a built-in dual low pass filter and a +1.8 V CMOS compatible decoder.
The Sony GaAs junction gate PHEMT (JPHEMT) MMIC process is used for low insertion loss and high linearity.
The device has low BOM with no DC blocking Capacitor.
Features

Low Insertion Loss:
0.50 dB (Typ.) TRx (Cellular Band)
0.60 dB (Typ.) TRx (IMT Tx Band)

High Linearity:
IIP3 = 68 dBm

Low Voltage Operation:
VDD = 2.5 V

No DC Blocking Capacitors except sourcing DC bias.

Small Package Size:

Lead-Free and RoHS Compliant.
UQFN-30P (3.0 mm × 3.8 mm × 0.625 mm Max.)
Structure
GaAs Junction Gate PHEMT (JPHEMT) MMIC Switch, CMOS Decoder.
Moisture Sensitivity
Moisture Sensitivity Level for this part is MSL = 2
This IC is ESD sensitive device. Special handling precautions are required.
1
CXM3583AUR
Preliminary
Block Diagram
SP12T Antenna Switch Module
TRx1
TRx2
TRx3
TRx4
Ant
TRx5
TRx6
TRx7
LPF1
Decoder Logic
Tx1
Tx2
LPF2
Rx1
Rx2
Rx3
SP12T 7TRx/2Tx/3Rx
*Built-in SW Control Circuit
ANT
F1
F2
F13
F3
F14
F4
F15
F5
F16
F7
F6
F17
F18
F8
F19
F9
F20
F11
F10
F21
F23
F22
LPF1
TRx1
TRx2
TRx3
TRx4
TRx5
TRx6
2
TRx7
Rx1
Rx2
Rx3
F12
Tx1
F24
LPF2
Tx2
CXM3583AUR
Preliminary
Truth Table
CTL
Active
State
Switch State (*1)
State
Path
A B C D F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24
1
TRx1 H L H L H L L
L
L
L L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
2
TRx2 H H H L L H L
L
L
L L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
3
TRx3 H L H H L
L H L
L
L L
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
4
TRx4 H H H H L
L L H L
L L
L
L
L
L
L
H
H
H
L
H
H
H
H
H
H
H
H
5
TRx5 H L L H L
L L
L H L L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
H
6
TRx6 H H L H L
L L
L
L H L
L
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
7
TRx7 L L L H L
L L
L
L
L H L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
8
Rx1 L L H L L
L L
L
L
L L H L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
9
Rx2 L H H L L
L L
L
L
L L
L H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
10
Rx3 L H L L L
L L
L
L
L L
L
L
H
L
L
H
H
H
H
H
H
H
H
H
L
H
H
11
Tx1 H H L L L
L L
L
L
L L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
12
Tx2 H L L L L
L L
L
L
L L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
(*1) State ”L” means a switch “OFF”, State ”H” means a switch “ON”
3
CXM3583AUR
Preliminary
GND
GND
Tx2
GND
15
Tx1
GN
Pin Configuration
14
13
12
11
10
GND 16
9
GN
Rx3 17
8
ANT
7
GN
6
TRx6
5
TRx
4
TRx
TRx1 22
3
TRx
TRx2 23
2
GN
GND 24
1
GN
GND 18
UQFN-30P PKG
UQFN-30P PKG
(3.0
mm × 3.8 mm
(3.0mm x 3.8mm
× 0.625 mm Max.)
Rx2 19
Rx1 20
27
4
CTLD
CTLC
28
29
30
GND
26
CTL
25
VDD
TRx7 21
CTLB
x 0.60mm Max.)
Top View
CXM3583AUR
Preliminary
DC Bias Conditions
Ta=25 ℃
Parameter
VDD
Vctl(H)
Vctl(L)
Min.
Typ.
Max.
Unit
2.5
1.35
0
2.8
1.8
-
3.3
3.1
0.45
V
V
V
Absolute Maximum Ratings
◆ Supply voltage
VDD
4
V
(Ta = 25 °C)
◆ Control voltage
Vctl
4
V
(Ta = 25 °C)
[Tx1]
36
dBm
(Duty cycle = 12.5  to 50 )
(Ta = 25 °C)
[Tx2]
34
dBm
(Duty cycle = 12.5  to 50 )
(Ta = 25 °C)
[TRx]
32
dBm
(Ta = 25 °C)
[Rx]
13
dBm
(Ta = 25 °C)
◆ Operating temperature
Topr
–35 to +90
°C
◆ Storage temperature
Tstg
–65 to +150
°C
◆ Maximum input
5
CXM3583AUR
Preliminary
Electrical Characteristics
VDD = 2.5 V,
Item
Symbol
Path
Ant - TRx1
Ant - TRx2
Ant - TRx3
Ant - TRx4
Insertion Loss
IL
Ant - TRx5
Vctl = 1.80 V,
Ta = 25 °C
Condition
Min
Typ
Max
*1, *2, *3
-
0.44
0.54
*4
-
0.71
0.86
*5
-
0.78
0.93
*6
-
0.86
1.06
*7
-
1.02
1.22
*1, *2, *3
-
0.48
0.58
*4
-
0.72
0.87
*5
-
0.78
0.93
*6
-
0.87
1.07
*7
-
1.00
1.20
*1, *2, *3
-
0.44
0.54
*4
-
0.71
0.86
*5
-
0.77
0.92
*6
-
0.85
1.05
*7
-
0.98
1.18
*1, *2, *3
-
0.50
0.60
*4
-
0.87
1.02
*5
-
0.95
1.10
*6
-
1.08
1.28
*7
-
1.29
1.49
*1, *2, *3
-
0.52
0.62
*4
-
0.99
1.14
*5
-
1.09
1.24
*6
-
1.22
1.42
*7
-
1.44
1.64
*1, *2, *3
-
0.53
0.63
*4
-
0.98
1.13
*5
-
1.09
1.24
*6
-
1.24
1.44
*7
-
1.49
1.69
*1, *2, *3
-
0.45
0.55
*4
-
0.71
0.86
*5
-
0.78
0.93
*6
-
0.86
1.01
*7
-
1.00
1.20
Ant - Tx1
*8
-
1.02
1.17
Ant - Tx2
*9
-
1.05
1.25
*10
-
0.75
0.85
*11
-
1.11
1.26
*10
-
0.75
0.85
*11
-
1.09
1.24
*10
-
0.74
0.84
*11
-
1.00
1.15
Ant - TRx6
Ant - TRx7
Ant - Rx1
Ant - Rx2
Ant - Rx3
(*)Electrical Characteristics are measured with all RF ports terminated in 50 Ω.
6
Unit
dB
CXM3583AUR
Preliminary
Electrical Characteristics
VDD = 2.5 V,
(*)Electrical Characteristics are measured with all RF ports terminated in 50 Ω.
7
Vctl = 1.80 V,
Ta = 25 °C
CXM3583AUR
Preliminary
Electrical Characteristics
Corresponding Band of TRx (UMTS/CDMA)
*1: Pin = 26 dBm,
452 MHz to 468 MHz(Band Class 5)
*2: Pin = 25 dBm,
704 MHz to 787 MHz(Band 13, Band 17)
*3: Pin = 26 dBm,
824 MHz to 960 MHz(Band 5, Band 8)
*4: Pin = 26 dBm,
1710 MHz to 1990 MHz (Band 1 Tx, Band 2 Tx, Band 3 Tx, Band4 Tx)
*5: Pin = 10 dBm,
2110 MHz to 2170 MHz (Band 1 Rx, Band 4 Rx)
*6: Pin = 26 dBm,
2300 MHz to 2400 MHz (Band 40)
*7: Pin = 26 dBm,
2500 MHz to 2690 MHz (Band 7)
*8: Pin = 35 dBm,
824 MHz to 915 MHz (GSM850/900 Tx)
*9: Pin = 32 dBm,
1710 MHz to 1910 MHz (GSM1800/1900 Tx)
*10: Pin = 10 dBm,
869 MHz to 960 MHz (GSM850/900 Rx)
*11: Pin = 10 dBm,
1805 MHz to 1990 MHz (GSM1800/1900 Rx)
*12A: Measured with the recommended Circuit1, Circuit2
*12B: Measured with the recommended Circuit3
(*)Electrical characteristics are measured with all RF ports terminated in 50 .
IMD Condition
Band
Band I
Band II
Band V
fRx
on TRx
fRx
+20 dBm on TRx
2140 MHz
1960 MHz
880 MHz
1950 MHz
1880 MHz
835 MHz
fBlocker
–15 dBm on Ant
IMD Condition
IMD2 (fRx-fTx)
190 MHz
IMD2 (fRx-fTx)
4090 MHz
IMD3 (2fTx-fRx)
1760 MHz
IMD3 (2fTx-fRx)
6040 MHz
IMD2 (fRx-fTx)
80 MHz
IMD2 (fRx-fTx)
3840 MHz
IMD3 (2fTx-fRx)
1800 MHz
IMD3 (2fTx-fRx)
5720 MHz
IMD2 (fRx-fTx)
45 MHz
IMD2 (fRx-fTx)
1715 MHz
IMD3 (2fTx-fRx)
790 MHz
IMD3 (2fTx-fRx)
2550 MHz
IIP3 Condition
Band
f1
+27 dBm on TRx
f2
+27 dBm on TRx
Band I
1950 MHz
1951 MHz
Band V
835 MHz
836 MHz
IIP3 Condition
IIP3 = (3 × Pout – IM3)/2
*25
*26
8
*13
*14
*15
*16
*17
*18
*19
*20
*21
*22
*23
*24
CXM3583AUR
Preliminary
Triple Beat Ratio
VDD = 2.5 V,
Item
Triple
Beat
Ratio
Symbol
Path
TBR
Ant-TRx
1, 2, 3, 4, 5, 6, 7
Condition
Vctl = 1.80 V, Ta = 25 °C
Min.
Typ.
Max.
-
-
Tx1 at
*1
TRx
21.5 dBm
[MHz]
Tx2 at
*1
TRx
21.5 dBm
[MHz]
Jammer at
Ant
–30 dBm
[MHz]
Triple
Beat
Product
*1
at TRx
[MHz]
-
835.5
836.5
881.5
881.5  1
81
-
-
1880
1881
1960
1960  1
81
-
-
dBc
(*)Electrical characteristics are measured with all RF ports terminated in 50 .
*12A:Measured with the recommended Circuit1, Circuit2
IIP2
VDD = 2.5 V,
Item
Symbol
Path
-
Input
IP2
IIP2
Ant - TRx
1, 2, 3, 4, 5, 6, 7
Condition
Vctl = 1.80 V,
Min.
Typ.
Max.
Tx at
TRx*1
24 dBm
[MHz]
Jammer
at Ant
-20 dBm
[MHz]
IM2
Product at
*1
TRx
[MHz]
-
-
-
836.61
1718.61
881.61
113.5
-
-
836.61
45
881.61
95.5
-
-
1885
3850
1965
95.5
-
-
1885
80
1965
95.5
-
-
1732.5
3865
2132.5
95.5
-
-
1732.5
400
2132.5
95.5
-
-
(*)Electrical characteristics are measured with all RF ports terminated in 50 .
*12A:Measured with the recommended Circuit1, Circuit2
9
Unit
Ta = 25 °C
Unit
dBm
CXM3583AUR
Preliminary
Recommended Circuit 1
15
14
13
12
GND
Tx2
GND
GND
Tx1
GND
Operation Frequency Range : 0.7 GHz to 2.7 GHz
11
10
GND
GND
16
Rx3
9
17
8
18
7
GND
GND
UQFN-30P PKG
UQFN
-30P
PKGmm
(3.0
mm
× 3.8
(3.0mm
3.8mm
×
0.625 xmm
Max.)
Rx2
19
Rx1
TRx6
6
TRx5
x 0.60mm Max.)
20
5
TRx7
21
4
Top View
TRx1
22
3
23
2
24
1
TRx2
TRx4
TRx3
GND
GND
GND
30
GND
29
CTLA
28
CTLB
27
CTLC
26
CTLD
C2
VDD
25
*1: No DC blocking capacitors are required on all RF ports. (Except sourcing DC bias)
*2: DC levels of all RF ports are GND.
*3: L1 Inductor(22 nH) and C1 Capacitor(12 pF) are recommended on Ant port for ESD protection.
*4: C2 Capacitor(100 pF) is recommended.
10
C1
ANT
L1
CXM3583AUR
Preliminary
Recommended Circuit 2
15
14
13
12
11
GND
Tx2
GND
GND
Tx1
GND
Operation Frequency Range : 0.45 GHz to 2.7 GHz
10
GND
GND
16
Rx3
9
17
8
18
7
GND
GND
Rx2
19
Rx1
20
UQFN-30P PKG
(3.0UQFN
mm -30P
× 3.8PKG
mm
(3.0mm x 3.8mm
× 0.625 mm Max.)
TRx5
x 0.60mm Max.)
5
TRx1
L2
L2
TRx4
L2
22
3
TRx2
TRx3
GND
23
2
24
1
GND
L2
GND
28
29
30
GND
27
CTLA
26
CTLB
C2
VDD
25
CTLC
L2
4
Top View
CTLD
L2
21
L1
TRx6
6
TRx7
L2
C1
ANT
*1: No DC blocking capacitors are required on all RF ports. (Except sourcing DC bias)
*2: DC levels of all RF ports are GND.
*3: L1 Inductor(47 nH) and C1 Capacitor(22 pF) are recommended on Ant port for ESD protection.
*4: L2 Inductor(12 nH) is recommended on a TRx port assigned for Band I to improve IMD2 performance(Rx-Tx(190 MHz)).
*5: C2 Capacitor(100 pF) is recommended.
11
CXM3583AUR
Preliminary
Recommended Circuit 3
2nd Harmonic Improvement at LTE : Band13
UQFN-30P PKG
(3.0 mm × 3.8 mm
× 0.625 mm Max.)
*1: No DC blocking capacitors are required on all RF ports. (Except sourcing DC bias)
*2: DC levels of all RF ports are GND.
*3: L1 Inductor(22 nH) and C1 Capactor(12 pF) are recommended on Ant port for ESD protection.
*4: C2 Capacitor(100 pF) is recommended.
*5: L3 Inductor(1.8 nH) and C3 Capacitor(6.6 pF) are recommended when TRx1 is assigned for Band 13.
L4 Inductor(1.8 nH) and C4 Capacitor(7.8 pF) are recommended when TRx3 is assigned for Band 13.
L5 Inductor(1.8 nH) and C5 Capacitor(6.6 pF) are recommended when TRx7 is assigned for Band 13.
12
CXM3583AUR
Preliminary
PCB Layout
Foot Pattern
Recommended PCB Design
13
CXM3583AUR
Preliminary
Package Outline
(Unit: mm)
Product Code:875341512
14
CXM3583AUR
Preliminary
Package Outline
(Unit: mm)
Product Code:875342694
15
CXM3583AUR
Preliminary
Marking
16
CXM3583AUR
Preliminary
Note
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume
responsibility for any problems arising out of the use of these circuits.
17
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