PD - 91666B IRFE130 REPETITIVE AVALANCHE AND dv/dt RATED JANTX2N6796U HEXFET TRANSISTORS JANTXV2N6796U SURFACE MOUNT (LCC-18) [REF:MIL-PRF-19500/557] 100V, N-CHANNEL Product Summary Part Number IRFE130 BVDSS 100V RDS(on) 0.18Ω ID 8.0A The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. LCC-18 Features: ! ! ! ! ! ! ! ! Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight Absolute Maximum Ratings Parameter ID @ VGS = 10V, TC = 25°C ID @ VGS = 10V, TC = 100°C I DM PD @ TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Units Continuous Drain Current Continuous Drain Current Pulsed Drain Current ➀ Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ➁ Avalanche Current ➀ Repetitive Avalanche Energy ➀ Peak Diode Recovery dv/dt ➂ Operating Junction Storage Temperature Range 8.0 5.0 32 25 0.17 ±20 134 8.3 -55 to 150 Pckg. Mounting Surface Temp. Weight 300 (for 5 S) 0.42(typical) A W W/°C V mJ A mJ V/ns o C g For footnotes refer to the last page www.irf.com 1 1/17/01 IRFE130 Electrical Characteristics Parameter Min Drain-to-Source Breakdown Voltage 100 Typ Max Units — — V — 0.11 — V/°C — — 2.0 3.0 — — — — — — — — 0.18 0.207 4.0 — 25 250 VGS(th) gfs IDSS Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS + LD Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance — — — — — — — — — — — — — — — — — — — 6.1 100 -100 29 6.5 17 30 75 40 45 — Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance — — — 660 260 51 — — RDS(on) Test Conditions VGS = 0V, ID = 1.0mA Reference to 25°C, ID = 1.0mA nC VGS = 10V, ID =5.0A➃ VGS =10V, ID =8.0A ➃ VDS = VGS, ID =250µA VDS > 15V, IDS =5.0A➃ VDS=80V, VGS=0V VDS =80V VGS = 0V, TJ = 125°C VGS =20V VGS =-20V VGS =10V, ID= 8.0A VDS =50V ns VDD =50V, ID =8.0A, RG =7.5Ω Ω V S( ) Ω BVDSS ∆BV DSS/∆TJ @ Tj = 25°C (Unless Otherwise Specified) µA nA nH pF Measured from the center of drain pad to center of source pad VGS = 0V, VDS =25V f = 1.0MHz Source-Drain Diode Ratings and Characteristics Parameter Min Typ Max Units IS ISM Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) ➀ — — — — 8.0 32 A VSD t rr QRR Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge — — — — — — 1.5 300 970 V nS µc ton Forward Turn-On Time Test Conditions Tj = 25°C, IS =8.0A, VGS = 0V ➃ Tj = 25°C, IF =8.0A, di/dt ≤100A/µs VDD ≤50V ➃ Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance Parameter RthJC RthJ-PCB Junction to Case Junction to PC Board Min Typ Max Units — — — — 5.0 °C/W 19" " Test Conditions Soldered to a copper clad PC board For footnotes refer to the last page 2 www.irf.com IRFE130 100 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 10 TOP I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP 4.5V 1 20µs PULSE WIDTH TJ = 25°C 0.1 0.1 1 10 100 10 4.5V 1 0.1 0.1 TJ = 150° C 1 V DS = 50V 20µs PULSE WIDTH 4 5 6 7 8 9 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10 RDS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) TJ = 25° C 0.1 10 100 Fig 2. Typical Output Characteristics 100 10 1 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 20µs PULSE WIDTH TJ = 150 °C 2.5 8.0 A ID = 7.4A 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 0 VGS = 10V 20 40 60 80 100 120 140 160 TJ , Junction Temperature ( ° C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRFE130 VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd C, Capacitance (pF) 1000 800 Ciss 600 Coss 400 200 0 Crss 1 10 20 VGS , Gate-to-Source Voltage (V) 1200 8.0AA ID = 7.4 16 12 8 4 0 100 FOR TEST CIRCUIT SEE FIGURE 13 0 6 100 24 30 1000 OPERATION IN THIS AREA LIMITED BY RDS(on) TJ = 25° C ID , Drain Current (A) ISD , Reverse Drain Current (A) 18 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage T J = 150° C 10 1 VGS = 0 V 0.8 1.4 2.0 VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 12 QG , Total Gate Charge (nC) VDS , Drain-to-Source Voltage (V) 0.1 0.2 V DS = 80V V DS = 50V V DS = 20V 2.6 100 10us 100us 10 1ms 10ms 1 0.1 TC = 25 °C TJ = 150 °C Single Pulse 1 10 100 1000 V DS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRFE130 10.0 RD V DS I D , Drain Current (A) 8.0 VGS D.U.T. RG + -V DD 6.0 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 4.0 Fig 10a. Switching Time Test Circuit 2.0 VDS 0.0 90% 25 50 75 100 125 150 TC , Case Temperature ( °C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 100 10 D = 0.50 1 0.20 0.10 P DM 0.05 0.1 0.02 0.01 0.01 0.00001 t1 t2 SINGLE PULSE (THERMAL RESPONSE) 0.0001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. www.irf.com Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 15V L VDS D.U.T RG 10V 20V IAS DRIVER + V - DD 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS A EAS , Single Pulse Avalanche Energy (mJ) IRFE130 400 TOP BOTTOM 300 ID 3.3A 5.0A 8.0A 200 100 0 25 50 75 100 125 150 Starting TJ , Junction Temperature ( °C) tp Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Current Regulator Same Type as D.U.T. Unclamped Inductive Waveforms 50KΩ QG 12V .2µF .3µF 10 V QGS QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform 6 D.U.T. IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRFE130 Foot Notes: ➀ Repetitive Rating; Pulse width limited by maximum junction temperature. ➁ VDD = 50V, starting TJ = 25°C, Peak IL =8.0A, ➂ ISD ≤ 8.0A, di/dt ≤480A/µs, VDD≤ 100V, TJ ≤ 150°C Suggested RG =7.5 Ω ➃ Pulse width ≤ 300 µs; Duty Cycle ≤ 2% Case Outline and Dimensions — LCC-18 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 (0) 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630 IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: 886-(0)2 2377 9936 Data and specifications subject to change without notice. 9/00 www.irf.com 7