INTEGRATED CIRCUITS DATA SHEET TDA1592 PLL stereo decoder and noise blanker Preliminary specification Supersedes data of June 1993 File under Integrated Circuits, IC01 1996 May 31 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 FEATURES GENERAL DESCRIPTION • Adjustment-free voltage controlled PLL oscillator for ceramic resonator (f = 456 kHz) • Pilot signal dependent mono/stereo switching The TDA1592 is a monolithic bipolar integrated circuit providing the stereo decoder function and noise blanking for FM car radio applications. • Analog control of mono/stereo change over [stereo blend, Stereo Noise Controller (SNC)] The device operates in a power supply range of 7.5 to 12 V. • Adjacent channel noise suppression (114 kHz) • Pilot canceller • Analog control of de-emphasis; High Cut Control (HCC) • Reduced and controlled de-emphasis for AM operation (pin 7 to GND) • Applicable as source selector for AM/FM/cassette switching • Soft mute for silent tuning • Separate interference noise detector • Integrated input low-pass filter for delayed noise blanking • Noise blanking at MPX-demodulator outputs. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP supply voltage (pin 5) 7.5 10 12 V IP supply current − 15 20 mA Vo(rms) audio output signal (RMS value) 800 900 1000 mV THD total harmonic distortion − 0.1 0.3 % S/N signal-to-noise ratio − 82 − dB αcs channel separation 30 40 − dB Vtrigg interference voltage trigger level − 10 − mV ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA1592 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 TDA1592T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1996 May 31 2 1996 May 31 3 100 nF 20 Rin 10 nF 1 19 750 kΩ PILOT DETECTOR 2 3 19 Vref LOGIC 19 100 nF POWER SUPPLY 19 PILOT CANCEL mono 38 100 kΩ 4 Iref SWITCH 18 VP 5 47 kΩ 33 pF 27 kΩ 6 Vref interference input MUTE 16 VSNC SNC 17 Vref VCO off 7 68 pF 47 nF 8 820 kΩ 33 kΩ NOISE AND AGC DETECTOR HIGH-PASS AMPLIFIER (120 kHz) AGC 7.4 kΩ 7.4 kΩ INTERFERENCE DETECTOR 2-POLE FILTER (30 kHz) TDA1592 14 6.8 nF 13 6.8 nF mute 47 kΩ Rout R auxiliary input 9 MED724 Rout L 47 kΩ Vref 6.8 kΩ Vref 6.8 kΩ 12 auxiliary input 27 kΩ BC548 PULSE FORMER GATE AND HCC 15 VHCC Lout 10 11 Rout PLL stereo decoder and noise blanker Fig.1 Block diagram with external components, also used as test circuit. CSB 456 F11 VCO PHASE DETECTOR 4-POLE FILTER (80 kHz) Vref 100 nF pilot indicator handbook, full pagewidth 68 kΩ 75 kΩ 164 kΩ 100 nF MPX input Philips Semiconductors Preliminary specification TDA1592 BLOCK DIAGRAM Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 PINNING SYMBOL PLL PIN DESCRIPTION 1 phase locked loop filter 2 oscillator input/output pin for ceramic resonator GND 3 ground (0 V) Iref 4 reference current VP 5 supply voltage (+10 V) INFI 6 interference signal input 7 pulse former time constant; VCO off 8 noise detector time constant; mute on 9 AF feedback input for left audio signal VoL 10 AF output signal left VoR 11 AF output signal right 12 AF feedback input for right audio signal 13 de-emphasis capacitor for left channel CDEER 14 de-emphasis capacitor for right channel HCC 15 HCC input for de-emphasis control SNC 16 stereo blend input Vref 17 externally applied reference voltage of 1 to 5 V 18 identification output (HIGH = pilot existing; stereo) 19 pilot detector level (forced mono input) 20 MPX input signal from IF demodulator OSC PUFO NDET FB-L FB-R CDEEL IDENT PILOT Vi MPX 1996 May 31 handbook, halfpage PLL 1 20 Vi MPX OSC 2 19 PILOT GND 3 18 IDENT Iref 4 17 Vref VP 5 16 SNC TDA1592 INFI 6 15 HCC PUFO 7 14 CDEER NDET 8 13 CDEEL FB-L 9 12 FB-R 11 VoR VoL 10 MED726 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker A smooth mono to stereo take-over, which is controlled by the level detector voltage of the IF part, is achieved by the SNC (pins 16 and 17; see Fig.6). FUNCTIONAL DESCRIPTION The MPX input of the TDA1592 (pin 20) is the null-node of an operational amplifier with internal feedback resistor. Adapting the stereo decoder input to the level of the FM demodulator output is realized by the value of input resistor Rin (see Fig.3). The total gain of the stereo decoder is applicable by varying the feedback resistors Rout (pins 9, 10, 11 and 12) of the output operational amplifiers (see Fig.4). From the output of the MPX demodulator the signals are fed to 2-pole low-pass filters with a cut-off frequency of 30 kHz to provide additional signal delay for noise blanking and attenuation of the subcarrier and its harmonics. These filters are followed by the noise suppression gates, which are combined with de-emphasis and HCC. The de-emphasis is defined by internal resistors (aligned by an external current) and external capacitors (pins 13 and 14). For HCC, the de-emphasis time constant can be changed to higher values (pins 15 and 17; see Figs 7 to 9). This function is controlled by an analog input signal, derived from the level detector voltage of the IF part. When the VCO is turned off (pin 7 to GND), de-emphasis is reduced to 20 µs for full frequency response when AM-AF is fed through the stereo decoder. De-emphasis remains controllable. The input amplifier is followed by an integrated 4th order Bessel low-pass filter with a cut-off frequency of 80 kHz. It provides necessary signal delay for noise blanking and damping of high frequency interferences at the stereo decoder input. The soft mute facility (pin 8) provides silent tuning for RDS processing. The mute time constant may be adjusted from pin 8. In mute position and the VCO switched off (pin 7), the output amplifiers can be used for cassette playback, AM stereo purpose or other signal sources. From the gate circuits audio is fed through internal series resistors to the inverting inputs of the output operational amplifiers (pins 9 and 12), which can also be used as signal inputs for cassette playback or other sources when the mute is activated. The gain of these amplifiers is defined by external feedback resistors Rout (pins 9, 10, 11 and 12). The voltage to current converted MPX signal is fed to phase detector, pilot detector and pilot canceller circuits. The oscillator is alignment-free with an external ceramic resonator at 456 kHz as reference (pin 2). The required 19 kHz and 38 kHz signals are generated by division of the oscillator output signal in a logical circuit. For regeneration of the 38 kHz subcarrier, a PLL is used. The 19 kHz quadrature phase signal is fed to the 19 kHz phase detector, where it is compared with the incoming pilot tone. The DC output signal of the phase detector (pin 1) controls the oscillator (PLL). The input of the ignition noise blanker is the null node of an operational amplifier (pin 6). It can be driven by the level detector output of the FM-IF limiter and/or the MPX signal. Its sensitivity is dependent on the value of the series input resistor at pin 6. The pilot presence detector is driven by internally generated in-phase 19 kHz. Its pilot-dependent DC output voltage (pin 19) is fed to a threshold switch, which activates the pilot indicator logic output (pin 18) and turns the stereo decoder to stereo operation. The same DC voltage is used to control the amplitude of an anti-phase internally generated 19 kHz signal. In the pilot canceller, the pilot tone is compensated by this anti-phase 19 kHz signal. The operational amplifier output signal is fed through an integrated 120 kHz high-pass filter, becomes amplified and is then fed in parallel to the noise detector and the interference detector. The noise detector is a negative peak detector. Its output (pin 8) controls the trigger sensitivity (prevention to false triggering at noisy input signals) and the attenuation of the input operational amplifier. The output of the interference detector, when receiving a steep pulse, triggers a mono flip-flop, which is a part of the pulse former circuit. The time constant of the mono flip-flop is defined by an external capacitor (pin 7) and its output activates the blanking gates in the audio. The pilot cancelled signal is fed to the multiplex decoder. There, the side signal is demodulated and combined with the main signal in a matrix to left and right audio channel. Compensation for roll-off in the incoming MPX signal caused by IF filters and FM demodulator is realized by corresponding side signal amplification. 1996 May 31 TDA1592 5 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VP supply voltage (pin 5) 0 13.2 V Ptot total power dissipation 0 0.25 W Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C Ves electrostatic handling for all pins; note 1 −400 +400 V Note 1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor. CHARACTERISTICS VP = 10 V; Tamb = 25 °C; input signal Vi MPX(p-p) = 1.7 V; m = 100% (∆f = ±75 kHz, fmod = 1 kHz); de-emphasis of 50 µs and series resistor at input R1 = 164 kΩ; measurements taken in Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage (pin 5) 7.5 10 12 V IP supply current − 15 20 mA Stereo decoder Vi MPX(p-p) MPX input signal − 1.7 − V ∆Vi MPX(p-p) overdrive margin of MPX input signal THD = 1% 6 − − dB Vo(rms) AF mono output signal at pins 10 and 11 (RMS value) without pilot 800 900 1000 mV ∆Vo overdrive margin of output signal THD = 1% 6 − − dB V10-11/Vo difference of output voltage levels − − 1 dB Vo 10,11 DC output voltage (pins 10 and 11) 3.2 3.7 4.2 V Ro 10,11 output resistance − 150 − Ω Io output current 330 400 − µA R2,3 maximum feedback resistor − − 68 kΩ 3.7 3.8 3.9 V 30 40 − dB − 0.1 0.3 % V4,3 reference voltage αcs channel separation THD total harmonic distortion pin 16 open-circuit; see Fig.6 S/N signal-to-noise ratio f = 20 to 16000 Hz 77 82 − dB α19 pilot signal suppression f = 19 kHz 40 50 − dB α38 subcarrier suppression f = 38 kHz 35 50 − dB f = 57 kHz 46 − − dB f = 76 kHz − 60 − dB fmod = 10 kHz; note 1 − 60 − dB fmod = 13 kHz − 58 − dB α57 α76 IM2 intermodulation for fspur = 1 kHz IM3 α57 VF traffic radio (VWF) f = 57 kHz; note 2 − 70 − dB α67 SCA (Subsidiary Communications Authorization) f = 67 kHz; note 3 70 − − dB 1996 May 31 6 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker SYMBOL MIN. TYP. MAX. UNIT f = 114 kHz; note 4 − 80 − dB f = 190 kHz; note 4 − 70 − dB f = 100 Hz; Vripple (rms) = 100 mV − 35 − dB oscillator frequency (ceramic resonator) − 456 − kHz frequency range of free running oscillator 451 − 459 kHz ∆f/f capture and holding range − ±0.65 − % V7 VCO-off voltage (pin 7) 0 − 0.6 V stereo on − 24 30 mV stereo off α114 PARAMETER TDA1592 CONDITIONS ACI (Adjacent Channel Interference) α190 PSRR power supply ripple rejection VCO (pin 2) fosc Mono/stereo control (pins 16, 17 and 19) Vi pilot pilot threshold voltage for automatic switching by pilot input voltage (RMS value) 8 20 − mV HYS hysteresis of pilot threshold voltage − 2 − dB V19 switching voltage for external mono control (pin 19) − − 0.7 V Vref reference input voltage range (pin 17) V16-17 control voltage for channel separation due to pin 17 (Vref) 1 − 5 V αcs = 6 dB; see Fig.5 −80 −100 −120 mV αcs = 20 dB; see Fig.5 −40 −55 −70 mV Pilot indicator logic level output (pin 18) V18 LOW voltage I18 = 500 µA − 250 400 mV I18 HIGH current V18 = 10 V − − 1 µA V8 < 1.6 V 80 − − dB V8 > 4 V − − 0.2 dB after muting − − ±50 mV 50 − 150 µs Muting (pin 8) MUTEatt Vo(offset) mute attenuation (pin 8) DC offset voltage (pins 10 and 11) HCC (pin 15) CRdeem control range of de-emphasis see Figs 7 and 8 Cdeem = 6.8 nF for European standard for USA standard V15-17 1996 May 31 control voltage (pin 15 due to pin 17) in both standards 7 Cdeem = 10 nF 75 − 225 µs lower value CRdeem − 0 − mV upper value CRdeem − −300 − mV Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker SYMBOL TDA1592 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT HCC (pin 15, pin 7 to GND) CRdeem V15-17 ∆V10, ∆V11 control range of de-emphasis see Fig.9 for European standard Cdeem = 6.8 nF 15 − 90 µs for USA standard Cdeem = 10 nF 22 − 135 µs lower value CRdeem − 0 − mV upper value CRdeem − −300 − mV − − ±200 mV − 10 − mV 150 200 250 mV 550 650 750 mV − 40 − µs − 20 − nA control voltage (pin 15 due to pin 17) in both standards DC offset voltage at AF outputs (AM on/off) Noise interference detector τpulse = 10 µs Vpulse trigger sensitivity ∆V8 trigger threshold voltage offset as a function of fint = 120 kHz Vtrigg Vinterf.in = 10 mV Vinterf.in = 100 mV tsup AF suppression time; pulse width I13,14 input offset current (pins 13 and 14) during AF suppression time Notes 1. Intermodulation suppression [Beat Frequency Components (BFC)]: V o(signal) ( at 1 kHz ) IM2 = ------------------------------------------------------- ; f = ( 2 × 10 kHz ) – 19 kHz V o(spurious) ( at 1 kHz ) s V o(signal) ( at 1 kHz ) IM3 = ------------------------------------------------------- ; f = ( 3 × 13 kHz ) – 38 kHz V o(spurious) ( at 1 kHz ) s measured with 91% mono signal; fmod = 10 kHz or 13 kHz; 9% pilot signal. 2. ARI suppression: V o(signal) ( at 1 kHz ) α 57 ARI = ---------------------------------------------------------------------------V o(spurious) ( at 1 kHz ± 23 Hz ) measured with 91% stereo signal; fmod = 1 kHz; 9% pilot signal; 5% ARI subcarrier (fs = 57 kHz; fmod = 23 Hz; AM m = 0.6). 3. Subsidiary Communication Authorization (SCA): V o(signal) ( at 1 kHz ) α 67 = ------------------------------------------------------- ; f = ( 2 × 38 kHz ) – 67 kHz V o(spurious) ( at 9 kHz ) s measured with 81% mono signal; fmod = 1 kHz; 9% pilot signal; 10% SCA subcarrier (fs = 67 kHz, unmodulated). 4. Adjacent Channel Interference (ACI): V o(signal) ( at 1 kHz ) α 114 = ------------------------------------------------------- ; f = 110 kHz – ( 3 × 38 kHz ) V o(spurious) ( at 4 kHz ) s V o(signal) ( at 1 kHz ) α 190 = ------------------------------------------------------- ; f = 186 kHz – ( 5 × 38 kHz ) V o(spurious) ( at 4 kHz ) s measured with 90% mono signal; fmod = 1 kHz; 9% pilot signal; 1% spurious signal (fs = 110 kHz or 186 kHz, unmodulated). 1996 May 31 8 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 MED727 4 handbook, halfpage Vi MPX(p-p) (V) 3 2 1 0 0 100 200 Rin (kΩ) 300 Fig.3 Input signal as a function of series input resistor Rin. MED728 handbook, halfpage +4 G (dB) +2 0 −2 −4 0 20 40 Rout (kΩ) 60 Fig.4 Overall signal gain as a function of feedback resistors Rout (Rin = 164 kΩ). 1996 May 31 9 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 MED729 50 handbook, full pagewidth αcs (dB) (1) 40 (2) 30 20 10 0 10 10 2 10 3 10 4 10 5 AFout (Hz) (1) Coupling capacitor CK at pin 20 = 10 µF. (2) Coupling capacitor CK at pin 20 = 0.1 µF. Fig.5 Channel separation as a function of audio frequency. MED730 50 αcs handbook, halfpage ∆Vo (dB) (dB) 40 −2 30 −4 20 −6 10 −8 0 −200 −10 −300 −100 0 control voltage V16-17 (mV) Fig.6 Stereo blend characteristic (SNC). 1996 May 31 MED731 0 handbook, halfpage −200 −100 0 control voltage V15-17 (mV) Fig.7 HCC with fmod = 10 kHz. 10 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 MED732 handbook, full pagewidth 2 Vo (dB) (1) 0 −2 −4 (2) −6 −8 −10 −12 10 10 2 10 3 10 4 10 5 AFout (Hz) (1) V15-17 = 0. (2) V15-17 = −300 mV. Fig.8 HCC with pre-emphasis as a function of audio frequency. MED733 2 handbook, full pagewidth Vo 0 (dB) −2 (1) −4 −6 −8 (2) −10 −12 −14 −16 −18 10 10 2 10 3 10 4 AFout (Hz) (1) V15-17 = 0. (2) V15-17 = −300 mV. Fig.9 HCC as a function of audio frequency (pin 7 connected to GND; without pre-emphasis). 1996 May 31 11 10 5 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 INTERNAL PIN CONFIGURATION handbook, full pagewidth 4.3 V (4.6 V) PLL 1 3.6 V OSC 2 20 3.8 V Vi MPX 19 4.5 V (0.4 V) PILOT 18 IDENT 3 GND TDA1592 3.8 V Iref VP 2.1 V ( 3 × VBE) 17 1 to 5 V Vref 16 1 to 5 V SNC 6 15 1 to 5 V HCC 7 14 3.8 V CDEER 13 3.8 V CDEEL 12 3.8 V FB-R 11 3.6 V VoR 4 5 INFI 2.1 V ( 3 × VBE) PUFO 14 µA VP − 2.2 V NDET 8 400 µA 3.8 V FB-L 9 3.6 V VoL 10 400 µA 400 µA MED725 Fig.10 Internal circuitry. 1996 May 31 12 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 TEST INFORMATION handbook, full pagewidth interference IN MPX IN 82 kΩ 68 kΩ 82 kΩ 100 nF 100 nF CSB456F11 mono 100 nF 100 µF 12 kΩ 10 kΩ 10 nF 100 nF 100 kΩ 820 kΩ TDA1592 10 Ω 27 kΩ 33 pF 68 pF 27 kΩ Vref 27 kΩ 100 kΩ SNC 100 kΩ 101 mm HCC 27 kΩ VCO off 6.8 nF 33 kΩ 6.8 nF Pilot indicator 47 kΩ mute 820 kΩ GND 47 kΩ 47 kΩ 47 nF 47 kΩ 220 nF 220 nF 220 nF +VP BC548 220 nF AUX IN right right OUT left OUT AUX IN left 76 mm Fig.11 TDA1592 test board (component side). 1996 May 31 13 MED734 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D (1) e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 1996 May 31 REFERENCES IEC JEDEC EIAJ SC603 14 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.42 0.39 0.055 0.043 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1996 May 31 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-24 15 o 8 0o Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1996 May 31 TDA1592 16 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker TDA1592 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 May 31 17 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker NOTES 1996 May 31 18 TDA1592 Philips Semiconductors Preliminary specification PLL stereo decoder and noise blanker NOTES 1996 May 31 19 TDA1592 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 805 4455, Fax. +61 2 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE May 31, 1996 © Philips Electronics N.V. 1996 SCA49 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 517021/1200/02/pp20 Date of release: 1996 May 31 Document order number: 9397 750 00875