PHILIPS PIP202-12M-2

PIP202-12M-2
DC-to-DC converter powertrain
Rev. 02 — 24 November 2003
Product data
M3D797
1. Description
The PIP202-12M is designed for use as the power output stage of a synchronous
buck DC-to-DC converter. It contains a MOSFET control IC, two power MOSFET
transistors and a Schottky diode. By combining the power MOSFETs and the driver
circuit into a single component, stray inductances are virtually eliminated, resulting in
higher switching frequency, lower switching losses and a compact, efficient design.
2. Features
■
■
■
■
■
■
■
Input voltage conversion range from 3.3 V to 12 V
Output voltages from 0.8 V to 5 V
Capable of up to 25 A continuous output current
Operating frequency up to 1 MHz
Peak system efficiency >92% at 500 kHz
Low-profile, surface mount package (10 × 10 × 0.85 mm)
Compatible with any single or multi-phase PWM controller.
3. Applications
■ High-current DC-to-DC point-of-load converters
■ Small form-factor Voltage Regulator Modules
■ Microprocessor and memory voltage regulators.
4. Ordering information
Table 1:
Ordering information
Type number
PIP202-12M-2
Package
Name
Description
Version
HVQFN68
(MLF68)
plastic, thermal enhanced very thin quad flat package; no leads; SOT687-1
68 terminals; body 10 × 10 × 0.85 mm
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
5. Block diagram
VDDC
13, 14
PIP202-12M
control cct
supply
VDDO
CB
1 to 8, 60, 61
68, PAD1
11, 12
bootstrap
capacitor
driveH
VI
VSSC
n.c.
PWM
input
16, 17
10, 26, 27,
45 to 59
62 to 67, PAD3
sourceH
9, 15
22 to 24, PAD2 control
cct gnd
18 to 21, 25
VO
driveL
28 to 44
sourceL
VSSO
03ag51
A bootstrap diode is integrated into the design of the PIP202-12M between VDDC and CB.
Fig 1. Block diagram.
6. Pinning information
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
VDDO
VO
VO
VO
VO
VO
VO
VDDO
VDDO
VO
VO
VO
VO
VO
VO
VO
VO
6.1 Pinning
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VDDO
PAD 1
VO
PAD 3
VSSC
PAD 2
PIP202-12M
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VO
VO
VO
VO
VO
VO
VO
VSSO
VSSO
V SSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSC
VSSC
VSSC
n.c.
VO
VO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
VSSO
n.c.
n.c.
n.c.
n.c.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
VSSC
VO
CB
CB
VDDC
VDDC
VSSC
VI
VI
03ag52
Shaded area denotes terminal 1 index area.
Fig 2. Pin configuration (footprint view).
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
2 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
6.2 Pin description
Table 2:
Pin description
Symbol
Pin
VDDO
1 to 8, 60, 61,
68
[1] [4]
9, 15, 22 to 24
VO
10, 26, 27,
45 to 59,
62 to 67
CB
VDDC
VSSC
I/O
Description
-
output stage supply voltage
[2] [4]
-
control circuit supply ground
[3] [4]
O
output
11, 12
I/O
bootstrap capacitor connection
13, 14
-
control circuit supply voltage
VI
16, 17
I
pulse width modulated input
VSSO
28 to 44
-
output stage supply ground
n.c.
18 to 21, 25
-
no internal connection
[1]
[2]
[3]
[4]
[5]
[5]
All pins connected to PAD1
All pins connected to PAD2
All pins connected to PAD3
PAD1, PAD2 and PAD3 are electrical connections and must be soldered to the printed circuit board
All n.c. pins should be connected to VSSC.
7. Functional description
7.1 Basic functionality
output stage supply voltage
control circuit supply (12 V)
VDDC CB
input voltage
VI
from PWM controller
VI
VSSC
tp
T
δ=
tp
T
100
nF
VDDO
Lout
VO
output
Cout
VSSO
signal ground power ground
03ad36
Fig 3. Simplified functional block diagram of a synchronous DC-to-DC converter
output stage.
In order to understand the functions performed by the PIP202-12M, consider the
requirements of a synchronous DC-to-DC converter output stage, driven from a PWM
controller (Figure 3).
When the input voltage is HIGH, the upper MOSFET must be on and the lower
MOSFET must be off. Current flows from the supply (VDDO), through the upper
MOSFET and the inductor (Lout), to the output.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
3 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
When the input voltage is LOW and current is flowing in the inductor, the upper
MOSFET must be off and the lower MOSFET must be on. Current flows from the
power ground (VSSO), through the lower MOSFET and the inductor (Lout), to the
output.
Finally, when switching between states, both MOSFETs must not be on at the same
time.
7.2 MOSFET driver function
input voltage
upper MOSFET
gate drive
delay
lower MOSFET
gate drive
delay
output voltage
03ag35
Fig 4. Input, output and gate drive waveforms of a synchronous DC-to-DC converter
output stage.
The input, output and gate drive waveforms are shown in Figure 4. When the input
voltage goes HIGH, the gate drive to the lower MOSFET immediately goes LOW. This
causes the output current to flow through the Schottky diode, connected between the
drain and source of the lower MOSFET. This causes output voltage to fall from zero to
approximately −0.5 V.
After a delay, if the input voltage is still HIGH, the gate drive to the upper MOSFET
goes HIGH. This causes the output voltage to rise to the output stage supply voltage,
VDDO.
When the input voltage goes LOW, the gate drive to the upper MOSFET immediately
goes LOW. The output voltage falls from VDDO, until it is clamped by the Schottky
diode at approximately −0.5 V.
After a delay, if the input voltage is still LOW, the gate drive to the lower MOSFET
goes HIGH. The lower MOSFET turns on, and the output voltage rises from −0.5 V to
zero.
7.3 Bootstrap diode
A bootstrap diode is integrated into the design of the PIP202-12M between VDDC and
CB.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
4 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
7.4 3-state function
If the input from the PWM controller becomes high impedance (3-state) for longer
than td(3-state), then both MOSFETs are turned off and the VI input is driven to 2.5 V
by an internal 2 x 10 kΩ resistor voltage divider between an internal 5 V reference
and ground. Once the VI input is outside the 3-state window for longer than td(3-state)
normal operation will commence.
8. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDDC
Conditions
Min
Max
Unit
control circuit supply voltage
−0.5
15
V
VDDO
output stage supply voltage
−0.5
25
V
VI
input voltage
−0.5
5.25
V
VO
output voltage
−0.5
VDDO + 0.5 V
VCB
bootstrap voltage
−0.5
VO + 15
V
IO(AV)
average output current
VDDC = 12 V; Tpcb ≤ 110 °C;
Figure 5
-
25
A
IORM
repetitive peak output current
VDDC = 12 V; tp ≤ 10 µs
[1]
-
200
A
Ptot
total power dissipation
Tpcb = 25 °C
[2]
-
25
W
Tpcb = 90 °C
[2]
-
12
W
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−55
+150
°C
[1]
[2]
Pulse width and repetition rate limited by maximum value of Tj.
Assumes a thermal resistance from junction to printed-circuit board of 5 K/W.
03ag41
30
IO(AV)
(A)
20
10
0
0
50
100
150
Tpcb (°C)
VDDC = 12 V; VDDO = 12 V; fi = 500 kHz; VO = 1.6 V.
Fig 5. Average output current as a function of printed-circuit board temperature.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
5 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
9. Thermal characteristics
Table 4:
Thermal characteristics
Symbol
Parameter
Rth(j-pcb)
thermal resistance from
junction to printed-circuit
board
Rth(j-a)
thermal resistance from
junction to ambient
Rth(j-c)
thermal resistance from
junction to case
Conditions
Min
Typ
Max
Unit
-
4
5
K/W
no thermal vias
-
25
-
K/W
with thermal vias
-
20
-
K/W
with thermal vias and forced
air cooling; airflow = 0.8 ms-1
(150 LFM)
-
15
-
K/W
-
11
-
K/W
Min
Typ
Max
Unit
device mounted on FR4
printed-circuit board; copper
area around device 25 × 25 mm
measured on upper surface of
package.
10. Characteristics
Table 5: Characteristics
VDDC = 12 V; Tj = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Static characteristics
control circuit supply voltage
25 °C ≤ Tj ≤ 150 °C
HIGH-level input voltage
VIL
7
12
14
V
25 °C ≤ Tj ≤ 150 °C
[1]
3.0
3.45
3.9
V
LOW-level input voltage
25 °C ≤ Tj ≤ 150 °C
[1]
1
1.45
1.9
V
ILI
input leakage current
0 V ≤ VI ≤ 5 V
-
0.3
1.2
mA
IDDC
control circuit supply current
fi = 0 Hz
-
1.5
3
mA
fi = 500 kHz; Figure 10
-
45
60
mA
VDDO = 12 V; IO(AV) = 20 A;
fi = 500 kHz; VO = 1.6 V;
Tpcb ≤ 120 °C; Figure 6
-
4.5
-
W
td(on)(IH-OH) turn-on delay time input HIGH VDDO = 12 V; IO(AV) = 25 A
to output HIGH
-
77
85
ns
td(off)(IL-OL) turn-off delay time input LOW
to output LOW
-
30
45
ns
to(r)
output rise time
-
18
25
ns
to(f)
output fall time
-
12
20
ns
td(3-state)
3-state delay time
-
140
-
ns
VDDC
VIH
total power dissipation
Ptot
Dynamic characteristics
[1]
If the input voltage remains between VIH and VIL (2.5 V typ) for longer than td(3-state), then both MOSFETs are turned off.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
6 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
03ag54
1.6
03ag53
8
a
Ptot
(W)
1.4
6
1.2
4
1
2
0.8
0
0
5
10
15
20
IO (A)
5
25
VDDC = 12 V; VDDO = 12 V; VO = 1.6 V; fi = 500 kHz
10
15
VDDO (V)
20
VDDC = 12 V; VO = 1.6 V; fi = 500 kHz; IO(AV) = 12.5 A
P tot
a = --------------------------------------P tot ( V
= 12V )
DDO
Fig 6. Total power dissipation as a function of average
output current; typical values.
03ag74
03ag55
1.3
Fig 7. Normalized power dissipation as a function of
output stage supply voltage; typical values.
1.6
c
b
1.4
1.2
1.2
1.1
1
1
0.8
0.9
0.6
1
2
3
4
5
VO (V)
VDDC = 12 V; VDDO = 12 V; fi = 500 kHz; IO(AV) = 12.5 A
P tot
b = ---------------------------------P tot ( V = 1.6V )
200
600
800
1000
fi (kHz)
VDDC = 12 V; VDDO = 12 V; VO = 1.6 V; IO(AV) = 12.5 A
P tot
c = -------------------------------------P tot ( f = 500kHz )
O
i
Fig 8. Normalized power dissipation as a function of
output voltage; typical values.
Fig 9. Normalized power dissipation as a function of
input frequency; typical values.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
400
Rev. 02 — 24 November 2003
7 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
03ae75
100
IDDC
(mA)
80
60
40
20
0
250
500
750
fi (kHz)
1000
VDDC = 12 V; VDDO = 12 V; VO = 1.6 V; IO(AV) = 12.5 A.
Fig 10. Control circuit supply current as a function of input frequency; typical values.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
8 of 20
PIP202-12M-2
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DC-to-DC converter powertrain
11. Application information
11.1 Typical application
10 Ω
control circuit
supply (12 V)
conversion
supply (12 V)
1 µF
100
nF
22 µF (4x)
VDDC CB VDDO
360 nH
VI
VO
PIP202-12M
VSSC
VSSO
100 µF (2x)
2.2 nF
2.2 Ω
10 Ω
22 µF (4x)
1 µF
100
nF
VDDC CB VDDO
360 nH
VI
VO
PIP202-12M
VSSC
PWM 1
PWM 2
PWM
Controller
2.2 nF
100 µF (2x)
2.2 Ω
10 Ω
PWM 3
PWM 4
VSSO
1 µF
100
nF
22 µF (4x)
VDDC CB VDDO
360 nH
VI
VO
PIP202-12M
VSSC
VSSO
2.2 nF
100 µF (2x)
2.2 Ω
10 Ω
1 µF
22 µF (4x)
100
nF
VDDC CB VDDO
output
voltage
360 nH
VI
signal ground
power ground
VO
PIP202-12M
VSSC
VSSO
2.2 nF
100 µF (2x)
2.2 Ω
03ag56
Fig 11. Typical application circuit using the PIP202-12M in a four-phase converter.
A typical four-phase buck converter is shown in Figure 11. This system uses four
PIP202-12M devices to deliver a continuous output current of 80 A at an operating
frequency of 500 kHz.
Remark: An external bootstrap diode is not required as one is already integrated into
the design of the PIP202-12M between VDDC and CB.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
9 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
At 500 KHz and 20 A output current, the maximum dissipation in each PIP202-12M is
typically 4.5 W. The typical thermal resistance from junction to ambient is given in
Table 4. With thermal vias and forced air cooling, the thermal resistance of each
PIP202-12M from junction to ambient is 15 K/W. Assuming an ambient temperature
of 55 °C, the junction temperature (Tj) is given by:
T j = P tot × R th ( j – a ) + T amb = 4.5 × 15 + 55 = 122.5°C
(1)
The thermal resistance between the junction and the printed-circuit board is 5 K/W.
Therefore, the printed-circuit board temperature (Tpcb) is given by:
T pcb ( max ) = T j ( max ) – P tot × R th ( j – pcb ) = 122.5 – 4.5 × 5 = 100°C
(2)
11.2 Advantages of an integrated driver
One problem in the design of low-voltage, high-current DC-to-DC converters using
discrete components, is stray inductance between the various circuit elements.
Stray inductance in the gate drive circuit increases the switching times of the
MOSFETs and causes high-frequency oscillation of the gate voltage.
Stray inductance in the high-current loop between VDDO and VSSO causes switching
losses and electromagnetic interference. In discrete designs, high-frequency electric
and magnetic fields radiate from PCB tracks and couple into adjacent circuits.
By integrating the power MOSFETs and their drive circuits into a single package,
stray inductance is virtually eliminated, resulting in a compact, efficient design.
In discrete designs, the delays in the MOSFET drivers must be long enough to
ensure no cross-conduction even when using the slowest MOSFETs. Use of an
integrated driver allows the propagation delays in the MOSFET drivers to be precisely
matched to the MOSFETs. This minimizes switching losses and eliminates
cross-conduction whilst allowing the circuit to operate at a higher frequency.
11.3 External connection of power and signal lines
A major benefit of the PIP202-12M module is the ability to switch the internal power
MOSFETs faster than a DC-to-DC converter built from discrete components. This not
only reduces switching losses and increases system efficiency but also results in
higher transient voltages on the device supply lines (VDDO and VSSO). This is due to
the high rate of change of current (dI/dt) through the combined parasitic inductance of
the PCB tracks and the decoupling capacitors.
To minimize the amplitude of these transients, decoupling capacitors must be placed
between VDDO and VSSO, as close as possible to the device pins. Low inductance,
chip ceramic capacitors are recommended.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
10 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
output stage supply voltage
10 Ω
control circuit
supply (12 V)
1 µF
input voltage
from PWM controller
100
nF
VDDC CB
VDDO
Lout
VO
VI
VSSC VSSO
output
Cin
Cout
signal ground
power ground
03ae27
Fig 12. External connection of power and signal lines.
To protect the control circuit from the transient voltages, the following precautions
must be taken. Refer to Figure 12.
1. The output stage ground (VSSO) must be connected to the decoupling capacitor
(Cin) before joining the ground plane. Otherwise, the switching noise on VSSO will
couple into the control circuit ground (VSSC).
2. The control circuit supply must be filtered using a resistor-capacitor (RC) filter.
The values shown in Figure 12 are suitable for most applications.
3. It is essential that the VSSC (signal ground) connection at the device is not
connected in the current return path between the VSSO (power ground)
connection at the device and the VDDO input capacitor.
4. It is also essential that the input to the VDDC (logic power) filter is not connected in
the current path between the VDDO (conversion power) connection at the device.
11.4 Switching frequency
A high operating frequency reduces the size and number of capacitors needed to
filter the output current, and also reduces the size of the output inductors. The
disadvantage, however is higher dissipation due to switching and MOSFET driver
losses. For example, doubling the operating frequency of the circuit in Figure 11 from
500 kHz to 1 MHz would increase the power dissipation in each PIP202-12M from
4 W to 6 W, at an output current of 20 A in each PIP202-12M.
The maximum switching frequency is limited by thermal considerations, the
dissipation in the PIP202-12M device(s) and the thermal resistance from junction to
ambient.
11.5 Thermal design
The PIP202-12M has three pads on its underside. These are designated PAD1, PAD2
and PAD3 (Figure 2). PAD1 is connected to VDDO, PAD2 is connected to VSSC and
PAD3 is connected to VO. In addition to providing low inductance electrical
connections, these pads conduct heat away efficiently from the MOSFETs and
control IC to the printed-circuit board. The thermal resistance from junction to
printed-circuit board is approximately 5 K/W. In order to take full advantage of the low
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
11 of 20
PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
thermal resistance of this package, the printed-circuit board must be designed so that
heat is conducted away efficiently from the package. This can be achieved by
maximizing the area of copper around each pad, and by incorporating thermal vias to
conduct the heat to inner and/or bottom layers of the printed-circuit board.
An example of a thermal via pattern is shown in Figure 13. In a typical application,
with no forced air cooling, the use of thermal vias typically reduces the thermal
resistance from 25 K/W to 20 K/W. The additional use of a small fan can reduce this
further to approximately 15 K/W.
PAD1
PAD3
PAD2
03ag36
All holes 0.5 mm diameter with 1 mm spacing.
Fig 13. Printed-circuit board thermal via pattern.
The thermal resistance of a particular design can be measured by passing a known
current between VSSO and VDDO. The current flows through the Schottky diode and
through the source-drain diode of the upper MOSFET. The direction of current flow is
into VSSO and out of VDDO. The volt drop between VSSO and VDDO is then measured
and used to calculate the power dissipation in the PIP202-12M. The case
temperature of the PIP202-12M can be measured using an infra-red thermometer.
The thermal resistance can then be calculated using the following equation:
T case – T amb
R th ( j – pcb ) = ------------------------------- ( K ⁄ W )
I × VF
(3)
where Tcase is the measured case temperature (°C), Tamb is the ambient
temperature (°C), I is the MOSFET current (A), and VF is the voltage drop between
VSSO and VDDO (V).
Where more than one phase is used, for example the circuit of Figure 11, the thermal
resistance of each PIP202-12M should be measured with current flowing in all
phases.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
12 of 20
PIP202-12M-2
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12. Test information
Figure 14 shows the test circuit used to measure power loss in the PIP202-12M. The
output voltage is measured using an averaging circuit. This eliminates losses in the
output inductor and the PCB tracks. The calculated power loss, using this method,
includes the losses in the Equivalent Series Resistance (ESR) of the input filter
capacitors. This must be subtracted from the total loss to give the net loss in the
PIP202-12M.
IDDO
output stage supply
control circuit
supply (12 V)
A
IDDC
V VDDO
A
100
nF
VDDC CB
VDDO
IO
500 nH
VO
VI
input voltage
from pulse generator
A
VSSC VSSO
load
VI
signal ground
power ground
averaging
circuit
VO(AV)
V
03ai73
P DDO = V DDO × I DDO
P DDC = V DDC × I DDC
P O = V O ( AV ) × I O
P tot = P DDO + P DDC – P O
Fig 14. Power loss (Ptot) test circuit.
13. Marking
terminal 1
index area
TYPE No.
Design centre
k = Hazel Grove, UK
Release status code
X = Development Sample
Y = Customer Qualification Sample
blank = Released for Supply
DIFFUSION LOT No.
Diffusion centre
h = Hazel Grove, UK
MANUFACTURING CODE
hfkYYWWY
COUNTRY OF ORIGIN
Assembly centre
f = Anam Korea
Date code
YY = last two digits of year
WW = week number
03ag38
03ai72
TYPE No: PIP202-12M-N (N is version number)
DIFFUSION LOT No: 7 characters
MANUFACTURING CODE: see Figure 16
COUNTRY OF ORIGIN: Korea
Fig 15. SOT687-1 marking.
Fig 16. Interpretation of manufacturing code.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
13 of 20
PIP202-12M-2
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14. Package outline
HVQFN68: plastic thermal enhanced very thin quad flat package; no leads;
68 terminals; body 10 x 10 x 0.85 mm
SOT687-1
B
D
A
D1
terminal 1
index area
A
E1 E
A4
A1
c
detail X
C
e1
e
18
y
y1 C
v M C A B
w M C
b
34
L
35
17
Eh1
e
Eh
e2
Eh1
1
terminal 1
index area
51
68
52
Dh
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A4
b
c
mm
1
0.05
0.00
0.80
0.65
0.30
0.18
0.2
D
D1
Dh
10.15 9.95
9.85 9.55
3.8
3.5
E
E1
10.15 9.95
9.85 9.55
Eh
Eh1
e
e1
e2
L
v
w
y
y1
7.85
7.55
3.8
3.5
0.5
8
8
0.75
0.50
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT687-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-18
03-06-13
Fig 17. SOT687-1.
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9397 750 11943
Product data
Rev. 02 — 24 November 2003
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15. Soldering
15.1 Introduction to soldering MLF packages
The MicroLeadFrame package (MLF) is a near Chip Scale Package (CSP) with a
copper leadframe. It is a leadless package, where electrical contact to the printed
circuit board is made through metal pads on the underside of the package. In addition
to the small pads around the periphery of the package, there are large pads on the
underside that provide low thermal resistance, low electrical resistance, low
inductance connections between the power components inside the MLF package and
the PCB. It is this feature of the MLF package that makes it ideally suited for VRM
applications.
Electrical connection between the package and the printed circuit board is made by
printing solder paste on the printed circuit board, placing the component and
reflowing the solder in a convection or infra-red oven. The solder reflow process is
shown in Figure 18 and the typical temperature profile is shown in Figure 19. To
ensure good solder joints, the peak temperature Tp should not exceed 220 °C for thin
packages such as MLF, and the time above liquidus temperature should be less than
1.25 minutes. The maximum temperature can be increased for lead free solder. The
ramp rate during preheat should not exceed 3 K/s. Nitrogen purge is recommended
during reflow.
SOLDER PASTE
PRINTING
03aj26
300
POST PRINT
INSPECTION
Temp
(°C)
COMPONENT
PLACEMENT
Tp
200
Tr
PRE REFLOW
INSPECTION
1 min max
REFLOW SOLDERING
100
rate of rise of
temperature < 3 K/s
POST REFLOW INSPECTION
(PREFERABLY X-RAY)
REWORK AND
TOUCH UP
0
0
03aj25
Fig 18. Typical reflow soldering process flow.
1
2
time (minutes)
3
Fig 19. Typical reflow soldering temperature profile.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
1.25 min max
Te
Rev. 02 — 24 November 2003
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PIP202-12M-2
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DC-to-DC converter powertrain
15.2 Rework guidelines
Since the solder joints are largely inaccessible, only the side fillets can be touched
up. If there are defects underneath the package, then the whole package has to be
removed.
The first step in component removal is to reflow the solder joints. It is recommended
that the board is heated from the underside using a convective heater whilst hot air or
gas is directed at the upper surface of the component. Nozzles should be used to
direct the hot air or gas to minimize heating of adjacent components. Excessive
airflow should be avoided since this may cause the package to skew. An airflow of 15
to 20 liters per minute is usually adequate.
Once the solder joints have reflowed, the component should be lifted off the board
using a vacuum pen.
The next step is to clean the solder pads using solder braid and a blade shaped
soldering tool. Finally, the pads should be cleaned with a solvent. The solvent is
usually specific to the type of solder paste used in the original assembly and the
paste manufacturers recommendations should be followed.
16. Mounting
16.1 PCB design guidelines
The terminals on the underside of the package are rectangular in shape with a
rounded edge on the inside. Electrical connection between the package and the
printed-circuit board is made by printing solder paste onto the PCB footprint followed
by component placement and reflow soldering. The PCB footprint shown in Figure 20
is designed to form reliable solder joints.
The use of solder resist between each solder land is recommended. PCB tracks
should not be routed through the corner areas shown in Figure 20. This is because
there is a small, exposed remnant of the leadframe in each corner of the package, left
over from the cropping process.
Good surface flatness of the PCB lands is desirable to ensure accuracy of placement
after soldering. Printed-circuit boards that are finished with a roller tin process tend to
leave small lumps of tin in the corners of each land. Levelling with a hot air knife
improves flatness. Alternatively, an electro-less silver or silver immersion process
produces completely flat PCB lands.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
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PIP202-12M-2
Philips Semiconductors
DC-to-DC converter powertrain
1 SP
(8×)
0.4 SP
0.6 Cu
0.4 SP
0.28 Cu (68×)
1 SP
(8×)
11.15 OA 7.6 Cu 4.1
(2×)
(2×)
8.9 Cu 10.8 Cu
(2×)
(2×)
0.6 Cu
0.5 SP
(4×)
0.4 SP (2×)
0.9 SP
(10×)
e = 0.5
4.1
1 SP
(10×)
8.63 OA
(4×)
solder lands
MGW820
0.1
Cu pattern
0.2
clearance
0.025
solder paste
occupied area
All dimensions in mm.
Fig 20. PCB footprint for SOT687-1 package (reflow soldering).
16.2 Solder paste printing
The process of printing the solder paste requires care because of the fine pitch and
small size of the solder lands. A stencil thickness of 0.125 mm is recommended. The
stencil apertures can be made the same size as the PCB lands in Figure 20.
The type of solder paste recommended for MLF packages is “No clean”, Type 3, due
to the difficulty of cleaning flux residues from beneath the MLF package.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
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DC-to-DC converter powertrain
17. Revision history
Table 6:
Revision history
Rev Date
02
CPCN
20031124
Description
Product data (9397 750 11943)
Modifications:
•
01
20020715
-
Table 5 “Characteristics” on page 6: Min, Typ and Max values changed for VIH, VIL and
td(3-state).
Product data (9397 750 10031)
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Product data
Rev. 02 — 24 November 2003
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DC-to-DC converter powertrain
18. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Definitions
20. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected]
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11943
Rev. 02 — 24 November 2003
19 of 20
Philips Semiconductors
PIP202-12M-2
DC-to-DC converter powertrain
Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
8
9
10
11
11.1
11.2
11.3
11.4
11.5
12
13
14
15
15.1
15.2
16
16.1
16.2
17
18
19
20
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Basic functionality . . . . . . . . . . . . . . . . . . . . . . . 3
MOSFET driver function . . . . . . . . . . . . . . . . . . 4
Bootstrap diode. . . . . . . . . . . . . . . . . . . . . . . . . 4
3-state function . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics. . . . . . . . . . . . . . . . . . . 6
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application information. . . . . . . . . . . . . . . . . . . 9
Typical application. . . . . . . . . . . . . . . . . . . . . . . 9
Advantages of an integrated driver . . . . . . . . . 10
External connection of power and signal lines 10
Switching frequency . . . . . . . . . . . . . . . . . . . . 11
Thermal design. . . . . . . . . . . . . . . . . . . . . . . . 11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 13
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction to soldering MLF packages. . . . . 15
Rework guidelines . . . . . . . . . . . . . . . . . . . . . 16
Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCB design guidelines . . . . . . . . . . . . . . . . . . 16
Solder paste printing. . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
© Koninklijke Philips Electronics N.V. 2003.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 24 November 2003
Document order number: 9397 750 11943