P4C116 P4C116 ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Output Enable Control Function High Speed (Equal Access and Cycle Times) – 10/12/15/20/25/35 ns (Commercial) – 15/20/25/35 ns (Military) Single 5V±10% Power Supply Common Data I/O Fully TTL Compatible Inputs and Outputs Low Power Operation – 633/715 mW Active — 15, 20 – 550/633 mW Active — 25, 35 – 193/220 mW Standby (TTL Input) Produced with PACE II TechnologyTM Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP, SOIC, SOJ – 24-Pin Rectangular LCC (300 x 400 mils) – 28-Pin Square LCC (450 x 450 mils) DESCRIPTION The P4C116 is a 16,384-bit ultra high-speed static RAMs organized as 2K x 8. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V±10% tolerance power supply. Current drain is typically 10 µA from a 2.0V supply. permitting greatly enhanced system operating speeds. CMOS is used to reduce power consumption to a low 633 mW active, 193 mW standby. Access times as fast as 10 nanoseconds are available, The P4C116 is also available in 24-pin rectangular and 28-pin square LCC packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS The P4C116 is available in 24-pin 300 mil DIP, SOJ and SOIC packages providing excellent board level densities. A (6) 16,384-BIT MEMORY ARRAY ROW SELECT A I/O 1 INPUT DATA CONTROL COLUMN I/O I/O 8 COLUMN SELECT WE CE A (5) A0 1 24 A1 A2 2 23 3 22 V CC A10 A9 A3 4 21 WE A4 5 20 OE A5 A6 6 19 A8 7 18 A7 8 17 I/O 1 9 16 CE I/O8 I/O7 I/O 2 10 15 I/O6 I/O 3 11 14 GND 12 13 I/O5 I/O4 DIP (P4, D4), SOJ (J4), SOIC (S4) DIP (P4 , D4), SOJ (J3 ), SOIC (S4 ) TOP VIEW A TOP VIEW OE See Selection Guide Page for LCC Means Quality, Service and Speed 1Q97 47 P4C116 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol Ambient Temp Commercial 0°C to 70°C Gnd 0V Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) RECOMMENDED OPERATING CONDITIONS Grade(2) Parameter (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Vcc Symbol 5.0V ±10% Parameter Conditions Typ. Unit CIN Input Capacitance VIN = 0V 5 pF COUT Output Capacitance VOUT= 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) P4C116 Symbol VIH Parameter Test Conditions Input High Voltage Unit Min Max 2.2 VCC +0.5 V 0.8 V VCC+0.5 V 0.2 V (3) VIL Input Low Voltage VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD Input Clamp Diode Voltage VCC = Min., IIN = –18 mA –1.2 V VOL Output Low Voltage (TTL Load) Output High Voltage (TTL Load) IOL = +8 mA, VCC = Min. 0.4 V VOH –0.5 VCC–0.2 (3) –0.5 IOH = –4 mA, VCC = Min. 2.4 V ILI Input Leakage Current VCC = Max., VIN = GND to VCC –5 +5 µA ILO Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC –5 +5 µA ICC Dynamic Operating Current – 10, 12 VCC = Max., f = Max., Outputs Open 130 mA ICC Dynamic Operating Current – 15, 20 VCC = Max., f = Max., Outputs Open ___ 115 mA ICC Dynamic Operating Current – 25, 35 VCC = Max., f = Max., Outputs Open ___ 100 mA ISB Standby Power Supply Current (TTL Input Levels) CE ≥VIH, VCC = Max., f = Max., Outputs Open ___ 35 mA ISBI Standby Power Supply CE ≥VHC, VCC = Max., f = 0, Outputs Open Current (CMOS Input Levels) VIN ≤VLC or VIN ≥ VHC ___ 17 mA 48 P4C116 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* Temperature Range Commercial Military –10 –12 180 170 –15 160 N/A N/A 170 –20 155 160 –35 –25 150 155 140 150 Unit mA mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. –12 –10 Parameter –20 –15 –25 –35 Unit Min Max Min Max Min Max Min Max Min Max Min Max tRC Read Cycle Time tAA tAC Address Access Time 10 12 15 20 25 35 ns Chip Enable Access Time 10 12 15 20 25 35 ns tOH Output Hold from Address Change 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 3 3 ns tHZ Chip Disable to Output in High Z 5 6 7 8 10 15 ns tOE Output Enable Low to Data Valid 6 8 10 10 15 20 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down 15 12 10 0 0 6 0 0 8 0 0 25 0 7 10 20 0 15 0 20 ns 0 12 9 0 12 35 ns 15 0 20 ns ns 25 ns OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 1 (OE t RC (9) ADDRESS t AA OE t OE CE t OH t OLZ (8) t OHZ(8) t AC t LZ (8) t HZ(8) DATA OUT Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. 49 P4C116 TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) t RC (9) ADDRESS t AA t OH PREVIOUS DATA VALID DATA OUT DATA VALID TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) tRC CE t LZ (8) t HZ t AC DATA VALID DATA OUT I CC VCC SUPPLY CURRENT (8) t PU HIGH IMPEDANCE t PD I SB 50 P4C116 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Parameter Sym. –10 –20 –15 –12 –35 –25 Unit Min Max Min Max Min Max Min Max Min Max Min Max tWC Write Cycle Time 10 12 15 20 25 35 ns tCW Chip Enable Time to End of Write 8 10 12 15 18 25 ns tAW Address Valid to End of Write 8 10 12 15 18 25 ns tAS Address Set-up Time 0 0 0 0 0 0 ns tWP Write Pulse Width 8 10 12 15 18 20 ns tAH Address Hold Time 0 0 0 0 0 0 ns tDW Data Valid to End of Write 7 8 10 12 15 20 ns tDH Data Hold Time 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 6 7 0 8 0 0 10 0 15 0 15 0 ns ns WE CONTROLLED)(10,11) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE t WC (13) ADDRESS t CW CE t AW t WR t AH t WP WE t AS t DW DATA IN t DH DATA VALID t OW(8,12) (8) t WZ DATA OUT (12) DATA UNDEFINED HIGH IMPEDANCE CE CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE t WC (13) ADDRESS t AS t CW CE t AH t WR t AW t WP WE t DW DATA IN t DH DATA VALID DATA OUT (11) HIGH IMPEDANCE Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. 51 P4C116 AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE Mode GND to 3.0V CE OE WE I/O Power Input Rise and Fall Times 3ns Standby H X X High Z Standby Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V DOUT Disabled L H H High Z Active Read L L H DOUT Active Write L X L High Z Active Output Load See Figures 1 and 2 +5 RTH = 166.5 Ω 480Ω DOUT V TH = 1.73 V DOUT 255Ω 30pF(5pF* for tHZ, tLZ , tOHZ, tOLZ , tWZ and tOW) 30pF(5pF* for tHZ, tLZ , tOHZ, tOLZ, tWZ and TOW) Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C116/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 52 P4C116 ORDERING INFORMATION P4C116 Device Type xx x x Speed Package Processing C 0˚C to +70˚C M –55°C to +125°C MB 883 Compliant P Plastic DIP S Plastic SOIC J Plastic SOJ D Ceramic DIP L Ceramic LCC (300 x 400 mils) 24 ld. L28 Ceramic LCC (450 x 450 mils) 28 ld. 10, 12, 15, 20, 25, 35 ns 2K x 8 SRAM The P4C116 is also available to SMD-5962-89690 & 5962-84036 SELECTION GUIDE The P4C116 is available in the following temperature, speed and package options. Temperature Range Commercial Military Temp. Military Processed* Speed (ns) 10 12 15 20 25 35 Plastic DIP Plastic SOIC Plastic SOJ CERDIP (300 mil) LCC (rectangular) LCC (square) –10PC –10SC –10JC N/A N/A N/A –12PC –12SC –12JC –15PC –15SC –15JC –15DM –15LM –15L28M –20PC –20SC –20JC –25PC –25SC –25JC –20DM –20LM –20L28M –25DM –25LM –25L28M –35PC –35SC –35JC –35DM –35LM –35L28M CERDIP (300 mil) LCC (rectangular) LCC (square) N/A N/A N/A N/A N/A N/A Package N/A N/A N/A –15DMB –25DMB –35DMB –20DMB –15LMB –25LMB –35LMB –20LMB –15L28MB –20L28MB –25L28MB –35L28MB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available 24 4 22 A9 A4 5 21 WE A4 A5 A5 6 20 OE A6 7 19 A6 A7 8 18 CE I/O1 I/O2 9 17 I/O8 A6 A7 10 16 I/O7 I/O1 1 1 2 13 14 28 27 2 6 24 WE OE NC 7 23 A6 NC 8 22 NC 9 21 NC 10 20 CE 11 19 I/O8 5 25 1 13 14 15 16 17 I/O6 I/O4 I/O5 18 I/O2 I/O3 GND I/O5 I/O6 I/O 4 12 LCC (L8) TOP VIEW LCC (L5-1) TOP VIEW 53 A9 A 10 V CC A0 26 3 15 I/O 3 GND 11 A1 4 23 2 A3 I/O7 3 A3 A2 V CC A 10 A2 A1 A0 LCC PIN CONFIGURATIONS P4C116 54