ESDALC6V1P6 ® ASD™ QUAD LOW CAPACITANCE TRANSIL™ ARRAY FOR ESD PROTECTION MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : ■ Computers ■ Printers ■ Communication systems and cellular phones ■ Video equipment This device is particularly adapted to the protection of symmetrical signals. FEATURES ■ 4 Unidirectional Transil™ functions ■ Breakdown voltage VBR = 6.1 V min. ■ Low diode capacitance (12pF @ 0V) ■ Low leakage current < 500 nA ■ SOT-666IP (Internal Pad) FUNCTIONAL DIAGRAM Very small PCB area < 2.6 mm2 I/O1 DESCRIPTION The ESDALC6V1P6 is a monolithic array designed to protect up to 4 lines against ESD transients. The device is ideal for situations where board space saving is required. I/O4 GND GND I/O2 I/O3 BENEFITS ■ High ESD protection level ■ High integration ■ Suitable for high density boards COMPLIES WITH THE FOLLOWING STANDARDS: ■ IEC61000-4-2 level 4: 15kV (air discharge) 8kV (contact discharge) ■ MIL STD 883E-Method 3015-7: class3 25kV HBM (Human Body Model) Order Codes Part Number ESDALC6V1P6 July 2004 Marking D REV. 3 1/9 ESDALC6V1P6 ABSOLUTE RATING (Tamb = 25°C) Symbol VPP ESD discharge PPP Tj Tstg Parameter Value ± 15 ±8 Unit 30 W 125 °C -55 to +150 °C 260 °C -40 to +125 °C IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Peak pulse power (8/20µs) (see note 1) Tj initial = Tamb Junction temperature Storage temperature range TL Maximum lead temperature for soldering during 10 s at 5mm for case Top Operating temperature range kV Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit. THERMAL RESISTANCES Symbol Parameter Rth(j-a) Junction to ambient on printed circuit on recommended pad layout ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT VF Voltage temperature coefficient C Rd Capacitance Dynamic resistance Unit °C/W I IF VF VCL VBR VRM V IRM Slope: 1/Rd IPP Forward voltage drop @ IR VBR Part Number ESDALC6V1P6 2/9 Value 220 IRM @ VRM max. Rd αT C typ. max. typ. @ 0V min. max. V V mA µA V Ω 10-4/°C pF 6.1 7.2 1 0.5 3 1.5 4.5 12 ® ESDALC6V1P6 Fig. 1: Peak power dissipation versus initial junction temperature. Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25°C). PPP(W) PPP[Tj initial] / PPP[Tj initial=25°C] 1000 1.1 Tj initial = 25°C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj initial (°C) tp(µs) 0.0 0 25 50 75 100 125 150 10 1 Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25°C). Rectangular waveform tp = 2.5µs. 10 100 Fig. 4: Peak forward voltage drop versus peak forward current (typical values). IFM(A) IPP(A) 1.E+00 100.0 tp = 2.5µs Tj = 125°C Tj = 25°C 10.0 1.E-01 1.0 1.E-02 VFM(V) VCL(V) 0.1 1.E-03 0 10 20 30 40 50 60 70 Fig. 5: Capacitance versus reverse applied voltage (typical values). 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Fig. 6: Relative variation of leakage current versus junction temperature (typical values). IR[Tj] / IR[Tj=25°C] C(pF) 1000 13 F=1MHz VOSC=30mVRMS Tj=25°C 12 11 VR = 3V 10 9 100 8 7 6 5 10 4 3 2 Tj(°C) VR(V) 1 0 1 0 1 ® 2 3 4 5 6 25 50 75 100 125 3/9 ESDALC6V1P6 TECHNICAL INFORMATION Fig. A: Application example. 1. ESD protection by ESDALC6V1P6 I/O2 Connector With the focus of lowering the operation levels, the I/O1 IC problem of malfunction caused by the environment to be is critical. Electrostatic discharge (ESD) is a major I/O4 cause of failure in electronic systems. protected I/O3 As a transient voltage suppressor, ESDALC6V1P6 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDALC6V1P6. ESDALC6V1P6 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDALC6V1P6 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor. Fig. A2: ESD clamping behavior. RG IPP Rd VG RLOAD V(i/o) VBR ESD surge Device to be protected ESDALC6V1P6 I VCL = VBR +Rd x IPP slope = 1 Rd IPP V VBR VCL To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis: R G > Rd ""and""R load > Rd we have: VG V ( i ⁄ o ) = V B R + R d × -------RG The results of the calculation done VG = 8kV, RG = 330Ω (IEC61000-4-2 standard), VBR = 6.4V (typ.) and Rd = 1.5Ω (typ.) give: V ( i ⁄ o ) = 42.8 Volts This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side. 4/9 ® ESDALC6V1P6 Fig. A3: ESD test board. Fig. A4: ESD test condition. ± 15kV ESD Air discharge V(i/o) I/O1, I/O2, I/O3 or I/O4 ± 15kV ESD Air discharge V(i/o) GND ESDALC6V1P6 The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to VBR (positive way, figure A5a) and -VF (negative way, figure A5b). Fig. A5: Remaining voltage during ESD surge. a: Response in the positive way b: Response in the negative way One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b. ® 5/9 ESDALC6V1P6 2. Crosstalk behavior Fig. A6: Crosstalk phenomenon. RG1 Line 1 VG1 RL1 RG2 α1VG1 + β12VG2 Line 2 VG2 α2VG2 + β21VG1 RL2 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG2. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). Fig. A7: Analog crosstalk test configuration. Fig. A8: Typical analog crosstalk response. 0.00 dB 50Ω I/O1 -10.00 unloaded VG -20.00 -30.00 Port 1 -40.00 GND -50.00 -60.00 50Ω I/O4 -70.00 -80.00 Port 2 -90.00 -100.00 100.0k 1.0M 10.0M 100.0M 1.0G f/Hz Figure A7 gives the measurement circuit for the analog crosstalk application. In figure 8, the curve shows the effect of the cell I/O1 on the cell I/O4. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -55dB. 6/9 ® ESDALC6V1P6 Fig. A9: Digital crosstalk test configuration. I/O1 Fig. A10: Typical digital crosstalk response. unloaded VG1 VG1 0 - 5V pulse generator F= 100kHz tR = 20ns GND β21VG1 β21VG1 unloaded I/O4 Figure A9 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A10 shows that in such a condition, ie signal from 0 to 5V and rise time of a few ns, the impact on the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range. 3. PCB layout recommendations As ESD is a fast event, the dI/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that means each nH causes an overvoltage of 30V. Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by reducing parasitic inductances. To ensure that, the following guidelines are recommended : ■ The ESDALC6V1P6 should be placed as close as possible to the input terminals or connectors. ■ The path length between the ESD suppressor and the protected line should be minimized. ■ All conductive loops, including power and ground loops should be minimized. ■ The ESD transient return path to ground should be kept as short as possible. ■ The connections from the ground pins to the ground plane should be the shortest possible. 4. Comparison with varistors Leakage current Protection efficiency Ageing Varistors ---- TRANSIL™ +++ ++ ++ Low leakage current for Transil™ device ■ Improve the autonomy of portable equipments as mobile Better efficiency in terms of ESD protection by using Transil™ device ■ Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be submitted to high voltages in the negative way. ■ Ratio VCL/VBR lower for Transil™ device Less dispersion in terms of VBR No ageing phenomena regarding ESD events with Transil™ device ■ Higher efficiency in terms of ESD protection ■ ® 7/9 ESDALC6V1P6 ORDER CODE ESDA LC 6V1 P6 ESD ARRAY PACKAGE: SOT-666IP VBR min LOW CAPACITANCE ORDERING INFORMATION Part Number ESDALC6V1P6 Marking Package Weight Base qty D SOT-666IP 2.9 mg 3000 Delivery mode Tape & reel REVISION HISTORY Table 1: Revision history Date January-2004 25-May-2004 05-Jul-2004 8/9 Revision 1 2 3 Description of Changes First issue SOT-666 Internal Pad version package change Stylesheet update. No content change. ® ESDALC6V1P6 PACKAGE MECHANICAL DATA SOT-666IP (internal Pad) b e L3 REF. A A3 D D2 E E1 E2 L1 L2 L3 L4 b b1 e e1 Θ L4 L1 b1 e1 Θ(4x) A A3 D E1 E L2 DIMENSIONS Millimeters Inches Min. Max. Min. Max. 0.53 0.60 0.021 0.024 0.13 0.18 0.005 0.007 1.50 1.70 0.059 0.067 1.05 1.25 0.041 0.049 1.50 1.70 0.059 0.067 1.10 1.30 0.043 0.051 0.23 0.43 0.009 0.017 0.11 0.26 0.004 0.010 0.10 0.30 0.004 0.012 0.05 0.002 0.83 Ref 0.032 0.14 0.25 0.006 0.010 0.34 0.013 0.50 Bsc 0.020 0.20 0.008 8° 12° 8° 12° FOOT PRINT DIMENSIONS (in millimeters) 0.36 0.30 0.62 2.30 0.84 0.20 0.20 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com ® 9/9