ESDAxxSC5 ESDAxxSC6 ® Application Specific Discretes A.S.D.™ QUAD TRANSIL ARRAY FOR ESD PROTECTION APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : - Computers - Printers - Communication systems - Cellular phone handsets and accessories - Other telephone set - Set top boxes FEATURES ■ ■ ■ 4 Unidirectional Transil™ Functions Low leakage current: IR max. < 20 µA at VBR 500 W Peak pulse power (8/20 µs) DESCRIPTION The ESDAxxSC5 and ESDAxxSC6 are monolithic voltage suppressors designed to protect components which are connected to data and transmission lines against ESD. They clamp the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transient. BENEFITS High ESD protection level : up to 25 kV High integration Suitable for high density boards COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 : level 4 15kV (air discharge) 8kV (contact discharge) MIL STD 883E-Method 3015-7 : class3B (human body model) May 2002 Ed: 6F SOT23-5L (SC-59) SOT23-6L (SC-59) ESDAxxSC5 ESDAxxSC6 FUNCTIONAL DIAGRAM SOT23-5L 1 5 2 3 4 SOT23-6L 1 6 2 5 3 4 1/9 ESDAxxSC5 / ESDAxxSC6 ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol Test conditions Value Unit VPP ESD discharge - MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge 25 kV PPP Peak pulse power (8/20µs) note1 ESDA5V3SCx ESDA6V1SCx 500 W ESDA14V2SCx ESDA17SC6 ESDA19SC6 ESDA25SC6 300 W 150 °C -55 to +150 °C 260 °C -40 to +125 °C Tj Junction temperature Tstg Storage temperature range TL Lead solder temperature (10 second duration) Top Operating temperature range ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol 2/9 I Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT Voltage temperature coefficient C Capacitance Rd Dynamic resistance VF Forward voltage drop IF VBR VF V RM VCL I RM Rd I PP V ESDAxxSC5 / ESDAxxSC6 VBR min. Types @ IR max. IRM @ VRM Rd αT C max. typ. max. typ. note 1 note 2 0V bias VF @ IF max. V V mA µA V mΩ 10-4/°C pF V mA ESDA5V3SC5 ESDA5V3SC6 5.3 5.9 1 2 3 230 5 280 1.25 200 ESDA6V1SC5 ESDA6V1SC6 6.1 7.2 1 20 5.25 350 6 190 1.25 200 ESDA14V2SC5 ESDA14V2SC6 14.2 15.8 1 5 12 650 10 100 1.25 200 ESDA17SC6 ESDA19SC6 17 19 19 21 1 1 0.075 0.1 14 15 700 800 10 8.5 85 80 1.2 1.2 10 10 ESDA25SC6 25 30 1 1 24 1000 10 60 1.2 10 note 1 : Square pulse, Ipp = 15A, tp=2.5µs. note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C) CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges. I Ipp 2µs t tp = 2.5µs 2.5 s duration measurement wave. 3/9 ESDAxxSC5 / ESDAxxSC6 Fig. 1: Peak power dissipation versus initial junction temperature. Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25 °C). Ppp [Tj initial] / Ppp [Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Ppp(W) 5000 ESDA5V3SC5/SC6 & ESDA6V1SC5/SC6 1000 ESDA14V2SC5/SC6 ESDA17SC6 ESDA19SC6 ESDA25SC6 Tj initial(°C) 0 25 50 75 tp(µs) 100 125 150 Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform (tp = 2.5 µs). 100 1 10 100 Fig. 4: Capacitance versus reverse applied voltage (typical values). C(pF) Ipp(A) 500 50.0 F=1MHz Vosc=30mV ESDA25SC6 ESDA19SC6 10.0 ESDA5V3SC5/SC6 ESDA17SC6 100 ESDA14V2SC5/SC6 ESDA6V1SC5/SC6 ESDA6V1SC5/SC6 1.0 ESDA5V3SC5/SC6 ESDA14V2SC5/SC6 ESDA17SC6 ESDA19SC6 Vcl(V) 0.1 VR(V) tp=2.5µs 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Fig. 5: Relative variation of leakage current versus junction temperature (typical values). 10 1 2 10 20 50 Fig. 6: Peak forward voltage drop versus peak forward current (typical values). IFM(A) IR[Tj] / IR[Tj=25°C] 5.00 500 ESDA17SC6 & ESDA19SC6 ESDA5V3SC5/SC6 ESDA19SC6 ESDA14V2SC5/SC6 & ESDA6V1SC5/SC6 ESDA14V2SC5/SC6 & ESDA6V1SC5/SC6 100 5 ESDA25SC6 ESDA17SC6 1.00 ESDA25SC6 ESDA25SC6 0.10 10 Tj(°C) 1 25 4/9 50 75 ESDA5V3SC5/SC6 VFM(V) 100 125 0.01 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ESDAxxSC5 / ESDAxxSC6 ESD protection by ESDAXXXSCX Electrostatic discharge (ESD) is a major cause of failure in electronic systems. Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of clamping the incoming transient overvoltage to a low enough level such that damage to the protected semiconductor is prevented. They serve as parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. Surface mount TVS arrays offer the best choice for minimal lead inductance. I/ O LINES ESD sensitive device GND ESDAxxxSC6 (1connection to GND for ESDAxxSC5) The ESDAxxSCx array is the ideal board level protection of ESD sensitive semiconductor components. The tiny SOT23-5L and SOT23-6L packages allow design flexibility in the high density boards where the space saving is at a premium. This enables to shorten the routing and contributes to hardening against ESD. ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : The ESDAxxSC5/6 should be placed as close as possible to the input terminals or connectors. ■ ■ ■ ■ ■ The path length between the ESD suppressor and the protected line should be minimized All conductive loops, including power and ground loops should be minimized The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible. 5/9 ESDAxxSC5 / ESDAxxSC6 ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended: The ESDA19SC6 should be placed as close as possible to the input terminals or connectors. The path length between the ESD suppressor and the protected line should be minimized. All conductive loops, including power and ground loops should be minimized. The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible. ■ ■ ■ ■ ■ TECHNICAL INFORMATION ESD PROTECTION The ESDA19SC6 is particularly optimized to perform ESD protection. ESD protection is achieved by clamping the unwanted overvoltage. The clamping voltage is given by the following formula : V CL = V BR + Rd ⋅ Ipp As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor. Fig. A1: ESD clamping behavior (example) Rg Rd Voutput Vg Rload VBR ESD Surge ESDA19SC6 Device to be protected To have a good approximation of the remaining voltages at both VI/O side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis : Rg > Rd and Rload > Rd we have: VOutput = V BR + Rd × Vg Rg The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC61000-4-2 standard), Vbr = 19 V (typ.) and Rd = 0.80 Ω (typ.) give: VOuput = 38.4 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few nanoseconds at the output side. 6/9 ESDAxxSC5 / ESDAxxSC6 ORDER CODE ESDA 6V1 SC6 PACKAGE: SC5: SOT23-5L SC6: SOT23-6L ESD ARRAY VBR min ORDERING INFORMATION ■ Odering Type Marking Package Weight Base qty Delivery mode ESDA5V3SC5 EC53 SOT23-5L 16.7 mg 3000 Tape & reel ESDA5V3SC6 ES53 SOT23-6L 16.7 mg 3000 Tape & reel ESDA6V1SC5 EC61 SOT23-5L 16.7 mg 3000 Tape & reel ESDA6V1SC6 ES61 SOT23-6L 16.7 mg 3000 Tape & reel ESDA14V2SC5 EC15 SOT23-5L 16.7 mg 3000 Tape & reel ESDA14V2SC6 ES15 SOT23-6L 16.7 mg 3000 Tape & reel ESDA17SC6 ES17 SOT23-6L 16.7 mg 3000 Tape & reel ESDA19SC6 ES19 SOT23-6L 16.7 mg 3000 Tape & reel ESDA25SC6 ES25 SOT23-6L 16.7 mg 3000 Tape & reel Epoxy meets UL94-V0 standard 7/9 ESDAxxSC5 / ESDAxxSC6 PACKAGE MECHANICAL DATA SOT23-5L DIMENSIONS A E A2 e D b e REF. Millimeters Min. Typ. Max. Min. Typ. Max. A 0.90 1.45 0.035 0.057 A1 0 0.10 0.004 A2 0.90 1.30 0.035 0.0512 b 0.35 0.50 0.0137 0.02 c 0.09 0.20 0.004 0.008 D 2.80 3.00 0.11 0.118 E 1.50 1.75 0.059 0.0689 e A1 C θ L H 0.60 0.024 8/9 mm inch 1.10 0.043 2.30 0.090 3.50 0.138 1.20 0.047 0.95 0.037 0 0.95 0.0374 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ FOOT PRINT Inches 10° 10° ESDAxxSC5 / ESDAxxSC6 PACKAGE MECHANICAL DATA SOT23-6L DIMENSIONS A E REF. A2 e D b e Millimeters Min. A1 θ L H Min. Typ. Max. 1.45 0.035 0.057 0.10 0.004 A 0.90 A1 0 A2 0.90 1.30 0.035 0.0512 b 0.35 0.50 0.0137 0.02 c 0.09 0.20 0.004 0.008 D 2.80 3.00 0.11 0.118 E 1.50 1.75 0.059 0.0689 e C Typ. Max. Inches 0 0.95 0.0374 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ 10° 10° FOOT PRINT 1.10 0.043 2.30 0.090 3.50 0.138 1.20 0.047 0.60 0.024 mm inch 0.95 0.037 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All rights reserved. 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