STMICROELECTRONICS STP62NS04Z

STP62NS04Z
N-CHANNEL CLAMPED 12.5mΩ - 62A TO-220
FULLY PROTECTED MESH OVERLAY™ MOSFET
VDSS
RDS(on)
ID
CLAMPED
<0.015 Ω
62 A
TYPE
STP62NS04Z
■
■
■
■
TYPICAL RDS(on) = 0.0125 Ω
100% AVALANCHE TESTED
LOW CAPACITANCE AND GATE CHARGE
175 oC MAXIMUM JUNCTION
TEMPERATURE
3
1
DESCRIPTION
2
TO-220
This fully clamped Mosfet is produced by using the latest
advanced Company’s Mesh Overlay process which is
based on a novel strip layout.
The inherent benefits of the new technology coupled with
the extra clamping capabilities make this product
particularly suitable for the harshest operation conditions
such as those encountered in the automotive
environment. Any other application requiring extra
ruggedness is also recommended.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ ABS, SOLENOID DRIVERS
■ POWER TOOLS
Ordering Information
SALES TYPE
STP62NS04Z
MARKING
P62NS04Z
PACKAGE
TO-220
PACKAGING
TUBE
ABSOLUTE MAXIMUM RATINGS
Symbol
VDS
VDG
VGS
ID
ID
IDG
IGS
IDM(•)
Ptot
dv/dt (1)
EAS (2)
VESD
Tstg
Tj
Parameter
Drain-source Voltage (VGS = 0)
Drain-gate Voltage
Gate- source Voltage
Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C
Drain Gate Current (continuous)
Gate SourceCurrent (continuous)
Drain Current (pulsed)
Total Dissipation at TC = 25°C
Derating Factor
Peak Diode Recovery voltage slope
Single Pulse Avalanche Energy
ESD (HBM - C = 100pF, R=1.5 kΩ)
Storage Temperature
Operating Junction Temperature
(•) Pulse width limited by safe operating area.
March 2004
.
Value
CLAMPED
CLAMPED
CLAMPED
62
37.5
± 50
± 50
248
110
0.74
8
500
8
Unit
V
V
V
A
A
mA
mA
A
W
W/°C
V/ns
mJ
kV
-55 to 175
°C
(1) ISD ≤40A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
(2) Starting Tj = 25 oC, ID = 20A, VDD= 20V
1/8
STP62NS04Z
THERMAL DATA
Rthj-case
Rthj-amb
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
(for 10 sec., 1.6mm from case)
Max
Max
°C/W
°C/W
°C
1.36
62.5
300
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)
OFF
Symbol
V(BR)DSS
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Clamped Voltage
ID = 1 mA,
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = 16 V
10
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 10 V
10
µA
VGSS
Gate-Source
Breakdown Voltage
IGS = 100 µA
VGS = 0
33
V
18
V
ON (*)
Symbol
Parameter
Test Conditions
VGS(th)
Gate Threshold Voltage
VDS = VGS
ID = 250 µA
RDS(on)
Static Drain-source On
Resistance
VGS = 10 V
ID = 30 A
Min.
Typ.
Max.
Unit
4
V
12.5
15
mΩ
Typ.
Max.
Unit
2
DYNAMIC
Symbol
2/8
Parameter
Test Conditions
gfs (*)
Forward Transconductance
VDS = 15 V
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS = 25V, f = 1 MHz, VGS = 0
ID=30A
Min.
20
S
1330
420
135
pF
pF
pF
STP62NS04Z
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on Delay Time
Rise Time
VDD = 20 V
ID = 20 A
VGS = 10 V
RG = 4.7 Ω
(Resistive Load, Figure 3)
13
104
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD= 20 V ID= 40 A VGS= 10V
34
10
11.5
47
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbol
Parameter
Test Conditions
Min.
td(off)
tf
Turn-off Delay Time
Fall Time
VDD = 20 V
ID = 20 A
VGS = 10 V
RG = 4.7 Ω
(Resistive Load, Figure 3)
41
42
ns
ns
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
Vclamp = 30 V
ID = 40 A
VGS = 10 V
RG = 4.7Ω,
(Inductive Load, Figure 5)
30
54
90
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
ISD
ISDM (•)
Source-drain Current
Source-drain Current (pulsed)
VSD (*)
Forward On Voltage
ISD = 62 A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 40 A
di/dt = 100A/µs
Tj = 150°C
VDD = 20 V
(see test circuit, Figure 5)
trr
Qrr
IRRM
Test Conditions
Min.
Typ.
VGS = 0
45
65
2.9
Max.
Unit
62
248
A
A
1.5
V
ns
nC
A
(*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
3/8
STP62NS04Z
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STP62NS04Z
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage Temperature.
.
.
5/8
STP62NS04Z
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STP62NS04Z
TO-220 MECHANICAL DATA
DIM.
mm.
MIN.
TYP.
inch.
MAX.
MIN.
TYP.
TYP.
A
4.4
4.6
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
0.107
D1
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.40
2.70
0.094
0.106
H2
10
10.40
0.393
0.409
L2
16.10
16.73
0.633
16.40
0.645
0.658
L4
13
14
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.20
6.60
0.244
0.260
L9
3.50
3.93
0.137
0.154
DIA
3.75
3.85
0.147
0.151
7/8
STP62NS04Z
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners.
© 2004 STMicroelectronics - All Rights Reserved
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