STP7NC40 N-CHANNEL 400V - 0.75Ω - 6A TO-220 PowerMESH™II MOSFET ■ ■ ■ ■ TYPE VDSS RDS(on) ID STP7NC40 400 V <1Ω 6A TYPICAL RDS(on) = 0.75Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW GATE CHARGE 3 1 DESCRIPTION The PowerMESH™II is the evolution of the first generation of MESH OVERLAY™. The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concerns swithing speed, gate charge and ruggedness. 2 TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 400 V Drain-gate Voltage (RGS = 20 kΩ) 400 V Gate- source Voltage ± 30 V 6 A ID Drain Current (continuos) at TC = 25°C ID Drain Current (continuos) at TC = 100°C 4 A Drain Current (pulsed) 24 A Total Dissipation at TC = 25°C 100 W Derating Factor 0.8 W/°C IDM (●) PTOT dv/dt(1) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (●) Pulse width limited by safe operating area March 2001 3 V/ns –65 to 150 °C 150 °C (1)ISD ≤6A, di/dt ≤100A/µs, VDD ≤ V (BR)DSS, T j ≤ T JMAX. 1/8 STP7NC40 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 1.25 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Max Value Unit 6 A 320 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating Gate-body Leakage Current (VDS = 0) VGS = ±30V Min. Typ. Max. 400 Unit V VDS = Max Rating, TC = 125 °C 1 µA 50 µA ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 3 A ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS = 10V Min. Typ. Max. Unit 2 3 4 V 0.75 1 Ω 6 A DYNAMIC Symbol gfs (1) 2/8 Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 3 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. Max. Unit 5.1 S 530 pF Ciss Input Capacitance Coss Output Capacitance 90 pF Crss Reverse Transfer Capacitance 15 pF STP7NC40 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. VDD = 200V, ID = 3 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 320V, ID =6A, VGS = 10V Typ. Max. Unit 11 ns 15 ns 18 4 8.5 23 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol td(off) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions Min. 8 12 23 Vclamp =320V, ID = 6 A RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) ns ns ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 6 A ISDM (2) Source-drain Current (pulsed) 24 A VSD (1) Forward On Voltage ISD = 6 A, VGS = 0 1.6 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 6 A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) ISD trr Qrr IRRM Parameter Test Conditions Min. Typ. 280 1.4 10 ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedence 3/8 STP7NC40 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP7NC40 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STP7NC40 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP7NC40 TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/8 STP7NC40 Information furnished is believed to be accurate and reliable. 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