UTC 4052 CMOS ANALOG MULTIPLEXERS /DEMULTIPLEXERS DESCRIPTION The UTC 4052 analog multiplexers is digitally –controlled analog switch. The device feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. SOP-16 FEATURES *Triple Diode Protection on Control Inputs *Switch Function is Break Before Make *Supply Voltage Range=3.0 Vdc to 18 Vdc *Analog Voltage Range(VDD-VEE)=3.0 to 18V *Note:VEE must be≤Vss *Linearized Transfer Characterisstics *Low-noise-12nV/√Cycle ,f≥1.0kHz Typical DIP-16 ABSOLUTE MAXIMUM RATINGS*1 PARAMETER SYMBOL RATING VDD -0.5 ~ +18.0 DC Supply Voltage (Referenced to VEE,Vss≥VEE) Input or Output Voltage (DC or Transient) (Referenced to Vin,Vout -0.5 ~ VDD+0.5 Vss for Control Inputs and VEE for switch I/O) Input Current (DC or Transient) per Control Pin Iin ±10 Switch Through Current ISW ±25 Power Dissipation *2 700 PD DIP-16 500 SOP-16 Ambient Temperature Range TA -55 ~ +125 Storage Temperature Range Tstg -65 ~ +150 Lead Temperature (8-Second Soldering) TLEAD 260 *1. Maximum Ratings are those values beyond which damage to the device may occur. *2. Temperature Derating : 7.0 mW/℃ From 65℃ ~ 125℃ UTC UNISONIC TECHNOLOGIES CO., LTD. UNIT V V mA mA mW °C °C °C 1 QW-R502-013,A UTC 4052 CMOS Dual 4-Channel Analog Multiplexer/Demultiplexer 6 CONTROLS SWITCHES IN/OUT PIN ASSIGMENT INHIBIT 10 9 A B 12 14 X0 X1 15 11 X2 X3 1 5 Y0 Y1 2 4 Y2 Y3 X COMMONS OUT/IN Y Y0 1 16 VDD Y2 2 15 X2 Y 3 14 X1 Y3 4 13 X Y1 5 12 X0 INH 6 11 X3 VEE 7 10 A Vss 8 9 B 13 9 VDD=PIN16, VSS=PIN8, VEE=PIN7 Note: Control Inputs referenced to Vss. Analog Inputs and Outputs reference to VEE. VEE must be <Vss. ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITIONS SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Current Per VDD VDD-3.0≥Vss≥VEE Range Quiescent Current Per Package -55°C MIN MAX MIN 3.0 18 3.0 25°C 125°C UNIT TYP*3 MAX MIN MAX 18 3.0 Control Inputs: Vin=Vss or VDD,Switch I/O : VEE≤VI/O≤≤VDD, and△Vswitch≤500mV *4 5.0 0.005 5.0 VDD=5.0V 10 0.010 10 VDD=10V 20 0.015 20 VDD=15V Total Supply Current ID(AV) TA=25℃only (The (Dynamic Plus channel component, Quiescent, Per (Vin-Vout) /Ron, is not Package included.) VDD=5.0V (0.07µA/kHz)f+IDD VDD=10V Typical (0.20µA/kHz)f+IDD VDD=15V (0.36µA/kHz)f+IDD CONTROL INPUTS-INHIBIT, A, B, C (Voltages Referenced to Vss) Low-Level Input VIL Ron=per spec, Voltage Ioff=per spec VDD=5.0V 1.5 2.25 1.5 3.0 4.50 3.0 VDD=10V 4.0 6.75 4.0 VDD=15V High-Level Input VIH Ron=per spec, Voltage Ioff=per spec 3.5 3.5 2.75 3.5 VDD=5.0V 7.0 7.0 5.50 7.0 VDD=10V 11 11 8.25 11 VDD=15V UTC 18 V IDD UNISONIC TECHNOLOGIES CO., LTD. 150 300 600 µA µA 1.5 3.0 4.0 V - V 2 QW-R502-013,A UTC 4052 PARAMETER CMOS SYMBOL TEST CONDITIONS -55°C MIN MAX MIN 25°C 125°C UNIT TYP*3 MAX MIN MAX Input Leakage Iin VDD=15V ,Vin=0 or VDD ±0.1 ±10-5 ±0.1 Current Input Capacitance Cin 5.0 7.5 SWITCHES IN/OUT AND COMMONS OUT/IN –X,Y,Z(Voltages Referenced to VEE) Recommended VI/O Peak-to-Peak Voltage Into or Out of the Switch Recommended Static △Vswitch or Dynamic Voltage Across the Switch *4 (Figure 3) Output Offset Voo Voltage ON Resistance Ron △ON Resistance Between Any Two Channels in the Same Package Off-Channel Leakage Current(Figure 8) △Ron Ioff 1.0 µA pF Channel On or Off 0 VDD 0 VDD 0 VDD Vpp Channel On 0 600 0 600 0 300 mV Vin=0V,No Load 10 µV 4 △Vswitch≤500mV * Vin=VIL or VIH (Control), and Vin=0 to VDD(Switch) VDD=5.0V VDD=10V VDD=15V VDD=5.0V VDD=10V VDD=15V 800 400 220 250 120 80 1050 500 280 1200 520 300 70 50 45 25 10 10 70 50 45 135 95 65 VDD=15V ,Vin=VIL or VIH ±100 ±0.05 ±100 ±1000 (Control) Channel to Channel or Any One Channel Ω Ω nA Capacitance, CI/O Inhibit=VDD 10 pF Switch I/O Capacitance, CO/I Inhibit=VDD 32 pF Common O/I Capacitance, CI/O Pins Not Adjacent 0.15 pF Feedthrough Pins Adjacent 0.47 (Channel Off) *3. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential *performance. *4. For voltage drops across the switch (△Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD *current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The *reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data *sheet.) UTC UNISONIC TECHNOLOGIES CO., LTD. 3 QW-R502-013,A UTC 4052 CMOS ELECTRICAL CHARACTERISTICS *5 (CL = 50 pF, TA = 25℃) (VEE PARAMETER SYMBOL Propagation Delay Times(Figure 4) Switch Input to Switch Output tPLH,tPHL RL=10kΩ Propagation Delay Times(Figure 4) Inhibit to Output tPHZ,tPLZ RL=10kΩ,VEE=Vss tPZH,tPZL Output”1” or “0” to High Impedance, or High Impedance to”1” or “0” Level VDD-VEE= 5.0 VDD-VEE=10 VDD-VEE=15 tPLN,tPHL RL=10kΩ,VEE=Vss VDD-VEE= 5.0 VDD-VEE=10 VDD-VEE=15 RL=10kΩ, f=1kHz, Vin=5Vpp, VDD-VEE=10 VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns Propagation Delay Times(Figure 4) Control Input to Output Second Harmonic Distortion Bandwidth (Figure 5) ≤VSS unless otherwise indicated) TEST CONDITIONS BW RL=1kΩ, Vin=1/2(VDD-VEE)p-p, CL=50pF, 20 Log (Vout/Vin)=-3dB, VDD-VEE=10 RL=1kΩ, Vin=1/2(VDD-VEE)p-p, Fin=30MHz, VDD-VEE=10 *6 MIN TYP MAX UNIT 30 12 10 75 30 25 300 155 125 600 310 250 325 130 90 650 260 180 0.07 17 ns ns ns % MHz Off Channel -50 Feedthrough Attenuation dB (Figure 5) Channel Separation -50 RL=1kΩ, Vin=1/2(VDD-VEE)p-p, fin=3.0MHz, dB (Figure 6) VDD-VEE=10 Crosstalk ,Control Input 75 R1=1kΩ, RL=10kΩ, to Common O/I (Figure mV Control tTLH=tTHL=20ns ,Inhibit=Vss), VDD-VEE=10 7) *5. The formulas given are for the typical characteristics only at 25 ℃. *6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential *performance. UTC UNISONIC TECHNOLOGIES CO., LTD. 4 QW-R502-013,A UTC 4052 CMOS VDD VDD VDD IN/OUT OUT/IN VEE VDD LEVEL CONVERTED CONTROL OUT/IN IN/OUT CONTROL VEE Figure 1.Switch Circuit Schematic 16 TRUTH TABLE Control Inputs Select Inhibit 0 0 0 0 1 B 0 0 1 1 X INH A B 6 10 9 X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 ON Switches A 0 1 0 1 X Y0 X0 Y1 X1 Y2 X2 Y3 X3 None VDD LEVEL CONVERTER 8 Vss 7 BINARY TO 1-OF-4 DECODER WITH INHIBIT VEE 13 X * X=Don't Care 3 Y Figure 2. Functional Diagram TEST CIRCUITS UTC UNISONIC TECHNOLOGIES CO., LTD. 5 QW-R502-013,A UTC 4052 CMOS ON SWITCH CONTROL SECTION OF IC A PULSE GENERATOR B C Vout LOAD CL RL INH V SOURCE VDD VEE VEE VDD Figure 4. Propagation Delay Times, Control and Inhibit to Output Figure 3.→△V Across Switch A,B,and C inputs used to tum ON or OFF the switch under tes. A A B C B C Vout RL INH Vss OFF CL=50pF INH Vin VDD VEE 2 2 Figure 5. Bandwidth and Off-Channe Feedthrough Attenuation Vout RL CL=50pF Vin VDD VEE UTC RL ON Figure 6. Channel Separation (Adjacent Channels Used For Setup) UNISONIC TECHNOLOGIES CO., LTD. 6 QW-R502-013,A UTC 4052 CMOS OFF CHANNEL UNDER TEST A B C RL INH CONTROL SECTION OF IC Vout CL=50pF OTHER CHANNEL(S) R1 VDD VEE VEE VDD VEE COMMON VDD Figure 7. Crosstalk,Control Input to Common O/I VDD Figure 8. Off Channel Leakage KEITHLEY 160 DIGITAL MULTIMETER 10K VDD 1kΩ RANGE X-Y PLOTTER VEE=VSS Figure 9. Channel Resistance(RON) Test Circuit 350 300 250 200 150 TA=125℃ 100 25℃ 50 -55℃ 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 Vin,INPUT VOLTAGE (VOLTS) Figure10.VDD=7.5V,VEE=-7.5V UTC RON,"ON" RESISTANCE (OHMS) RON,"ON" RESISTANCE (OHMS) TYPICAL RESISTANCE CHARACTERISTIS 350 300 250 200 150 100 50 TA=125℃ 25℃ -55℃ 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 Vin,INPUT VOLTAGE (VOLTS) Figure11.VDD=5.0V,VEE=-5.0V UNISONIC TECHNOLOGIES CO., LTD. 7 QW-R502-013,A UTC 4052 CMOS 700 350 600 300 RON,"ON" RESISTANCE (OHMS) RON,"ON" RESISTANCE (OHMS) TA=25℃ 500 400 300 TA=125℃ 200 25℃ 100 -55℃ 250 150 5.0V 100 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 VDD=2.5V 200 7.5V 50 0 -10 10 -8.0 -6.0 Vin,INPUT VOLTAGE (VOLTS) -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (VOLTS) Figure13 Comparison at 25℃,VDD=-VEE Figure12.VDD=2.5V,VEE=-2.5V Figure A illustrates use of the on–chip level converter detailed in Figures 2. The 0 ~ 5 V Digital Control signal is used to directly control a 9 Vp–p analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD – VSS = 5 V maximum swing above VSS; VSS – VEE = 5 V maximum swing below VSS. The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VEE. Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10 V, VSS = + 5 V, and VEE – 3 V is acceptable. See the Table below. +5V -5V VDD Vss VEE +4.5V +5V 9 Vp-p SWITCH ANALOG SIGNAL I/O 4052 EXTERNAL CMOS DIGITAL CIRCUITRY 0 ~ 5V DIGITAL CONTROL SIGNALS COMMON O/I 9 Vp-p ANALOG SIGNAL INHIBIT, A,B,C GND -4.5V Figure A. Application Example UTC UNISONIC TECHNOLOGIES CO., LTD. 8 QW-R502-013,A UTC 4052 CMOS V DD V DD Dx Dx AN ALO G I/O C O MMO N O /I Dx Dx VEE VEE Figure B.External G ermanium or Schottky C lipping D iodes POSSIBLE SUPPLY CONNECTIONS VDD IN VOLTS VSS IN VOLTS VEE IN VOITS CONTROL INPUTS LOGIC HIGH/LOGIC LOW IN VOLTS +8 +5 +5 +5 +10 0 0 0 0 +5 -8 -12 0 -5 -5 +8/0 +5/0 +5/0 +5/0 +10/+5 UTC MAXIMUM ANALOG SIGNAL RANGE IN VOLTS +8 ~ -8=16Vp-p +5 ~–12=17Vp-p +5 ~ 0=5Vp-p +5 ~ -5=10Vp-p +10 ~ –5=15Vp-p UNISONIC TECHNOLOGIES CO., LTD. 9 QW-R502-013,A