ETC T68R1MDI-10

T68 K/S/R 1M Family
Low Power 1M (128Kx8)-Bits Static RAM
¢
DESCRIPTION
The T68K1M, T68S1M, and T68R1M device family is a low power and high performance
CMOS SRAM organized as 131,072 words by 8 bits. It operates from 2.7V to 3.6V, 2.2V to
2.7V, and 1.65V to 2.2V. Easy memory expansion is provided by an active LOW chip enable 1
(/CE1), active HIGH chp enable 2 (CE2) and active LOW output enable (/OE) and three-state
I/O drivers. Four control pins (/CE1, CE2, /OE, and /WE) fully control the operation mode of the
T68 K/S/R 1M device family. An active LOW write enable signal (/WE active low) controls the
write/read operation of the memory. When /CE1 and /WE inputs go LOW and CE2 input goes
HIGH simultaneously, the device is in write mode and data on the 8 data pins (IO1~IO8) is
written into the memory location specified by the address on address pins (A0~A16). When
/CE1 and /OE inputs go LOW and CE2 and /WE input stay in HIGH state, the device is in read
mode and data in the specified memory address is driven onto the 8 data pins. The 8 data pins
will be in high -impedance state if both /OE and /WE pins are in HIGH (inactive) state. The T68
K/S/R 1M device family has an automatically power-down feature when the chip is deselected
(/CE1 pin HIGH or CE2 pin LOW). The T68 K/S/R 1M device family is available in JEDEC
standard 32-pin 450-mil SOP, 32-pin 8mmx20mm plastic TSOP, 32-pin 8mmx13.4mm plastic
STSOP, and 36-ball 6mmx8mm BGA package, also for DICE.
¢
FEATURES
—
Operation voltage… … … … … … T68K1M… … … … … … … … … … … ................. 2.7V ~ 3.6V
T68S1M… … … … … … … … … … … … … … … .. 2.2V ~ 2.7V
T68R1M… … … … … … … … … … .................. 1.65V ~ 2.2V
— Low active power and standby power
— High access times: 70ns/85ns/100ns
—
TTL-compatible inputs and outputs
— Easy memory expansion with /CE1, CE2 and /OE
—
Low data retention voltage… … … … … … … … … … ..2.0V (for K), 1.5V (for S), 1.0V (for R)
—
Auto power down when deselected
2003-REV 090
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T68 K/S/R 1M
¢ PRODUCT FAMILY
Part Number
VCC Range
Speed
Operating
Temperature
Power Dissipation
Operating
Standby
(ICC2, Max.)
(ISB1, Max.)
Type
T68K1MGC -7/-8
SOP-32
T68K1MTC -7/-8
TSOP-32
T68K1MSC -7/-8
2.7V~3.6V
20mA
3uA
T68K1MBC -7/-8
Dice
70ns/ 85ns
T68S1MGC -7/-8
SOP-32
T68S1MTC -7/-8
T68S1MSC -7/-8
STSOP-32
BGA-36
T68K1MDC -7/-8
TSOP-32
Commercial
2.2V~2.7V
o
o
(+0 C~+70 C)
20mA
3uA
T68S1MBC -7/-8
STSOP-32
BGA-36
T68S1MDC -7/-8
Dice
T68R1MGC -8/-10
SOP-32
T68R1MTC -8/-10
T68R1MSC -8/-10
TSOP-32
1.65V~2.2V
85ns/ 100ns
15mA
2uA
STSOP-32
T68R1MBC -8/-10
BGA-36
T68R1MDC -8/-10
Dice
Part Number
VCC Range
Speed
Operating
Temperature
Power Dissipation
Operating
Standby
(ICC2, Max.)
(ISB1, Max.)
Package
Type
T68K1MGE -7/-8
SOP-32
T68K1MTE -7/-8
TSOP-32
T68K1MSE -7/-8
2.7V~3.6V
20mA
3uA
T68K1MBE -7/-8
STSOP-32
BGA-36
T68K1MDE -7/-8
Dice
70ns/ 85ns
T68S1MGE -7/-8
SOP-32
T68S1MTE -7/-8
TSOP-32
T68S1MSE -7/-8
Extended
2.2V~2.7V
o
o
(-25 C~+85 C)
20mA
3uA
T68S1MBE -7/-8
STSOP-32
BGA-36
T68S1MDE -7/-8
Dice
T68R1MGE -8/-10
SOP-32
T68R1MTE -8/-10
T68R1MSE -8/-10
16
Package
TSOP-32
1.65V~2.2V
85ns/ 100ns
15mA
2uA
STSOP-32
T68R1MBE -8/-10
BGA-36
T68R1MDE -8/-10
Dice
TIWIN Semiconductor • www.tiwin.com.tw • Tel :(886)-3 -5636031 • Fax:(886)-3-5644823
2003-REV 090
T68 K/S/R 1M
Part Number
VCC Range
Speed
Operating
Temperature
Power Dissipation
Operating
Standby
(ICC2, Max.)
(ISB1, Max.)
Package
Type
T68K1MGI -7/-8
SOP-32
T68K1MTI -7/-8
TSOP-32
68K1MSI -7/-8
2.7V~3.6V
20mA
3uA
T68K1MBI -7/-8
BGA-36
T68K1MDI -7/-8
Dice
70ns/ 85ns
T68S1MGI -7/-8
SOP-32
T68S1MTI -7/-8
T68S1MSI -7/-8
STSOP-32
TSOP-32
Industrial
2.2V~2.7V
o
o
(-40 C~+85 C)
20mA
3uA
T68S1MBI -7/-8
STSOP-32
BGA-36
T68S1MDI -7/-8
Dice
T68R1MGI -8/-10
SOP-32
T68R1MTI -8/-10
T68R1MSI -8/-10
TSOP-32
1.65V~2.2V
85ns/ 100ns
15mA
2uA
STSOP-32
T68R1MBI -8/-10
BGA-36
T68R1MDI -8/-10
Dice
2003-REV 090
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17
T68 K/S/R 1M
¢
18
PIN CONFIGURATION
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2003-REV 090
T68 K/S/R 1M
¢
LOGIC BLOCK
¢
(PIN DESCRIPTION)
2003-REV 090
Pin Name
Function
A0 ~ A16
Address Input Pins
IO1 ~ IO8
Data Input/Output Pins
/CE1
Chip Enable 1 Input Pin
CE2
Chip Enable 2 Input Pin
/OE
Output Enable Input Pin
/WE
Write Enable Input Pin
VCC
Power Supply Pin
VSS
Ground Pin
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19
T68 K/S/R 1M
¢
TRUTH TABLE
Mode
/CE1
CE2
/WE
/OE
I/O1~8
Power
(1)
Deselected
H
X
X
High-Z
Standby
Deselected
X
X
L
X
X
High-Z
Standby
Write
L
H
L
X
Input
Active
Read
L
H
H
L
Output
Active
Output Disabled
L
H
H
H
High-Z
Active
1. ’X’ means don’t care. Must be in high or low state.
¢
ABSOLUTE MAXINUM RATINGS (1)
Symbol
VCC
Parameter
Rating
Unit
-0.5 ~ Vcc.max+1V
Power Supply Voltage (to VSS)
(2)
-0.5 ~ Vcc.max+0.3V
VIN/VOUT Input / Output Voltage
I OUT
PD
TSTG
TSOLDER
TA
-0.5 ~ Vcc+0.5V
(2)
-0.5 ~ Vcc+0.3V
(3)
Output Current into Outputs (LOW)
20
Power Dissipation
1.0
Storage Temperature
-65 ~ +150
V
V
V
V
mA
W
O
C
O
C
O
Soldering Temperature and Time
Operating Temperature
(3)
260 C , 10sec (Lead Only)
C-Grade
0 ~ 70
E-Grade
-25 ~ 85
I-Grade
-40 ~ 85
1. Stresses greater than those listed in the Absolute Maximum Ratings table may cause permanent damage
to the device.Functional operation should be restricted to recommended operating condition. Exposure to
absolute maximum ratings conditions for extended periods may affect reliability.
2. For K and S family.
3. For R family.
20
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2003-REV 090
T68 K/S/R 1M
¢
RECOMMENDED DC OPERATING RANGE
Symbol
Parameter
T68K1M
VCC
Supply Voltage
T68S1M
Unit
V
2.2 ~ 2.7
V
1.65 ~ 2.2
V
0
V
2.2 ~ VCC+0.5
V
2.0 ~ VCC+0.5
V
T68R1M
1.4 ~ VCC+0.5
V
T68K1M
-0.5 ~ 0.6
V
-0.5 ~ 0.6
V
-0.5 ~ 0.4
V
T68R1M
VSS
Ground
T68K1M
VIH
T68S1M
VIL
T68S1M
Input High Voltage
Input Low Voltage
T68R1M
¢
Rating
2.7 ~ 3.6
CAPACITANCES (1)
Symbol
Parameter
Min.
Max.
Condition
C IN
Input Capacitance
-
8pF
Unmeasured pins set
10pF
to 0V
C IO
Input/Output Capacit ance
1. The Capacitances listed in the above table are sampled, not 100% tested.
¢ DATA RENTATION CHARACTERISTICS
Symbol
VDR
Parameter
VCC for Data
Retention
Test Condition
Min.
Typ.
Max.
2.0
-
3.6
1.5
-
2.7
1.0
-
2.2
C-Grade
-
-
2
E-Grade
-
-
3
I-Grade
-
-
3
C-Grade
-
-
1
E-Grade
-
-
2
I-Grade
-
-
2
C-Grade
-
-
1
E-Grade
-
-
2
I-Grade
-
-
2
0
-
-
ns
TRC
-
-
ns
T68K1M
T68S1M
Standby Mode
T68R1M
T68K1M
I DR
Data Retention
Current
T68S1M
T68R1M
TSDR
Data Retention Setup Time
VCC=2.0V and
CMOS Standby mode
(1)
VCC=1.5V and
CMOS Standby mode
(1)
VCC=1.0V and
CMOS Standby mode
(1)
See data retention waveform
TRDR
Data Retention Recovery Time
Note: 1. Standby mode: /CE1≥Vcc-0.2V or CE2≤ Vss+0.2V
2003-REV 090
Unit
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V
uA
21
T68 K/S/R 1M
¢
DC ELECTRICAL CHARACTERISTICS
Symbol
I LI
I LO
Min
Typ
Max
Unit
Input Leakage Current
Parameter
VIN = VSS to VCC
-1
-
1
µA
Output Leakage Current
/CE1=VIH CE2=VIL or /OE=VIH
or /WE=VIL, VIO =VSS to VCC
-1
-
1
µA
(1)
6
(1)
6
I CC1
Average Operating Current
I CC2
VOL
VOH
Output Low Voltage
Output High Voltage
Test Condition
T68K1M /CE1≤0.2V, CE2≥VCC-0.2V,
VIN≤0.2V or VIN≥VCC- 0.2V
T68S1M
Cycle time = 1µs, 100%duty,
T68R1M I IO =0mA
-
-
2
T68K1M /CE1=VIL, CE2=VIH, VIN=VIH or
VIN=VIL,
T68S1M
Cycle time = min, 100% duty,
T68R1M I IO =0mA
-
15
-
15
-
T68K1M IOL = 2.0mA
T68S1M IOL = 0.5mA
T68R1M IOL = 0.2mA
I SB1
TTL Standby Current
CMOS Standby Current
3
(1)
20
(1)
20
10
(1)
15
-
-
0.4
-
-
0.4
-
-
0.4
T68K1M IOH = -1.0mA
2.2
-
-
T68S1M IOH = -0.5mA
2.0
-
-
T68R1M IOH = -0.1mA
1.4
-
-
-
-
0.2
-
-
0.2
T68R1M
-
-
0.2
T68K1M /CE1≥VCC-0.2V or
T68S1M CE2≤VSS+0.2V ,
-
1.0
-
1.0
T68R1M other inputs = 0 to VCC
-
0.8
T68S1M
/CE1=VIH or CE2= VIL,
other inputs = VIH or VIL
mA
4
(1)
T68K1M
I SB
-
3
(1)
3
(1)
3
(1)
2
mA
V
V
mA
µA
o
Note: 1. Ta=25 C, VCC=3.0V (K), VCC=2.5V (S), and VC C=1.8V (R), not 100% tested.
22
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2003-REV 090
T68 K/S/R 1M
¢
AC ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
˜
Input Pulse Level: 0.2Vcc(≦ViL), 0.8Vcc(≧VIH)
Input Rising and Falling Time: 5ns
Input and Output Reference Voltage: 0.9V(R), 1.1V(S), 1.5V (K)
Output Load: CL = 30pF + one TTL gate
˜
READ CYCLE
Speed Bin
Symbol
˜
Parameter List
-7 (70ns)
-8(85ns)
-10(100ns)
Units
Min
Max
Min
Max
Min
70
-
85
-
100
-
ns
Address Access Time
-
70
-
85
-
100
ns
t CO
Chip Select to Output
-
70
-
85
-
100
ns
t OE
Output Enable to Valid Output
-
35
-
40
-
50
ns
t LZ
Chip Select to Low-Z Output
10
-
10
-
10
-
ns
t OLZ
Output Enable to Low-Z Output
5
-
5
-
5
-
ns
t HZ
Chip Disable to High-Z Output
0
25
0
25
0
30
ns
t OHZ
Output Disable to High-Z Output
0
25
30
ns
t OH
Output Hold From Address
10
-
-
ns
t RC
Read Cycle Time
t AA
25
10
-
15
Max
WRITE CYCLE
Speed Bin
Symbol
2003-REV 090
Parameter List
-7 (70ns)
-8(85ns)
-10 (100ns)
Min
Max
Min
Max
Min
Max
Units
t WC
Write Cycle Time
70
-
85
-
100
-
ns
t CW
Chip Select to End of Write
60
-
70
-
80
-
ns
t AS
Address Setup Time
0
-
0
-
0
-
ns
t AW
Address Valid to End of Write
60
-
70
-
80
-
ns
t WP
Write Pulse Width
55
-
60
-
70
-
ns
t WR
Write Recovery Time
0
-
0
-
0
-
ns
t WHZ
Write to Output High-Z
0
25
0
25
0
30
ns
t DW
Data to Write Time Overlap
30
-
35
-
40
-
ns
t DH
Data Hold from Write Time
0
-
0
-
0
-
ns
t OW
End Write to Output Low-Z
5
-
5
-
5
-
ns
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23
T68 K/S/R 1M
¢
TIMING DIAGRAMS
˜ TIMEING WAVEFORM OF READ CYCLE (1)
(Address Controlled, /CE1=/OE=VIL, CE2=/WE=VIH)
˜ TIMEING WAVEFORM OF READ CYCLE (2) (/WE=VIH)
24
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2003-REV 090
T68 K/S/R 1M
˜
TIMING WAVEFORM OF WRITE CYCLE (1) (/WE Controlled)
˜ TIMING WAVEFORM OF WRITE CYCLE (2) (/CE1 OR CE2 Controlled)
2003-REV 090
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25
T68 K/S/R 1M
˜ DATA RETENTION WAVEFORM (1) (/CE1 Controlled)
˜ DATA RETENTION WAVEFORM (2) (CE2 Controlled)
26
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2003-REV 090
T68 K/S/R 1M
¢
PACKAGE DIMENSION
32L PIN SOP (445 mil)
32L PIN TSOP (8x20)
2003-REV 090
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27
T68 K/S/R 1M
32L PIN TSOP (8x13.4)
36 BALL BGA ( 6mm x 8mm)
28
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2003-REV 090