STP80NS04ZB N-CHANNEL CLAMPED 7.5mΩ - 80A TO-220 FULLY PROTECTED MESH OVERLAY™ MOSFET PRELIMINARY DATA ■ ■ ■ ■ TYPE VDSS RDS(on) ID STP80NS04ZB CLAMPED <0.008 Ω 80 A TYPICAL RDS(on) = 0.0075 Ω 100% AVALANCHE TESTED LOW CAPACITANCE AND GATE CHARGE 175 oC MAXIMUM JUNCTION TEMPERATURE 3 1 DESCRIPTION This fully clamped Mosfet is produced by using the latest advanced Company’s Mesh Overlay process which is based on a novel strip layout. The inherent benefits of the new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions such as those encountered in the automotive environment. Any other application requiring extra ruggedness is also recommended. 2 TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ ABS, SOLENOID DRIVERS ■ MOTOR CONTROL ■ DC-DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDG VGS ID ID IDG IGS IDM(•) Ptot VESD(G-S) VESD(G-D) VESD(D-S) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Gate Current (continuous) Gate SourceCurrent (continuous) Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Gate-Source ESD (HBM - C = 100pF, R=1.5 kΩ) Gate-Drain ESD (HBM - C = 100pF, R=1.5 kΩ) Drain-source ESD (HBM - C = 100pF, R=1.5 kΩ) Storage Temperature Max. Operating Junction Temperature Value CLAMPED CLAMPED CLAMPED 80 60 ± 50 ± 50 320 200 1.33 4 4 4 -65 to 175 -40 to 175 Unit V V V A A mA mA A W W/°C kV kV kV °C °C (•) Pulse width limited by safe operating area. May 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/6 STP80NS04ZB THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 0.75 62.5 300 °C/W °C/W °C Max Value Unit AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 80 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 30 V) 500 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit Clamped Voltage ID = 1 mA, VGS = 0 -40 < TJ < 175 oC IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = 16 V VDS = 16 V VDS = 16 V Tc=25 oC TJ =150 oC TJ =175 oC 10 50 100 µA µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 10 V VGS = ± 16 V TJ =175 oC TJ =175 oC 50 150 µA µA VGSS Gate-Source Breakdown Voltage IGS = 100 µA V(BR)DSS 33 V 18 V ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 1 mA -40 < TJ < 150 oC RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 16 V ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS = 10V Min. Typ. Max. Unit 1.7 3 4.2 V 8 7.5 9 8 mΩ mΩ ID = 40 A ID = 40 A 80 A DYNAMIC Symbol 2/6 Parameter Test Conditions Min. Typ. 30 50 gfs (*) Forward Transconductance VDS>ID(on)xRDS(on)max ID=40A Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2700 1275 285 Max. Unit S 3300 1600 350 pF pF pF STP80NS04ZB ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Qg Qgs Qgd Parameter Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. VDD= 20 V ID= 80 A VGS= 10V Typ. Max. Unit 80 20 27 105 nC nC nC Typ. Max. Unit 115 80 210 150 105 280 ns ns ns Typ. Max. Unit 80 320 A A 1.5 V SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions Min. ID = 80 A Vclamp = 30 V RG = 4.7Ω, VGS = 10 V (Inductive Load, Figure 5) SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 80 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 80 A VDD = 25 V Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Test Conditions Min. VGS = 0 90 0.18 4 ns µC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. 3/6 STP80NS04ZB Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STP80NS04ZB TO-220 MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 4.40 TYP. 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 TYP. 1.27 MAX. 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 L2 0.409 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 5/6 STP80NS04ZB Information furnished is believed to be accurate and reliable. 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