CALOGIC SST109

N-Channel JFET Switch
CORPORATION
J108 – J110 / SST108 – SST110
FEATURES
Low Cost
Automated Insertion Package
Low Insertion Loss
No Offset or Error Voltages Generated by Closed Switch
Purely Resistive
High Isolation Resistance from Driver
Fast Switching
Low Noise
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PIN CONFIGURATION
SOT-23
TO-92
D
S
5018
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ABSOLUTE
MAXIMUM RATINGS
(TA = 25oC unless otherwise specified)
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . . . . . . -25V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Storage Temperature Range . . . . . . . . . . . . . -55oC to +150oC
Operating Temperature Range . . . . . . . . . . . -55oC to +135oC
Lead Temperature (Soldering, 10sec) . . . . . . . . . . . . . +300oC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . 3.3mW/ oC
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
G
G
D S
APPLICATIONS
Analog Switches
Choppers
Commutators
Low-Noise Audio Amplifiers
PRODUCT MARKING (SOT-23)
SST108
I08
SST109
I09
SST110
I10
ORDERING INFORMATION
Part
Package
J108-110
Plastic TO-92
XJ108-110
Sorted Chips in Carriers
SST109-110 Plastic SOT-23
Temperature Range
-55oC to +135oC
-55oC to +135oC
-55oC to +135oC
ELECTRICAL CHARACTERISTICS (TA = 25oC unless otherwise specified)
SYMBOL
108
109
110
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
-3
-3
-3
nA
-3
-10
-2
-6
-0.5
-4
V
-25
-25
-25
80
40
10
mA
3
3
3
nA
8
12
18
Ω
15
15
15
PARAMETER
IGSS
VGS(off)
BVGSS
IDSS
ID(off)
rDS(on)
Cdg(off)
Gate Reverse Current (Note 1)
Gate-Source Cutoff Voltage
Gate-Source Breakdown Voltage
Drain Saturation Current (Note 2)
Drain Cutoff Current (Note 1)
Drain-Source ON Resistance
Drain-Gate OFF Capacitance
Csg(off)
Source-Gate OFF Capacitance
Cdg(on)
+ Csg(on)
td(on)
tr
td(off)
Drain-Gate Plus Source-Gate
ON Capacitance
Turn On Delay Time
Rise Time
Turn OFF Delay Time
tf
Fall Time
o
15
15
15
85
85
85
4
1
6
4
1
6
4
1
6
30
30
30
NOTES: 1. Approximately doubles for every 10 C increase in TA.
2. Pulse test duration = 300µs; duty cycle ≤3%.
3. For design reference only, not 100% tested.
pF
ns
TEST CONDITIONS
VDS = 0V, VGS = -15V
VDS = 5V, ID = 1µA
VDS = 0V, IG = -1µA
VDS = 15V, VGS = 0V
VDS = 5V, VGS = -10V
VDS ≤0.1V, VGS = 0V
VDS = 0,
VGS = -10V
(Note 3)
f = 1MHz
VDS = VGS = 0
(Note 3)
Switching Time Test
Conditions (Note 3)
J107
J109
J110
VDD 1.5V
1.5V
1.5V
VGS(off) -12V
-7V
-5V
RL
150Ω 150Ω 150Ω