TI SN74F163AN

SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
Internal Look-Ahead Circuitry for Fast
Counting
Carry Output for N-Bit Cascading
Fully Synchronous Operation for Counting
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
CLR
CLK
A
B
C
D
ENP
GND
description
1
16
2
15
3
14
4
13
5
12
6
11
7
10
VCC
RCO
QA
QB
QC
QD
ENT
LOAD
8
9
This synchronous, presettable, 4-bit binary
counter features an internal carry look-ahead
circuitry for application in high-speed counting
designs. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so
instructed by the count enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that are normally associated with asynchronous (ripple-clock) counters; however,
counting spikes may occur on the ripple carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of the clock input waveform.
This counter is fully programmable; that is, it may be preset to any number between 0 and 15. As presetting is
synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
The clear function for the SN74F163A is synchronous and a low level at the clear (CLR) input sets all four of
the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels of the enable
inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the
maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable (ENP, ENT) inputs and a
ripple-carry (RCO) output. Both ENP and ENT must be high to count, and ENT if fed forward to enable RCO.
RCO thus enabled will produce a high-level pulse while the count is 15 (HHHH). The high-level overflow
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed
regardless of the level of the clock input.
The SN74F163A features a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the setup and hold times.
The SN74F163A is characterized for operation from 0°C to 70°C.
Copyright  1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
logic symbol†
1
CLR
9
LOAD
ENT
ENP
CLK
A
B
C
D
10
7
2
3
4
5
6
state diagram
CTRDIV16
5CT = 0
M1
M2
3CT = 15
0
15
RCO
2
3
4
15
5
14
6
13
7
G3
G4
C5/2,3,4+
1, 5D
1
2
4
8
14
13
12
11
QA
QB
QC
QD
12
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2–2
1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
10
9
8
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
logic diagram (positive logic)
CLR
LOAD
ENT
ENP
1
9
10
7
15
RCO
3R
14
CLK
A
2
3
G2
QA
1, 2T/C3
1, 3D
M1
3R
13
G2
QB
1, 2T/C3
B
4
1, 3D
M1
3R
12
G2
QC
1, 2T/C3
C
5
1, 3D
M1
3R
G2
11
QD
1, 2T/C3
D
6
1, 3D
M1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–3
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
logic symbol, each flip-flop
R
3R
TE
G2
Q1
1, 2T/C3
CLK
D
Q1
Q2
1, 3D
Q2
LOAD
M1
logic diagram, each flip-flop (positive logic)
R
TE
(Toggle
Enable)
Q1
CLK
Q2
D
LOAD
2–4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero
2. Preset to binary twelve
3. Count to thirteen, fourteen, fifteen, zero, one, and two
4. Inhibit
CLR
LOAD
A
Data
Inputs
B
C
D
CLK
ENP
ENT
QA
Data
Outputs
QB
QC
QD
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1.2 V to 7 V
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
IOH
IOL
TA
Operating free-air temperature
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
0.8
V
– 18
mA
High-level output current
–1
mA
Low-level output current
20
mA
70
°C
Input clamp current
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = – 18 mA
IOH = – 1 mA
VCC = 4.75 V,
VCC = 4.5 V,
IOH = – 1 mA
IOL = 20 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
MIN
TYP‡
2.5
3.4
ENT, LOAD
0.3
– 1.2
V
V
0.5
V
0.1
mA
20
µA
– 0.6
VCC = 5.5 V,
VI = 0.5 V
CLR
– 1.2
mA
– 1.2
IOS§
VCC = 5.5 V,
VO = 0
– 60
ICC
VCC = 5.5 V
37
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
2–6
UNIT
2.7
ENP, CLK, A, B, C, D
IIL
MAX
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–150
mA
55
mA
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
fclock
Clock frequency
tw
Pulse duration
CLK high or low (loading)
CLK (counting)
Data before CLK↑
tsu
ENP and ENT before CLK↑
Data after CLK↑
th
Hold time
LOAD and CLR after CLK↑
ENP and ENT after CLK↑
MAX
0
100
MIN
MAX
UNIT
0
90
MHz
5
5
High
4
4
Low
6
7
High or low
LOAD and CLR before CLK↑
Setup time
MIN
5
5
High
11
11.5
Low
8.5
9.5
High
11
11.5
Low
5
5
High or low
2
2
High
2
2
Low
0
0
High or low
0
0
ns
ns
ns
switching characteristics (see Note 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
FROM
(INPUT)
TO
(OUTPUT)
CLK (LOAD high)
Any Q
CLK (LOAD low)
Any Q
CLK
RCO
VCC = 5 V,
CL = 50 pF,
RL = 500 Ω,
TA = 25°C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX†
MIN
TYP
100
120
MAX
MIN
2.7
5.1
7.5
2.7
8.5
2.7
7.1
10
2.7
11
3.2
5.6
8.5
3.2
9.5
3.2
5.6
8.5
3.2
9.5
4.2
9.6
14
4.2
15
4.2
9.6
14
4.2
15
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
90
1.7
4.1
7.5
1.7
ENT
RCO
tPHL
1.7
4.1
7.5
1.7
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.
UNIT
MHz
8.5
8.5
ns
ns
ns
ns
2–7
SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088 – MARCH 1987 – REVISED OCTOBER 1993
2–8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated