IXYS IXDD404SI

PRELIMINARY DATA SHEET
IXDD404PI / 404SI / 404SIA / 404SI-16
4 Amp Dual Low-Side Ultrafast MOSFET Driver
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected
• High Peak Output Current: 4A Peak
• Wide Operating Range: 4.5V to 25V
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two identical drivers in single chip
The IXDD404 is comprised of two 4 Amp CMOS high speed
MOSFET drivers. Each output can source and sink 4 A of
peak current while producing voltage rise and fall times of less
than 15ns to drive the latest IXYS MOSFETS & IGBT's. The
input of the driver is compatible with TTL or CMOS and is fully
immune to latch up over the entire operating range. Designed
with small internal delays, cross conduction/current shootthrough is virtually eliminated in the IXDD404. Improved speed
and drive capabilities are further enhanced by very low,
matched rise and fall times.
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Limiting di/dt under Short Circuit
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Additionally, each driver in the IXDD404 incorporates a unique
ability to disable the output under fault conditions. When a
logical low is forced into the Enable input of a driver, both of it's
final output stage MOSFETs (NMOS and PMOS) are turned
off. As a result, the respective output of the IXDD404 enters a
tristate mode and achieves a Soft Turn-Off of the MOSFET/
IGBT when a short circuit is detected. This helps prevent
damage that could occur to the MOSFET/IGBT if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
The IXDD404 is available in the standard 8 pin P-DIP (PI),
SOP-8 (SI -with metal tab), SOP-8 (SIA -without metal tab) and
SOP-16 (SI-16) packages.
Figure 1 - Functional Diagram
Vcc
200k
OUTA
200k
OUTB
ENA
INB
ENB
GND
Copyright © IXYS CORPORATION 2001
First Release
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Absolute Maximum Ratings (Note 1)
Parameter
Supply Voltage
All Other Pins
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
Operating Ratings
Parameter
Operating Temperature Range
Value
25 V
-0.3 V to VCC + 0.3 V
150 oC
Value
-40 oC to 85 oC
Thermal Impedance (To Ambient)
8 Pin PDIP (PI) (θ JA)
8 Pin SOIC (SI) (θ JA)
-65 oC to 150 oC
300 oC
8 Pin SOIC (SIA) (θ JA)
16 Pin SOIC (SI-16) (θJA)
120 oC/W
110 oC/W
120 oC/W
110 oC/W
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXDD404 configured as described in Test Conditions. All specifications are for one channel.
Symbol
Parameter
VIH
High input voltage
VIL
Low input voltage
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
ROH
Output resistance
@ Output high
Output resistance
@ Output Low
Peak output current
ROL
IPEAK
IDC
Test Conditions
Min
Typ
Max
3.5
0V ≤ VIN ≤ VCC
Units
V
0.8
V
-5
VCC + 0.3
V
-10
10
µA
V CC - 0.025
V
0.025
V
IOUT = 10mA, VCC = 18V
1.5
3
Ω
IOUT = 10mA, VCC = 18V
1.5
3
Ω
VCC is 18V
4
VEN
Continuous output
current
Enable voltage range
- 0.3
VENH
High En Input Voltage
2/3 Vcc
VENL
Low En Input Voltage
A
1
A
Vcc + 0.3
V
V
1/3 Vcc
V
tR
Rise time
CL=1800pF Vcc=18V
11
12
15
ns
tF
Fall time
CL=1800pF Vcc=18V
12
14
17
ns
tONDLY
CL=1800pF Vcc=18V
33
34
38
ns
CL=1800pF Vcc=18V
28
30
35
ns
30
ns
30
ns
VCC
On-time propagation
delay
Off-time propagation
delay
Enable to output high
delay time
Disable to output low
Disable delay time
Power supply voltage
ICC
Power supply current
VIN = 3.5V
VIN = 0V
VIN = + V CC
REN
Enable Pull-up Resistor
tOFFDLY
tENOH
tDOLD
4.5
18
25
V
1
0
3
10
10
mA
µA
µA
kΩ
200
2
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Pin Configurations
1 EN A
SO8 (SI, SIA)
8 PIN DIP (PI)
2 IN A
3 GND
4 IN B
I
X
D
D
4
0
4
EN B 8
OUT A 7
SO16 (SI-16)
VCC 6
OUT B 5
Pin Description
SYMBOL
FUNCTION
EN A
A Channel Enable
IN A
A Channel Input
GND
Ground
IN B
B Channel Input
OUT B
B Channel Output
VCC
Supply Voltage
OUT A
A Channel Output
EN B
B Channel Enable
DESCRIPTION
The Channel A enable pin. This pin, when driven low, disables the A
Channel, forcing a high impedance state to the A Channel Output.
A Channel Input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry, this pin provides
ground reference for the entire chip. This pin should be connected to a low
noise analog ground plane for optimum performance.
B Channel Input signal-TTL or CMOS compatible.
B Channel Driver output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
Positive power-supply voltage input. This pin provides power to the entire
chip. The range for this voltage is from 4.5V to 25V.
A Channel Driver output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The Channel B enable pin. This pin, when driven low, disables the B
Channel, forcing a high impedance state to the B Channel Output.
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.
Figure 2 - Characteristics Test Diagram
VIN
3
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Typical Performance Characteristics
Rise Time vs. Supply Voltage
Fig. 3
Fall Time vs. Supply Voltage
Fig. 4
60
40
35
50
30
Fall Time (ns)
40
25
Rise Time (ns)
CL=4700 pF
20
15
1800 pF
30
CL=4700 pF
20
1800 pF
10
0
10
200 pF
5
8
10
12
14
16
0
18
200 pF
8
10
12
Supply Voltage (V)
Fig. 5
14
16
18
Supply Voltage (V)
Rise And Fall Times vs. Temperature
CL=18V VCC=18V
Rise Time vs. Load Capacitance
Fig. 6
80
25
70
8V
60
15
Rise Time (ns)
Time (ns)
20
tF
10
tR
10V
50
12V
40
18V
30
14V 16V
20
5
10
0
-40
-20
0
20
40
60
80
100
0
0k
120
Temperature (°C)
Fig. 7
2k
100
6k
8k
10k
Max / Min Input vs. Temperature
VCC=18V CL=1nF
Fig. 8
Fall Time vs. Load Capacitance
4k
Load Capacitance (pF)
3.2
8V
90
3.0
80
Minimum Input High
2.8
Max / Min Input (V)
Fall Time (ns)
70
10V
60
12V
50
40
18V
30
14V 16V
20
2.6
2.4
2.2
Maximum Input Low
2.0
1.8
10
0
0k
2k
4k
6k
Load Capacitance (pF)
8k
1.6
-60
10k
-40
-20
0
20
40
Temperature (oC)
4
60
80
100
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Fig. 9
100
Supply Current vs. Load Capacitance
Vcc=18V
Fig. 10
100
Supply Current vs. Frequency
Vcc=18V
CL= 1800 pF
80
60
2 MHz
1 MHz
500 KHz
40
100 kHz
20
1000 pF
Supply Current (mA)
Supply Current (mA)
10
200 pF
1
0.1
50 kHz
10 kHz
0
0.1k
0.01
1.0k
10.0k
1
10
Fig. 11
100
Supply Current vs. Load Capacitance
Vcc=12V
Fig. 12
100
Supply Current (mA)
Supply Current (mA)
60
1 MHz
1000
Supply Current vs. Frequency
Vcc=12V
80
2 MHz
100
Frequency (kHz)
Load Capacitance (pF)
500 KHz
40
10
CL= 1800 pF
1
200 pF
1000 pF
0.1
20
100 kHz
0
0.1k
50 kHz
10 kHz
1.0k
0.01
10.0k
1
10
Fig. 13
100
100
1000
Frequency (kHz)
Load Capacitance (pF)
Supply Current vs. Load Capacitance
Vcc=8V
Fig. 14
100
Supply Current vs. Frequency
Vcc=8V
80
Supply Current (mA)
Supply Current (mA)
10
60
40
2 MHz
1 MHz
20
0
0.1k
500 KHz
CL= 1800 pF
1000 pF
1
200 pF
0.1
100 kHz
50 kHz
10 kHz
0.01
1.0k
10.0k
Load Capacitance (pF)
1
10
100
Frequency (kHz)
5
1000
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Fig. 15
50
60
50
tONDLY
Propagation Delay (ns)
Propagation Delay (ns)
40
30
tOFFDLY
20
10
0
Propagation Delay vs. Input Voltage
CL=1800pF VCC=15V
Fig. 16
Propagation Delay vs. Supply Voltage
CL=1800pF [email protected]
tONDLY
40
30
tOFFDLY
20
10
0
8
10
12
14
16
18
0
2
4
Fig. 17
6
8
10
12
Input Voltage (V)
Supply Voltage (V)
Fig. 18
Propagation Delay Times vs. Temperature
CL=1800pF VCC=18V
Quiescent Supply Current vs. Temperature
VCC=18V [email protected] CL=1000pF
0.26
60
55
0.24
tONDLY
45
Time (ns)
Quiescent Vcc Input Current (mA)
50
40
tOFFDLY
35
30
25
20
15
0.22
0.20
0.18
0.16
0.14
10
-40
-20
0
20
40
60
80
100
120
-40
-20
Fig. 20
60
80
N Channel Output Current Vs. Temperature
VCC=18V, CL=1000pF
6
N Channel Output Current (A)
6
P Channel Output Current (A)
40
Temperature ( C)
P Channel Output Current Vs. Temperature
VCC=18V, CL=1000pF
5
4
3
20
o
Temperature (°C)
Fig. 19
0
-40
-20
0
20
40
60
80
5
4
3
100
o
-40
-20
0
20
40
o
Temperature ( C)
Temperature ( C)
6
60
80
100
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Fig. 21
High State Output Resistance
vs. Supply Voltage
Fig. 22
Enable Threshold vs. Supply Voltage
5
14
High State Output Resistance (Ohm)
12
Enable Threshold (V)
10
8
6
4
2
0
4
3
2
1
0
8
10
12
14
16
18
20
22
24
26
10
8
Supply Voltage (V)
Low-State Output Resistance
Vs. Supply Voltage
Fig. 23
15
20
25
Supply Voltage (V)
Vcc vs. P Channel Output Current
Fig. 24
3.0
Low-State Output Resistance (Ohms)
0
P Channel Output Current (A)
-2
2.0
-4
1.0
-6
0.0
8
10
15
20
-8
25
Supply Voltage (V)
N Channel Output Current (A)
6
4
2
8
10
15
20
15
20
25
Figure 26 - Typical Application Short Circuit di/dt Limit
8
0
10
Vcc
VCC vs. N Channel Output Current
Fig. 25
8
25
30
Vcc
7
30
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET such as the IXFN100N20,
(20A, 1000V), as shown in Figure 26, can cause the current
through the module to flow in excess of 60A for 10µs or more
prior to self-destruction due to thermal runaway. For this
reason, some protection circuitry is needed to turn off the
MOSFET module. However, if the module is switched off too
fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche breakdown.
caused by the inductance of the wire connecting the source
resistor to ground. (Those glitches might cause false triggering
of the comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the IXFN100N20 gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the IXFN100N20.
The IXDD404 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
Thus, the IXDD404 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD404 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD408 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD404 input, and this
pulse will reset the SRFF outputs to normal operation.
The IXDD404 is designed to not only provide ±4A per output
under normal conditions, but also to allow it's outputs to go into
a high impedance state. This permits the IXDD404 output to
control a separate weak pull-down circuit during detected
overcurrent shutdown conditions to limit and separately control dVGS/dt gate turnoff. This circuit is shown in Figure 27.
When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD404 output. The
SRFF also turns on the low power MOSFET, (2N7000).
Referring to Figure 27, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the IXFD100N20. A low pass filter should be added to the
input of the comparator to eliminate any glitches in voltage
In this way, the high-power MOSFET module is softly turned off
by the IXDD404, preventing its destruction.
Figure 27 - Application Test Diagram
+
Ld
10uH
VCC
VCCA
Rg
OUT
IN
EN
VCC
+
-
VIN
High_Power
IXFN100N20
1ohm
Rsh
1600ohm
DGND
SUB
Rs
Low_Power
2N7002/PLP
Ls
R+
10kohm
One ShotCircuit
Rcomp
5kohm
NAND
CD4011A
NOT1
CD4049A
NOT2
CD4049A
Ccomp
1pF
Ros
Cos
1pF
V+
V-
+
C+
100pF
+
REF
Q
NOT3
CD4049A
NOR1
CD4001A
EN
NOR2
CD4001A
SR Flip-Flop
8
S
20nH
0
Comp
LM339
R
1Mohm
VB
Rd
0.1ohm
IXDD404
+
-
-
-
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Supply Bypassing and Grounding Practices,
Output Lead inductance
TTL to High Voltage CMOS Level Translation
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD404, it is very important to keep certain design
criteria in mind, in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
The enable (EN) input to the IXDD404 is a high voltage
CMOS logic level input where the EN input threshold is ½
VCC, and may not be compatible with 5V CMOS or TTL input
levels. The IXDD404 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, VCC =15V
and the EN input threshold at 7.5V, a 5V CMOS logical high
input applied to this typical IXDD404 application’s EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.
Say, for example, we are using the IXDD404 to charge a 2500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=2500pF &
∆t=25ns we can determine that to charge 2500pF to 25 volts in
25ns will take a constant current of 2.5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
4A).
The circuit in Figure 28 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD404 EN input. From the figure, VCC is the gate driver
power supply, typically set between 8V to 20V, and VDD is the
logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so that
the Q1 base is positioned at the midpoint of the expected
TTL logic transition levels.
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD404
must be able to draw this 2.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD404
to an absolute minimum.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied
to the Q1 emitter will drive it on. This causes the level
translator output, the Q1 collector output to settle to VCESATQ1
+ VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V
for VCC =15V given in the IXDD404 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 28 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage
CMOS logical EN output applied to the IXDD404 EN input
will enable it, allowing the gate driver to fully function as a
±4 Amp output driver.
GROUNDING
In order for the design to turn the load off properly, the IXDD404
must be able to drain this 2.5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD404
and it’s load. Path #2 is between the IXDD404 and it’s power
supply. Path #3 is between the IXDD404 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD404.
The total component cost of the circuit in Figure 28 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Figure 28 - TTL to High Voltage CMOS Level Translator
CC
(From Gate Driver
Power Supply)
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
VDD
(From Logic
Power Supply)
10K
3.3K
or TTLInput)
9
R1
Q1
2N3904
3.3K
driver, and connect directly to the ground terminal of the
load.
R3
R2
High Voltage
CMOS EN
Output
(To IXDD404
EN Input)
PRELIMINARY DATA SHEET
IXDD404PI/404SI/404SIA/404SI-16
Ordering Information
P a rt N u m b er
IX D D 4 0 4 P I
IX D D 4 0 4 S I
IX D D 4 0 4 S IA
IX D D 4 0 4 S I-1 6
P a ck ag e T yp e
8 -P in P D IP
8 -P in S O IC
8 -P in S O IC
1 6 -P in S O IC
Tem p
-4 0 ° C
-4 0 ° C
-4 0 ° C
-4 0 ° C
. R
to
to
to
to
an ge
+ 8 5 °C
+ 8 5 °C
+ 8 5 °C
+ 8 5 °C
NOTE: Mounting or solder tabs on all
packages are connected to ground
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526
Tel: 970-493-1901; Fax: 970-493-1903
e-mail: [email protected]
10
Doc #9200-0226 R4