IXYS IXDD415SI

IXDD415SI
Dual 15 Ampere Low-Side Ultrafast MOSFET Driver
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected
• High Peak Output Current: Dual 15A Peak
• Wide Operating Range: 8V to 30V
• Rise And Fall Times of <3ns
• Minimum Pulse Width Of 6ns
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 4nF in <5ns
• Matched Rise And Fall Times
• 32ns Input To Output Delay Time
• Low Output Impedance
• Low Supply Current
The IXDD415 is a dual CMOS high speed high current gate
driver specifically designed to drive MOSFETs in Class D and E
HF RF applications, as well as other applications requiring
ultrafast rise and fall times or short minimum pulse widths.
Each output of the IXDD415 can source and sink 15A of peak
current while producing voltage rise and fall times of less than
3ns. The outputs of the IXDD415 may be paralleled, producing a
single output of up to 30A with comparable rise and fall times.
The input of the driver is compatible with TTL or CMOS and is
fully immune to latch up over the entire operating range.
Designed with small internal delays, cross conduction/current
shoot-through is virtually eliminated in the IXDD415. Its features
and wide safety margin in operating voltage and power make
the IXDD415 unmatched in performance and value.
Applications
The IXDD415 has two enable inputs, ENA and ENB. These
enable inputs can be used to independently disable either of the
outputs, OUTA or OUTB, for added flexibility. Additionally, the
IXDD415 incorporates a unique ability to disable the output
under fault conditions. When a logical low is forced into the
Enable inputs, both final output stage MOSFETs (NMOS and
PMOS) are turned off. As a result, the output of the IXDD415
enters a tristate mode and achieves a Soft Turn-Off of the
MOSFET when a short circuit is detected. This helps prevent
damage that could occur to the MOSFET if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
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Driving RF MOSFETs
Class D or E Switching Amplifier Drivers
Multi MHz Switch Mode Power Supplies (SMPS)
Pulse Generators
Acoustic Transducer Drivers
Pulsed Laser Diode Drivers
DC to DC Converters
Pulse Transformer Driver
The IXDD415 is available in a 28 pin SO package (IXDD415SI),
incorporating DEI's patented (1) RF layout techniques to minimize
stray lead inductances for optimum switching performance.
(1)
DEI U.S. Patent #4,891,686
Figure 1 - Functional Diagram
Vcc (3, 4)
Vcc (1, 2)
INA (7)
OUTA (22, 23, 24)
200k
ENA (6)
GND (25, 26)
GND (27, 28)
Vcc (11, 12)
Vcc (13, 14)
INB (8)
OUTB (19, 20, 21)
200k
ENB (9)
GND (15, 16)
Copyright © IXYS CORPORATION 2001
GND (17, 18)
Patent Pending
First Release
IXDD415SI
Absolute Maximum Ratings (Note 1)
Parameter
Supply Voltage
All Other Pins
Value
30V
-0.3V to VCC + 0.3V
Power Dissipation
TAMBIENT ≤25 oC
TCASE ≤25 oC
1W
Operating Ratings
Parameter
Maximum Junction Temperature
Operating Temperature Range
-40oC to 85oC
Thermal Impedance (Junction To Case)
28 Pin SOIC (SI) (θJC)
0.75oC/W
12W
Derating Factors (to Ambient)
28-Pin SOIC
Storage Temperature
Soldering Lead Temperature
(10 seconds maximum)
Value
150oC
0.1W/oC
-65oC to 150oC
300oC
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXDD415 configured as described in Test Conditions.
S ym b o l
P a r a m e te r
V IH
H ig h in p u t v o lta g e
V IL
L o w in p u t v o lta g e
V IN
In p u t v o lta g e ra n g e
I IN
In p u t c u rre n t
V OH
H ig h o u tp u t vo lta g e
V OL
L o w o u tp u t v o lta g e
R OH
O u tp u t re s is ta n c e
@ O u tp u t H ig h
O u tp u t re s is ta n c e
@ O u tp u t L o w
P e a k o u tp u t c u rre n t
R OL
IP EA K
ID C
T e s t C o n d itio n s
M in
M ax
U n its
0 .8
V
-5
V C C + 0 .3
V
0 V ≤ V IN ≤ V C C
-1 0
10
µA
0 .0 2 5
V
0 .8
1 .2
Ω
IO U T = 1 0 m A , V C C = 1 5 V
0 .8
1 .2
Ω
V C C = 1 5 V , e a c h o u tp u t
15
-0 .3
V ENH
H ig h E n in p u t v o lta g e
2 /3 V c c
V ENL
L o w E n in p u t v o lta g e
fM AX
M a x im u m fre q u e n c y
tR
R is e tim e
tF
F a ll tim e
tO N D L Y
O n -tim e p ro p a g a tio n
(1 )
d e la y
O ff-tim e p ro p a g a tio n
d e la y (1 )
M in im u m p u ls e w id th
tO FF D L Y
P W m in
tE N O L
V CC
E n a b le to o u tp u t lo w
d e la y tim e
E n a b le to o u tp u t h ig h
d e la y tim e
D is a b le to o u tp u t lo w
D is a b le d e la y tim e
D is a b le to o u tp u t h ig h
D is a b le d e la y tim e
P o w e r s u p p ly v o lta g e
IC C
P o w e r s u p p ly c u rre n t
tE N O H
tD O LD
tD O H D
V
IO U T = 1 0 m A , V C C = 1 5 V
V EN
(1 )
V
V C C - 0 .0 2 5
C o n tin u o u s o u tp u t
c u rre n t
E n a b le v o lta g e ra n g e
(1 )
T yp
3 .5
A
2
A
V c c + 0 .3
V
1 /3 V c c
V
45
MHz
V
C L = 1 .0 n F V c c = 1 5 V , m a x C W fre q u e n c y
lim ite d b y p a c k a g e p o w e r d is s ip a tio n
C L = 1 n F V c c = 1 5 V V O H = 2 V to 1 2 V
C L = 4 n F V c c = 1 5 V V O H = 2 V to 1 2 V
C L = 1 n F V c c = 1 5 V V O H = 2 V to 1 2 V
C L = 4 n F V c c = 1 5 V V O H = 2 V to 1 2 V
C L= 4 n F V c c = 1 5 V
2 .5
4 .5
2 .0
3 .5
32
38
ns
ns
ns
ns
ns
C L= 4 n F V c c = 1 5 V
29
35
ns
F W H M C L= 1 n F
+ 3 V to + 3 V C L = 1 n F
V cc=15V
5 .0
7 .0
80
ns
ns
ns
V cc=15V
170
ns
V cc=15V
30
ns
V cc=15V
30
ns
8
V IN = 3 .5 V
V IN = 0 V
V IN = + V C C
(1) Refer to Figures 2a and 2b
Specifications Subject To Change Without Notice
2
15
30
V
1
0
3
10
10
mA
µA
µA
IXDD415SI
Pin Configurations And Package Outline
NOTE: Bottom-side heat sinking metalization is connected to ground
Pin Description
P IN #
SYM BOL
F U N C T IO N
1 -4
1 1 -1 4
VCC
S u p p ly V o lta g e
7
IN A
In p u t
6
ENA
E n a b le
2 2 -2 4
OUTA
8
IN B
In p u t
9
ENB
E n a b le
1 9 -2 1
OUTB
O u tp u t
5 ,1 0
1 5 -1 8
2 5 -2 8
GND
G ro u n d
O u tp u t
D E S C R IP T IO N
P o s itiv e p o w e r-s u p p ly v o lta g e in p u t. T h is p in p ro v id e s p o w e r
to th e e n tire c h ip . T h e ra n g e fo r th is v o lta g e is fro m 8 V to
30V.
In p u t s ig n a l-T T L o r C M O S c o m p a tib le .
T h e s y s te m e n a b le p in . T h is p in , w h e n d r iv e n lo w , d is a b le s
th e c h ip , fo rc in g h ig h im p e d a n c e s ta te to th e o u tp u t.
D riv e r O u tp u t. F o r a p p lic a tio n p u rp o s e s , th is p in is
c o n n e c te d to th e G a te o f a M O S F E T . In s o m e a p p lic a tio n s ,
a lo w -im p e d a n c e s e rie s re s is to r m a y b e r e q u ire d b e tw e e n
th is o u tp u t a n d th e M O S F E T G a te .
In p u t s ig n a l-T T L o r C M O S c o m p a tib le .
T h e s y s te m e n a b le p in . T h is p in , w h e n d r iv e n lo w , d is a b le s
th e c h ip , fo rc in g h ig h im p e d a n c e s ta te to th e o u tp u t.
D riv e r O u tp u t. F o r a p p lic a tio n p u rp o s e s , th is p in is
c o n n e c te d to th e G a te o f a M O S F E T . In s o m e a p p lic a tio n s ,
a lo w -im p e d a n c e s e rie s re s is to r m a y b e r e q u ire d b e tw e e n
th is o u tp u t a n d th e M O S F E T G a te .
T h e s y s te m g ro u n d p in s . In te rn a lly c o n n e c te d to a ll c ir c u itr y ,
th e s e p in s p ro v id e g ro u n d r e fe re n c e fo r th e e n tire c h ip . A ll o f
th e s e p in s s h o u ld b e c o n n e c te d to a lo w n o is e a n a lo g
g ro u n d p la n e fo r o p tim u m p e rfo rm a n c e .
Note 1: Operating the device beyond parameters with listed “Absolute Maximum Ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.
Ordering Information
Part Number
IXDD415SI
Package Type
28-Pin SOIC
Temp. Range
-40°C to +85°C
3
Grade
Industrial
IXDD415SI
Typical Performance Characteristics
Figure 2a - Characteristics Test Diagram
Figure 2b - Timing Diagram
5V
90%
INPUT 2.5V
10%
0V
PWMIN
VIN
tOFFDLY
tR
tONDLY
tF
Vcc
90%
OUTPUT
10%
0V
Rise Time vs. Load Capacitance
VCC = 15V, VOH = 2V To 12V
Fig. 4
5
5
4
4
3
3
Fall Time (ns)
Rise Time (ns)
Fig. 3
2
1
Fall Time vs. Load Capacitance
VCC = 15V, VOH = 12V To 2V
2
1
0
0
1k
2k
3k
0
4k
0
1k
Load Capacitance (pF)
Supply Current vs. Frequency
Vcc=15V
Fig. 5
4000
2k
3k
4k
Load Capacitance (pF)
Supply Current vs. Load Capacitance
Vcc=15V
Fig. 6
4000
4 nF
3000
2 nF
1 nF
Supply Current (mA)
Supply Current (mA)
3000
CL = 0
2000
1000
25 MHz
2000 20 MHz
15 MHz
1000
10 MHz
5 MHz
1 MHz
0
0k
0
5
10
15
20
25
Frequency (MHz)
1k
2k
Load Capacitance (pF)
4
3k
4k
IXDD415SI
Fig. 7
Propagation Delay vs. Supply Voltage
CL=4nF [email protected]
50
Propagation Delay vs. Input Voltage
CL=4nF VCC=15V
Fig. 8
50
tONDLY
40
40
Propagation Delay (ns)
Propagation Delay (ns)
tONDLY
30
30
tOFFDLY
20
tOFFDLY
20
10
10
0
8
10
12
14
16
0
18
2
Supply Voltage (V)
Fig. 9
4
6
8
10
12
Input Voltage (V)
Propagation Delay vs. Junction Temperature
CL=4nF, VCC=15V
50
Time (ns)
45
40
tONDLY
35
tOFFDLY
30
25
20
15
10
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Typical Output Waveforms
Unless otherwise noted, all waveforms are taken driving a 1nF load, 1MHz repetition frequency, VCC=15V, Case Temperature = 25°C
Figure 10
2.2ns Rise Time
Figure 11
5
<6ns Minimum Pulse Width
IXDD415SI
Figure 12 500KHz CW Repetition Frequency
Figure 13 50MHz Burst Repetition Frequency
Figure 14 - High Frequency Gate Drive Circuit
6
IXDD415SI
APPLICATIONS INFORMATION
High Frequency Gate Drive Circuit
returning current that need to be considered: Path #1 is
between the IXDD415 and its load. Path #2 is between the
IXDD415 and its power supply. Path #3 is between the
IXDD415 and whatever logic is driving it. All three of these
paths should be as low in resistance and inductance as
possible, and thus as short as practical.
The circuit diagram in figure 14 is a circuit diagram for a
very high switching speed, high frequency gate driver
circuit using the IXDD415SI. This is the circuit used in
the EVDD415 Evaluation Board,and is capable of driving
a MOSFET at up to the maximum operating limits of the
IXDD415. The circuit's very high switching speed and
high frequency operation dictates the close attention to
several important issues with respect to circuit design.
The three key elements are circuit loop inductance, Vcc
bypassing and grounding.
Output Lead Inductance
Of equal importance to supply bypassing and grounding are
issues related to the output lead inductance. Every effort
should be made to keep the leads between the driver and
its load as short and wide as possible, and treated as
coplanar transmission lines.
Circuit Loop Inductance
Referring to Figure 14, the Vcc to Vcc ground current
path defines the loop which will generate the inductive
term. This loop must be kept as short as possible. The
output leads (pins 24, 23, 22, 21, 20, and 19) must be
no further than 0.375 inches (9.5mm) from the gate of
the MOSFET. Furthermore the output ground leads (pins
25, 26, 27 and 28 on one end of the IC and pins 15, 16,
17, and 18 on the other end of the IC) must provide a
balanced symmetric coplanar ground return for optimum
operation.
In configurations where the optimum configuration of circuit
layout and bypassing cannot be used, a series resistance
of a few Ohms in the gate lead may be necessary to prevent
ringing.
Heat Sinking
For high power operation, the bottom side metalized heat
sink pad should be epoxied to the circuit board ground
plane, or attached to an appropriate heat sink, using
thermally conductive epoxy. The heat sink tab is connected
to ground.
Vcc Bypassing
In order for the circuit to turn the MOSFET on properly,
the IXDD415 must be able to draw up to 15A of current
per output channel from the Vcc power supply in 2-6ns
(depending upon the input capacitance of the MOSFET
being driven). This means that there must be very low
impedance between the driver and the power supply.
The most common method of achieving this low
impedance is to bypass the power supply at the driver
with a capacitance value that is at least two orders of
magnitude larger than the load capacitance. Usually,
this is achieved by placing two or three different types of
bypassing capacitors, with complementary impedance
curves, very close to the driver itself. (These capacitors
should be carefully selected, low inductance, low
resistance, high-pulse current-service capacitors). Care
should be taken to keep the lengths of the leads
between these bypass capacitors and the IXDD415 to an
absolute minimum.
Figure 15: IXDD415SI Bottom Side
Heat Sinking Metalization
The bypassing should be comprised of several values of
chip capacitors symmetrically placed on ether side of
the IC. Recommended values are .01uF, .47uF chips
and at least two 4.7uF tantalums.
Grounding
In order for the design to turn the load off properly, the
IXDD415 must be able to drain this 15A of current into an
adequate grounding system. There are three paths for
7
IXDD415SI
TTL to High Voltage CMOS Level Translation
The enable (EN) input to the IXDD415 is a high voltage
CMOS logic level input where the EN input threshold is ½ VCC,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD415 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, VCC =15V and the
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD415 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.
Figure 16 - TTL to High Voltage CMOS Level Translator
CC
(From Gate Driver
Power Supply)
VDD
(From Logic
Power Supply)
10K
3.3K
R1
Q1
2N3904
3.3K
The circuit in Figure 16 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD415 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition
levels.
R3
High Voltage
CMOS EN
Output
(To IXDD415
EN Input)
R2
or TTL Input)
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to
the Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1 +
VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD415 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 16 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD415 EN input will enable
it, allowing the gate driver to fully function as a 15 Ampere
output driver.
The total component cost of the circuit in Figure 16 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526
Tel: 970-493-1901; Fax: 970-493-1903
e-mail: [email protected]
www.directedenergy.com
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
www.ixys.com
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
8
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