DATA SHEET COMPOUND TRANSISTOR µPA103 HIGH FREQUENCY NPN TRANSISTOR ARRAY FEATURES • FIVE MONOLITHIC 9 GHz fT TRANSISTORS: Two of these use a common emitter pin and can be used as differential amplifiers • OUTSTANDING hFE LINEARITY • TWO PACKAGE OPTIONS: µPA103B: Superior thermal dissipation due to studded ceramic package µPA103G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting DESCRIPTION AND APPLICATIONS The µPA103 is a user configurable Silicon bipolar transistor array consisting of a common emitter pair and three individual bipolar transistors. It is available in a surface mount 14-pin plastic SOP package and a 14-pin ceramic package. Typical applications include: differential amplifiers and oscillators, high speed comparators, advanced cellular phone systems, electro-optic and other signal processing up to 1.5 gigabits/second. ORDERING INFORMATION PART NUMBER PACKAGE µPA103B-E1 14-pin ceramic package µPA103G-E1 14-pin plastic SOP (225 mil) ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) SYMBOLS PARAMETERS UNITS RATINGS VCBO* Collector to Base Voltage V 15 VCEO* Collector to Emitter Voltage V 6 VEBO* Emitter to Base Voltage V 2.5 IC * Collector Current mA 40 PT Power Dissipation µPA103B µPA103G mW mW 650 350 Junction Temperature µPA103B µPA103G °C °C 200 125 Storage Temperature µPA103B µPA103G °C °C –55 to +200 –55 to +125 TJ TSTG * Absolute maximum ratings for each transistor. Caution electro-static sensitive devices The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10708EJ2V0DS00 (2nd edition) Date Published October 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1995, 1999 µPA103 PACKAGE DIMENSIONS (UNIT: mm) µPA103B 14 PIN CERAMIC PACKAGE φ 0.8 TOP VIEW 0.35 6.2 1.27 5.0 MAX. 4.5 MIN. 2. 7 SIDE VIEW MAX. 0.08 2.3 MIN. φ 1.6 BOTTOM VIEW 1.8 3.0 µPA103G 14 PIN PLASTIC SOP (225 mil) 14 8 detail of lead end +7° 3° –3° 1 7 10.2 ± 0.26 6.55 ± 0.2 4.38 ± 0.1 1.49 1.1 ± 0.16 0.6 ± 0.2 1.42 MAX 1.27 0.40 +0.10 –0.05 +0.10 0.15 –0.05 0.10 0.10 M 0.1 ± 0.1 1.59 +0.21 –0.20 NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. See connection diagram for description of leads. 2 Data Sheet P10708EJ2V0DS00 µPA103 ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 ˚C µPA103B, µPA103G common) SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN. TYP. MAX. ICBO Collector Cutoff Current at VCB = 5 V, IE = 0 (Q1 to Q5) µA 1.0 IEBO Emitter Cutoff Current at VEB = 1 V, IC = 0 (Q1 to Q5) µA 1.0 hFE Direct Current Amplification at VCE = 3 V, IC = 5 mA (Q1 to Q5) 40 100 250 hFE1/hFE2 Direct Current Amplification Ratio at VCE = 3 V, IC = 5 mA, (Q1, Q2) 0.9 1.0 1.1 V 0.8 1.0 VBE Emitter to Base Voltage at VCE = 3 V, IC = 5 mA (Q1, Q2) ∆VBE Emitter to Base Voltage Difference, VCE = 3 V, IC = 5 mA |Q1 - Q2| mV 8.0 20 CCB Collector to Base Capacitance at VCB = 3 V, f = 1 MHz (Q1 to Q5) pF 0.9 1.8 CEB Emitter to Base Capacitance at VEB = 0, f = 1 MHz (Q1 to Q4) pF 1.4 2.8 CCS Collector/Substrate Capacitance at VCS = 3 V, f = 1 MHz (Q1 to Q4) pF 1.4 2.8 GHz 9.0 fT Gain Bandwidth Product* at VCE = 3 V, IC = 10 mA * Measured by installing a single transistor in a Micro-X package: the value shown is a reference value. CONNECTION DIAGRAM (Top View) µPA103B 14 13 12 11 10 9 8 SUB Q4 Q5 2 1 Q3 Q2 Q1 3 4 5 6 7 µPA103G 14 13 12 11 10 9 8 SUB Q4 Q5 Q1 1 2 Q3 Q2 3 4 5 6 Data Sheet P10708EJ2V0DS00 7 3 µPA103 TYPICAL PERFORMANCE CHARACTERISTICS (TA = +25 °C) COLLECTOR CURRENT vs. BASE TO EMITTER VOLTAGE COLLECTOR CURRENT vs. COLLECTOR TO EMITTER VOLTAGE 10 200 100 8 Collector Current, IC (mA) Collector Current, IC (mA) 100 80 60 6 40 4 IB = 20 µ A 2 50 20 10 5 2 1 0.5 VCE = 3 V 0 0 0.1 1 2 3 4 5 Collector to Emitter Voltage, VCE (V) DC CURRENT GAIN vs. COLLECTOR CURRENT GAIN BANDWIDTH PRODUCT vs. COLLECTOR CURRENT 12 Gain Bandwidth Product, fT (GHz) 1000 DC Current Gain, hFE 500 200 100 50 20 10 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Base to Emitter Voltage, VBE (V) 0.5 1 2 5 10 20 Collector Current, IC (mA) 50 VCE = 5 V 10 8 3V 6 1V 4 1 2 5 10 20 Collector Current, IC (mA) GAIN AND NOISE FIGURE OF INDIVIDUAL TRANSISTOR 20 8 Gain (dB) GAIN 6 10 4 NF 0 4 1 2 5 10 20 50 100 Collector Current, IC (mA) Data Sheet P10708EJ2V0DS00 2 0 Noise Figure, NF (dB) VCC = 3 V f = 1 GHz 50 µPA103 TYPICAL HIGH SPEED COMPARATOR R1 ANALOG INPUT R2 Q1 REFERENCE R3 R4 R5 R6 Q2 Q7 Q8 Q5 Q3 Q6 Q4 Q9 Q10 OUTPUT LATCH LATCH µ µ µ Q11 µ FEATURES: 1. High Sensitivity µ 2. Low Positive Feedback time 3. Optimized latch recovery time Q12 µ TYPICAL DIFFERENTIAL OSCILLATOR VCC VCC C1 R2 C2 VOUT Q2 Q1 RFC 4 BIAS BENEFITS: 1. Ease of Integration 2. Very Low Distortion 3. Automatic Gain Control 4. Minimum Loading on Tank Circuit 5. Very Low 1/f Noise AC SHORT TYPICAL COMMON MODE DIFFERENTIAL AMP VCC (10 V) 100 Ω 100 pF OUT IN 1 KΩ VBB1 (5 V) VBB2 1 KΩ 1 KΩ 160 Ω 1000 pF FEATURES: 1. High Gain 2. Stable 3. Auto Gain Control The application circuits and their parameters are for references only and are not intended for use in actual design-in's. Data Sheet P10708EJ2V0DS00 5 µPA103 NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as wide as possible to minimize ground impedance (to prevent undesired operation). (3) Design circuits connected Sub pin to the lowest voltage to prevent latch-up. (4) Design circuits as each pin voltage difference within 15 V maximum. RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. µPA103G Soldering process Soldering conditions Recommended condition symbol Infrared ray reflow Package peak temperature: 235 °C, Hour: within 30 s. (more than 210 °C), Time: 2 times, Limited days: no.Note IR35-00-2 VPS Package peak temperature: 215 °C, Hour: within 40 s. (more than 200 °C), Time: 2 times, Limited days: no.Note VP15-00-2 Wave soldering Soldering tub temperature: less than 260 °C, Hour: within 10 s. Time: 1 time, Limited days: no.Note WS60-00-1 Pin part heating Pin area temperature: less than 300 °C, Hour: within 3 s./pin Limited days: no.Note µPA103B Soldering process Infrared ray reflow Soldering conditions Symbol Peak package’s surface temperature: 230 °C or below, Reflow time: 10 seconds or below (210 °C or higher), Number of reflow process: 1, Exposure limit*: None Partial heating method Terminal temperature: 260 °C or below, Flow time: 10 seconds or below, Exposure limit*: None Note It is the storage days after opening a dry pack, the storage conditions are 25 °C, less than 65 % RH. Caution The combined use of soldering method is to be avoided (However, except the pin area heating method). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 6 Data Sheet P10708EJ2V0DS00 µPA103 [MEMO] Data Sheet P10708EJ2V0DS00 7 µPA103 NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. 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