DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2710GR SWITCHING P-CHANNEL POWER MOS FET DESCRIPTION PACKAGE DRAWING (Unit: mm) The µPA2710GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit. 8 5 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8 : Drain FEATURES • Low on-state resistance RDS(on)1 = 5.5 mΩ MAX. (VGS = –10 V, ID = –7.5 A) RDS(on)2 = 9.0 mΩ MAX. (VGS = –4.5 V, ID = –7.5 A) RDS(on)3 = 11 mΩ MAX. (VGS = –4.0 V, ID = –7.5 A) ★ • Low Ciss: Ciss = 4300 pF TYP. • Small and surface mount package (Power SOP8) ORDERING INFORMATION PART NUMBER PACKAGE µPA2710GR Power SOP8 4.4 0.8 0.15 +0.10 –0.05 1.44 6.0 ±0.3 4 5.37 MAX. 0.05 MIN. 1.8 MAX. 1 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS –30 V Gate to Source Voltage (VDS = 0 V) VGSS m20 V Drain Current (DC) ID(DC) m15 A ID(pulse) m100 A PT1 2 W PT2 2 W Tch 150 °C Tstg –55 to + 150 °C IAS −15 A EAS 22.5 mJ Drain Current (pulse) Note1 Total Power Dissipation Note2 Total Power Dissipation Note3 Channel Temperature Storage Temperature Single Avalanche Current Note4 Single Avalanche Energy Note4 Notes 1. 2. 3. 4. Remark EQUIVALENT CIRCUIT Drain Body Diode Gate Source PW ≤ 10 µs, Duty Cycle ≤ 1% 2 Mounted on ceramic substrate of 1200 mm x 2.2 mm Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G15978EJ3V0DS00 (3rd edition) Date Published February 2003 NS CP(K) Printed in Japan The mark ★ shows major revised points. 2002 µPA2710GR ★ ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = –30 V, VGS = 0 V –1 µA Gate Leakage Current IGSS VGS = m20 V, VDS = 0 V m100 nA –2.5 V Note VGS(off) VDS = –10 V, ID = –1 mA –1.0 | yfs | VDS = –10 V, ID = –7.5 A 14 RDS(on)1 VGS = –10 V, ID = –7.5 A 4.7 5.5 mΩ RDS(on)2 VGS = –4.5 V, ID = –7.5 A 6.4 9.0 mΩ RDS(on)3 VGS = –4.0 V, ID = –7.5 A 7.2 11 mΩ Gate Cut-off Voltage Note Forward Transfer Admittance Note Drain to Source On-state Resistance 31 S Input Capacitance Ciss VDS = –10 V 4300 pF Output Capacitance Coss VGS = 0 V 1200 pF Reverse Transfer Capacitance Crss f = 1 MHz 690 pF Turn-on Delay Time td(on) VDD = –15 V, ID = –7.5 A 11 ns VGS = –10 V 22 ns RG = 10 Ω 420 ns 240 ns Rise Time tr Turn-off Delay Time td(off) Fall Time tf Total Gate Charge QG VDD = –24 V 97 nC Gate to Source Charge QGS VGS = –10 V 12 nC Gate to Drain Charge QGD ID = –15 A 29 nC Body Diode Forward Voltage VF(S-D) IF = 15 A, VGS = 0 V 0.79 V Reverse Recovery Time trr IF = 15 A, VGS = 0 V 119 ns Reverse Recovery Charge Qrr di/dt = 50 A/µs 84 nC Note Pulsed PW≤350 µs, Duty Cycle≤2% TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME D.U.T. RG = 25 Ω D.U.T. L RL PG 50 Ω VDD VGS = –20 → 0 V RG PG. − IAS 90% VDS(−) VDS Wave Form τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = −2 mA RL 50 Ω VDD 90% VDS VGS(−) 0 τ Starting Tch 2 VDD VGS 10% 0 90% VDD PG. Wave Form BVDSS VDS ID VGS(−) VGS Data Sheet G15978EJ3V0DS 10% 10% 0 td(on) tr td(off) ton tf toff µPA2710GR TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 120 100 80 60 40 20 Mounted on ceramic substrate of 2 1200 mm x 2.2 mm 2.4 2 1.6 1.2 0.8 0.4 0 0 0 25 50 75 100 125 150 175 0 25 TA - Ambient Temperature - °C 50 75 100 125 150 175 TA - Ambient Temperature - °C ★ FORWARD BIAS SAFE OPERATING AREA - 1000 - 100 RDS(on) Limited 1 ms ID(DC) - 10 10 ms DC -1 100 ms Power Dissipation Limited - 0.1 TA = 25°C Single Pulse Mounted on ceramic substrate of 1200 mm2 x 2.2 mm - 0.01 - 0.01 - 0.1 -1 - 10 - 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 1000 rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A PW=100 µs ID(pulse) Rth(ch-A) = 62.5°C/W 100 10 1 0.1 0.01 100 µ Mounted on ceramic substrate of 2 1200 mm x 2.2 mm Single Pulse 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G15978EJ3V0DS 3 µPA2710GR ★ ★ DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE - 1000 −4.5 V - 100 VGS = −1 V - 80 Pulsed Pulsed ID - Drain Current - A ID - Drain Current - A - 120 FORWARD TRANSFER CHARACTERISTICS −4.0 V - 60 - 40 - 100 T ch = −55°C 25°C 75°C 150°C - 10 -1 - 0.1 - 20 V DS = −10 V 0 - 0.01 0 - 0.4 - 0.8 - 1.2 0 VDS - Drain to Source Voltage - V VGS(off) - Gate Cut-off Voltage - V -2 - 1.5 -1 - 0.5 P uls ed V D S = − 10 V 50 100 Tc h = − 55°C 25°C 75°C 150°C 10 1 V D S = − 10 V P uls ed 0.1 - 0.1 150 -1 RDS(on) - Drain to Source On-state Resistance - mΩ RDS(on) - Drain to Source On-state Resistance - mΩ P uls ed 15 10 V G S = − 4.0V 5 − 10 V -1 - 10 - 100 ID - Drain Current - A 4 - 100 ★ DRAIN TO SOURCE ON-STATE RESISTANCE vs. RESISTANCE vs. DRAIN CURRENT 0 - 0.1 - 10 ID - Drain Current - A ★ DRAIN TO SOURCE ON-STATE − 4.5 V -5 100 Tch - Channel Temperature - °C 20 -4 DRAIN CURRENT - 2.5 0 -3 ★ FORWARD TRANSFER ADMITTANCE vs. GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE 0 - 50 -2 VGS - Gate to Source Voltage - V | yfs | - Forward Transfer Admittance - S ★ -1 GATE TO SOURCE VOLTAGE 40 30 P uls ed ID = − 7.5 A 20 10 0 0 -5 - 10 - 15 VGS - Gate to Source Voltage - V Data Sheet G15978EJ3V0DS - 20 µPA2710GR ★ CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE CHANNEL TEMPERATURE 10 00 0 15 Ciss, Coss, Crss - Capacitance - pF V GS = − 4.0 V − 4.5 V − 10 V 10 5 P uls ed ID = − 7.5 A 0 - 50 0 50 100 C is s 10 00 C os s C rs s 10 0 V GS = 0 V f = 1 M Hz 10 0.0 1 150 Tch - Channel Temperature - °C 10 10 0 ★ DYNAMIC INPUT/OUTPUT CHARACTERISTICS ★ SWITCHING CHARACTERISTICS - 30 td(off) VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 1 VDS - Drain to Source Voltage - V 1000 tf 100 tr 10 td(on) VDD = −15 V VGS = −10 V RG = 10 Ω 1 - 0.1 - 15 V DD = −24 V −15 V −6 V - 20 -5 V GS V DS -1 - 10 - 100 0 20 40 60 80 0 100 QG - Gate Charge - nC ★ REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 10000 V G S = − 10 V trr - Reverse Recovery Time - ns P uls ed 100 ID = −15 A 0 ★ SOURCE TO DRAIN DIODE FORWARD VOLTAGE 1000 - 10 - 10 ID - Drain Current - A IF - Diode Forward Current - A 0.1 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ ★ DRAIN TO SOURCE ON-STATERESISTANCE vs. 0 V 10 1 0.1 1000 100 VGS = 0 V di/dt = 50 A /µs 10 0.01 0 0.2 0.4 0.6 0.8 1 1.2 VF(S-D) - Source to Drain Voltage - V 0.1 1 10 100 IF - Diode Forward Current - A Data Sheet G15978EJ3V0DS 5 µPA2710GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD SINGLE AVALANCHE ENERGY DERATING FACTOR 100 Energy Derating Factor - % IAS - Single Avalanche Current - A - 100 IAS = −15 A - 10 E AS = 22.5 mJ -1 V DD = −15 V V GS = −20 → 0 V R G = 25 Ω Starting T ch = 25°C - 0.1 0.01 0.1 80 60 40 20 0 1 10 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - °C L - Inductive Load - mH 6 VDD = −15 V RG = 25 Ω VGS = −20 → 0 V IAS ≤ −15 A Data Sheet G15978EJ3V0DS µPA2710GR • The information in this document is current as of February, 2003. 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