LH53259 FEATURES • 32,768 words × 8 bit organization • Access time: 150 ns (MAX.) • Low-power consumption: Operating: 137.5 mW (MAX.) Standby: 550 µW (MAX.) CMOS 256K (32K × 8) MROM PIN CONNECTIONS TOP VIEW 28-PIN DIP 28-PIN SOP NC 1 28 VCC A12 2 27 A14 A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE/OE A2 8 21 A10 A1 9 20 CE • Programmable output enable • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP 28-pin, 8 × 13.4 mm2 TSOP (Type I) • JEDEC standard EPROM pinout (DIP) DESCRIPTION The LH53259 is a mask-programmable ROM organized as 32,768 × 8 bits. It is fabricated using silicon-gate CMOS process technology. A0 10 19 D7 D0 11 18 D6 D1 12 17 D5 D2 13 16 D4 GND 14 15 D3 53259-1 Figure 1. Pin Connections for DIP and SOP Packages 28-PIN TSOP (Type I) TOP VIEW 1 28 A10 A11 2 27 CE OE/OE A9 3 26 D7 A8 4 25 D6 A13 5 24 D5 A14 6 23 D4 VCC 7 22 D3 NC 8 21 GND A12 9 20 D2 A7 10 19 D1 A6 11 18 D0 A5 12 17 A0 A4 13 16 A1 A3 14 15 A2 53259-7 Figure 2. Pin Connections for TSOP Package 1 LH53259 CMOS 256K MROM 27 26 2 23 MEMORY MATRIX (32,768 x 8) ADDRESS BUFFER A10 21 A9 24 A8 25 ADDRESS DECODER A14 A13 A12 A11 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 COLUMN SELECTOR A1 9 A0 10 SENSE AMPLIFIER CE BUFFER CE 20 TIMING GENERATOR OUTPUT BUFFER OE BUFFER OE/OE 22 28 14 VCC GND 11 D0 12 D1 13 D2 15 D3 16 D4 17 D5 18 D6 19 D7 NOTE: Pin numbers apply to the 28-pin DIP or SOP. 53259-2 Figure 3. LH53259 Block Diagram PIN DESCRIPTION SIGNAL A0 – A14 D0 – D7 CE OE/OE PIN NAME NOTE SIGNAL PIN NAME Address input VCC Power supply (+5 V) Data output GND Ground NC Chip enable input Output enable input NOTE No connection 1 NOTE: 1. The active level of OE/OE is mask-programmable. TRUTH TABLE CE OE/OE H X L L/H H/L NOTE: 1. X = H or L MODE D0 - D7 Non selected High-Z Selected DOUT SUPPLY CURRENT NOTE Standby 1 Operating ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage 2 SYMBOL RATING UNIT VCC –0.3 to +7.0 V CMOS 256K MROM LH53259 Input voltage VIN –0.3 to VCC +0.3 V Output voltage VOUT –0.3 to VCC +0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VCC 4.5 5.0 5.5 V Supply voltage DC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER Input ‘Low’ voltage SYMBOL CONDITIONS MIN. VIL TYP. MAX. UNIT –0.3 0.8 V 2.2 VCC + 0.3 V 0.4 V NOTE Input ‘High’ voltage VIH Output ‘Low’ voltage VOL I OL = 1.6 mA Output ‘High’ voltage VOH I OH = –400 µA Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 ICC1 t RC = 150 ns 25 ICC2 t RC = 1 µs 20 mA 2 ICC3 t RC = 150 ns 20 ICC4 t RC = 1 µs 15 mA 3 Operating current Standby current Input capacitance Output capacitance 2.4 V ISB1 CE = V IH 2 mA ISB2 CE = V CC – 0.2 V 100 µA CIN f = 1 MHz T A = 25°C 10 pF 10 pF COUT NOTES: 1. CE/OE = VIH or OE = VIL 2. VIN = VIH/VIL, CE = VIL, outputs open 3. VIN = (VCC – 0.2 V) or 0.2 V, CE = 0.2 V, outputs open AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Read cycle time tRC 150 Address access time tAA Chip enable access time tACE Output enable time tOE 10 Output hold time tOH 5 CE to output in High-Z tCHZ 70 ns OE to output in High-Z tOHZ 70 ns NOTE ns 150 ns 150 ns 80 ns ns 1 NOTE: 1. This is the time required for the output to become high impedance. 3 LH53259 CMOS 256K MROM AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude 0.6 V to 2.4 V Input rise/fall time 10 ns Input reference level 1.5 V Output reference level 0.8 V and 2.2 V Output load condition 1TTL + 100 pF tRC A0 - A14 tAA (NOTE) CE tACE (NOTE) tCHZ OE OE tOE (NOTE) tOHZ tOH D0 - D7 DATA VALID NOTE: Data becomes valid after the intervals tAA, tACE, and tOE from address inputs, chip enable and output enable, respectively have been met. 53259-3 Figure 4. Timing Diagram 4 CMOS 256K MROM LH53259 PACKAGE DIAGRAMS 28DIP (DIP028-P-0600) 28 15 DETAIL 13.45 [0.530] 12.95 [0.510] 1 0° TO 15° 14 0.30 [0.012] 0.20 [0.008] 36.30 [1.429] 35.70 [1.406] 15.24 [0.600] TYP. 4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. 0.60 [0.024] 0.40 [0.016] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-2 28-pin, 600-mil DIP 28SOP (SOP028-P-0450) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.70 [0.067] 28 15 8.80 [0.346] 8.40 [0.331] 1 12.40 [0.488] 11.60 [0.457] 10.60 [0.417] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP 5 LH53259 CMOS 256K MROM 28TSOP (TSOP028-P-0813) 0.28 [0.011] 0.12 [0.005] 0.55 [0.022] TYP. 28 15 12.00 [0.472] 11.60 [0.457] 1 13.70 [0.539] 13.10 [0.516] 12.60 [0.496] 12.20 [0.480] 14 8.20 [0.323] 7.80 [0.307] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] DETAIL 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] 0 - 10° 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000] MAXIMUM LIMIT MINIMUM LIMIT 28TSOP 28-pin, 8 × 13.4 mm2 TSOP (Type I) ORDERING INFORMATION LH53259 Device Type X Package D 28-pin, 600-mil DIP (DIP028-P-0600) N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13.4 mm2 TSOP (Type I) (TSOP028-P-0813) CMOS 256K (32K x 8) Mask Programmable ROM Example: LH53259D (CMOS 256K (32K x 8) Mask Programmable ROM, 28-pin, 600-mil DIP) 53259-6 6