STE48NM60 N-CHANNEL 600V - 0.09Ω - 48A ISOTOP MDmesh™Power MOSFET TYPE STE48NM60 VDSS RDS(on) ID 600V < 0.11Ω 48 A TYPICAL RDS(on) = 0.09Ω HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. ISOTOP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ±30 V ID Drain Current (continuous) at TC = 25°C 48 A ID Drain Current (continuous) at TC = 100°C 30 A VDS VDGR VGS IDM () PTOT dv/dt (1) Tstg Tj Parameter Drain Current (pulsed) 192 A Total Dissipation at TC = 25°C 450 W Derating Factor 3.57 W/°C Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area June 2003 15 V/ns –65 to 150 °C 150 °C (1) ISD ≤48A, di/dt ≤400A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. 1/8 STE48NM60 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.28 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W 300 °C Tl Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) Max Value Unit 15 A 850 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 600 Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 10 µA VDS = Max Rating, TC = 125 °C 100 µA Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 22.5A Min. Typ. Max. Unit 3 4 5 V 0.09 0.11 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 22.5A VDS = 25V, f = 1 MHz, VGS = 0 Min. 15 S 3800 pF 1250 pF 46 pF Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Coss eq. (2) Equivalent Output Capacitance VGS = 0V, VDS = 0V to 480V 340 pF Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 1.4 Ω RG 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS 2/8 STE48NM60 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. VDD = 250V, ID = 22.5A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 400V, ID = 45A, VGS = 10V Typ. Max. Unit 30 ns 20 ns 96 134 nC 31 nC 43 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 400V, ID = 45A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Typ. Max. Unit 16 ns 23 ns 40 ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 48 A ISDM (2) Source-drain Current (pulsed) 192 A VSD (1) Forward On Voltage ISD = 45A, VGS = 0 1.5 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 45A, di/dt = 100A/µs, VDD = 100 V, Tj = 25°C (see test circuit, Figure 5) 508 10 40 ns µC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 45A, di/dt = 100A/µs, VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 650 14 43 ns µC A ISD trr Qrr IRRM trr Qrr IRRM Parameter Test Conditions Min. Typ. Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STE48NM60 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STE48NM60 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STE48NM60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STE48NM60 ISOTOP MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. A 11.8 12.2 0.466 TYP. MAX. 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 8.2 0.307 0.157 N 4 O 7.8 0.157 0.322 A G B O F E H D N J K C L M 7/8 STE48NM60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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