STMICROELECTRONICS STD3NK50Z-1

STQ3NK50ZR-AP
STD3NK50Z - STD3NK50Z-1
N-CHANNEL 500V - 2.8Ω - 2.3A TO-92/DPAK/IPAK
Zener-Protected SuperMESH™ MOSFET
Figure 1: Package
Table 1: General Features
TYPE
VDSS
RDS(on)
ID
Pw
STQ3NK50ZR-AP
STD3NK50Z
STD3NK50Z-1
500 V
500 V
500 V
3.3 Ω
3.3 Ω
3.3 Ω
0.5 A
2.3 A
2.3 A
3W
45 W
45 W
■
■
■
■
■
■
TYPICAL RDS(on) = 2.8Ω
EXTREMELY HIGH dv/dt CAPABILITY
ESD IMPROVED CAPABILITY)
100% AVALANCHE TESTED
NEW HIGH VOLTAGE BENCHMARK
GATE CHARGE MINIMIZED
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme opyimization of ST’s well established strip
based PowerMESH™ layout. In addition to pushing on-resistance significatly down, special care is
taken to ensure a very good dv/dt capability for the
most demanding application. Such series complements ST full range of high voltage MOSFETs
icluding revolutionary MDmesh™ products
3
1
DPAK
TO-92 (Ammopak)
3
2
1
IPAK
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ AC ADAPTORS AND BATTERY CHARGERS
■ SWITH MODE POWER SUPPLIES (SMPS)
■ LIGHTING
Table 2: Order Coder
SALES TYPE
MARKING
PACKAGE
PACKAGING
STQ3NK50ZR-AP
Q3NK50ZR
TO-92
AMMOPAK
STD3NK50Z
D3NK50Z
DPAK
TAPE & REEL
STD3NK50Z-1
D3NK50Z
IPAK
TUBE
Rev. 2
January 2005
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
DPAK/IPAK
VDS
VDGR
VGS
Unit
TO-92
Drain-source Voltage (VGS = 0)
500
V
Drain-gate Voltage (RGS = 20 kΩ)
500
V
Gate- source Voltage
±30
V
ID
Drain Current (continuous) at TC = 25°C
2.3
0.5
A
ID
Drain Current (continuous) at TC = 100°C
1.45
0.32
A
Drain Current (pulsed)
9.2
2
A
Total Dissipation at TC = 25°C
45
3
W
0.36
0.025
W/°C
IDM ()
PTOT
Derating Factor
VESD(G-S)
dv/dt (1)
Tj
Tstg
Gate source ESD (HBM-C=100 pF, R= 1.5KΩ)
2000
V
4.5
V/ns
-55 to 150
°C
Peak Diode Recovery voltage slope
Operating Junction Temperature
Storage Temperature
() Pulse width limited by safe operating area
(1) ID ≤ 2 di/dt ≤ 200A/µs, VDD ≤ V(BR)DSS
Table 4: Thermal Data
DPAK
Rthj-case
Thermal Resistance Junction-case Max
Rthj-amb
Thermal Resistance Junction-ambient Max
Rthj-lead
Thermal Resistance Junction-lead Max
Tl
IPAK
2.77
50 (#)
100
--
Maximum Lead Temperature For Soldering Purpose
-275
TO-92
Unit
--
°C/W
120
°C/W
40
°C/W
260
°C
(#) When mounted on 1inch² FR4, 2 Oz copper board.
Table 5: Avalanche Characteristics
Symbol
Parameter
Max. Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
2.3
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
120
mJ
Table 6: GATE-SOURCE ZENER DIODE
Symbol
BVGSO
Parameter
Gate-Source Breakdown
Voltage
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in-back-to-back Zener diodes have specifically been designed to enchance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
500
Unit
Drain-source
Breakdown Voltage
ID = 1 mA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating, TC = 125 °C
1
50
µA
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20V
±10
µA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 50 µA
3.75
4.5
V
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 1.15 A
2.8
3.3
Ω
Typ.
Max.
Unit
V(BR)DSS
3
V
Table 8: Dynamic
Symbol
gfs (1)
Ciss
Coss
Crss
Coss eq. (3)
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
Min.
VDS = 15 V, ID = 1.15 A
VDS = 25V, f = 1 MHz, VGS = 0
1.5
S
280
42
8
pF
pF
pF
27.5
pF
ns
ns
ns
ns
Equivalent Output
Capacitance
VGS = 0V, VDS = 0V to 400 V
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
VDD = 250 V, ID = 1.15 A
RG = 4.7Ω VGS = 10 V
(see Figure 19)
8
13
24
14
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 400 V, ID = 2.3 A,
VGS = 10V
(see Figure 22)
11
2.5
5.6
15
nC
nC
nC
Typ.
Max.
Unit
2.3
9.2
A
A
1.6
V
Table 9: Source Drain Diode
Symbol
Parameter
Test Conditions
Min.
ISD
ISDM (2)
Source-drain Current
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 2.3 A, VGS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD =2.3 A, di/dt = 100 A/µs
VDD = 40V, Tj = 25°C
(see Figure 20)
250
745
6
ns
µC
A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD =2.3A, di/dt = 100 A/µs
VDD = 40V, Tj = 150°C
(see Figure 20)
300
960
6.2
ns
µC
A
trr
Qrr
IRRM
trr
Qrr
IRRM
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
VDSS.
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Figure 3: Safe Operating Area For TO-92
Figure 6: Thermal Impedance TO-92
Figure 4: Safe Operating Area For DPAK / IPAK
Figure 7: Thermal Impedance For DPAK / IPAK
Figure 5: Output Characteristics
Figure 8: Transfer Characteristics
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Figure 9: Transconductance
Figure 12: Capacitance Variations
Figure 10: Gate Charge vs Gate-source Voltage
Figure 13: Normalized Gate Threshold Voltage
vs Temperature
Figure 11: Static Drain-Source On Resistance
Figure 14: Source-Drain Forward Characteristics
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Figure 15: Maximum Avalanche Energy vs
Temperature
Figure 16: Normalized On Resistance vs Temperature
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Figure 17: Normalized BVDSS vs Temperature
STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Figure 18: Unclamped Inductive Load Test Circuit
Figure 21: Unclamped Inductive Wafeform
Figure 19: Switching Times Test Circuit For
Resistive Load
Figure 22: Gate Charge Test Circuit
Figure 20: Test Circuit For Inductive Load
Switching and Diode Recovery Times
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.20
2.40
0.087
0.094
A1
0.90
1.10
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.213
C
0.45
0.60
0.018
0.024
C2
0.48
0.60
0.019
0.024
D
6.00
6.20
0.236
0.244
E
6.40
6.60
0.252
0.260
G
4.40
4.60
0.173
0.181
H
9.35
10.10
0.368
L2
0.8
0.398
0.031
L4
0.60
1.00
0.024
0.039
V2
0o
8o
0o
0o
P032P_B
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
TO-251 (IPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
B
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
C
0.45
C2
0.48
D
6
E
6.4
6.6
0.037
0.6
0.017
0.023
0.6
0.019
0.023
6.2
0.236
0.244
0.252
0.260
G
4.4
4.6
0.173
0.181
H
15.9
16.3
0.626
0.641
L
9
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
1
0.031
0.039
A1
C2
A3
A
C
H
B
B3
=
1
=
2
G
=
=
=
E
B2
=
3
B5
L
D
B6
L2
L1
0068771-E
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
TO-92 MECHANICAL DATA
mm.
inch
DIM.
MIN.
MAX.
MIN.
TYP.
MAX.
A
4.32
4.95
0.170
0.194
b
0.36
0.51
0.014
0.020
D
4.45
4.95
0.175
0.194
E
3.30
3.94
0.130
0.155
e
2.41
2.67
0.094
0.105
0.055
e1
1.14
1.40
0.044
L
12.70
15.49
0.50
0.610
R
2.16
2.41
0.085
0.094
S1
0.92
1.52
0.036
0.060
W
0.41
0.56
0.016
0.022
V
10/14
TYP
5°
5°
STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
DPAK FOOTPRINT
TUBE SHIPMENT (no suffix)*
All dimensions
are in millimeters
All dimensions are in millimeters
TAPE AND REEL SHIPMENT (suffix ”T4”)*
REEL MECHANICAL DATA
DIM.
mm
MIN.
A
B
1.5
C
12.8
D
20.2
G
16.4
N
50
T
TAPE MECHANICAL DATA
DIM.
mm
inch
MIN.
MAX.
A0
6.8
7
0.267 0.275
B0
10.4
10.6
0.409 0.417
B1
D
1.5
MIN.
12.1
0.476
1.6
0.059 0.063
1.5
E
1.65
1.85
F
7.4
7.6
0.291 0.299
K0
2.55
2.75
0.100 0.108
0.153 0.161
3.9
4.1
7.9
8.1
0.311 0.319
P2
1.9
2.1
0.075 0.082
40
12.992
13.2
0.504 0.520
18.4
0.645 0.724
0.059
0.795
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
2500
0.065 0.073
P0
15.7
MAX.
330
0.059
P1
R
MIN.
MAX.
D1
W
inch
MAX.
1.574
16.3
0.618
0.641
* on sales type
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
TO-92 AMMOPACK
DIM.
mm.
MIN.
TYP
MIN.
TYP.
MAX.
A1
4.45
4.95
0.170
0.194
T
3.30
3.94
0.130
0.155
T1
1.6
T2
2.3
0.56
0.06
0.09
d
0.41
P0
12.5
12.7
12.9
0.49
0.5
0.51
P2
5.65
6.35
7.05
0.22
0.25
0.27
0.016
0.022
2.54
2.94
0.09
0.1
0.11
2
-0.08
19
0.69
0.71
0.74
F1, F2
2.44
delta H
-2
W
17.5
W0
5.7
6
6.3
0.22
0.23
0.24
W1
8.5
9
9.25
0.33
0.35
0.36
18
W2
18.5
H0
15.5
D0
0.08
0.5
H
16
H1
12/14
inch
MAX.
0.02
20.5
0.72
0.80
16.5
0.61
0.63
0.65
0.15
0.157
0.16
25
3.8
4
4.2
t
0.9
L
11
l1
3
delta P
-1
0.98
0.035
0.43
0.11
1
-0.04
0.04
STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Table 10: Revision History
Date
Revision
09-Jul-2004
17-Jan-2005
1
2
Description of Changes
First Release.
Complete Version
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STD3NK50Z - STD3NK50Z-1 - STQ3NK50ZR-AP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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