SSG6680
11.5A, 30V,RDS(ON) 11mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode Power Mos.FET
RoHS Compliant Product
SOP-8
Description
0.19
0.25
0.40
0.90
The SSG6680 provide the designer with the best combination of fast switching,
45
o
0.375 REF
6.20
5.80
ruggedized device design, low on-resistance and cost-effectiveness.
0.25
The SOP-8 is universally preferred for all commercial
industrial surface mount application and suited for low
3.80
4.00
voltage applications such as DC/DC converters.
1.27Typ.
0.35
0.49
4.80
5.00
0.100.25
o
0
o
8
Features
1.35
1.75
Dimensions in millimeters
* Surface Mount Package
D
D
D
D
* High Vgs Max. Rating Voltage
8
7
6
5
D
* Low On-Resistance
6680SC
Date Code
G
1
2
3
4
S
S
S
G
S
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Ratings
Unit
VDS
30
V
±25
V
11.5
A
ID@TA=70 C
9.5
A
IDM
50
A
2.5
W
0.02
W/ C
VGS
Continuous Drain Current
3
Continuous Drain Current
3
Pulsed Drain Current
Symbol
o
ID@TA=25 C
o
1
o
PD@TA=25 C
Total Power Dissipation
Linear Derating Factor
Operating Junction and Storage Temperature Range
Tj, Tstg
-55~+150
Symbol
Ratings
o
o
C
Thermal Data
Parameter
Thermal Resistance Junction-ambient
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
3
Max.
Rthj-a
50
Unit
o
C /W
Any changing of specification will not be informed individual
Page 1 of 5
SSG6680
11.5A, 30V,RDS(ON) 11mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode Power Mos.FET
Electrical Characteristics( Tj=25 oC Unless otherwise specified)
Parameter
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Gate Threshold Voltage
Gate-Source Leakage Current
Drain-Source Leakage Current (Tj=25oC)
Drain-Source Leakage Current (Tj=70oC)
Static Drain-Source On-Resistance2
Symbol
Min.
Typ.
Max.
Unit
BVDSS
30
_
_
V
BVDS/ Tj
_
0.02
_
V/ oC
VGS(th)
1.0
_
3.0
IGSS
_
_
_
_
_
_
IDSS
RDS(ON)
±100
nA
VGS=± 25A
1
uA
VDS=30V,VGS=0
_
25
uA
VDS=24V,VGS=0
_
11
Qg
_
16.8
Gate-Source Charge
Qgs
_
Gate-Drain ("Miller") Charge
Qgd
Turn-on Delay Time2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Forward Transconductance
_
Td(ON)
_
Tr
_
Td(Off)
_
Tf
_
Ciss
Coss
_
_
Reference to 25oC, ID=1mA
VDS=VGS, ID=250uA
_
2
VGS=0V, ID=250uA
V
_
Total Gate Charge
Test Condition
VGS=10V, ID=11.5A
VGS=4.5V, ID=9.5A
18
_
4.2
_
8
_
8.9
_
7.3
_
25.6
_
18.6
_
1450
mΩ
nC
ID=11.5A
VDS=15V
VGS=5V
VDD=15V
ID=1A
nS
VGS=10V
RG=5.5 Ω
RD=10 Ω
_
285
_
180
_
Crss
_
Gfs
_
30
_
Min.
Typ.
Max.
_
_
_
_
pF
VGS=0V
VDS=25V
S
VDS=15V, ID=11.5A
f=1.0MHz
Source-Drain Diode
Parameter
Forward On Voltage 2
Continuous Source Current (Body Diode)
Symbol
VDS
Is
Unit
Test Condition
o
1.3
V
IS=3.5A,VGS=0V,Tj=25 C
1.92
A
VD=VG=0V, VS=1.3V
Notes: 1.Pulse width limited by Max. junction temperature
2.Pulse width≦300us, dutycycle≦2%.
3.Surface mounted on 1 inch2 copper pad of FR4 board; 125°C/W when mounted on min. copper pad.
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
Any changing of specification will not be informed individual
Page 2 of 5
SSG6680
11.5A, 30V,RDS(ON) 11mΩ
Elektronische Bauelemente
N-Channel Enhancement Mode Power Mos.FET
Characteristics Curve
Fig 1. Typical Output Characteristics
Fig 3. On-Resistance v.s. Gate Voltage
Fig 5. Maximum Drain Current
v.s. Case Temperature
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
Fig 2. Typical Output Characteristics
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
Fig 6. Type Power Dissipation
Any changing of specification will not be informed individual
Page 3 of 5
SSG6680
11.5A, 30V,RDS(ON) 11mΩ
Elektronische Bauelemente
Fig 7. Maximum Safe Operating Area
Fig 9. Gate Charge Characteristics
Fig 11. Forward Characteristics of
Reverse Diode
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
N-Channel Enhancement Mode Power Mos.FET
Fig 8. Effective Transient Thermal Impedance
Fig 10. Typical Capacitance Characteristics
Fig 12. Gate Threshold Voltage v.s.
Junction Temperature
Any changing of specification will not be informed individual
Page 4 of 5
SSG6680
11.5A, 30V,RDS(ON) 11mΩ
Elektronische Bauelemente
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
http://www.SeCoSGmbH.com/
01-Jun-2002 Rev. A
N-Channel Enhancement Mode Power Mos.FET
Any changing of specification will not be informed individual
Page 5 of 5