TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 D D D D D D D D D D Organization TM124MBK36F . . . 1 048 576 × 36 TM248NBK36F . . . 2 097 152 × 36 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Socket TM124MBK36F – Utilizes Two 16-Megabit and One 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248NBK36F – Utilizes Four 16-Megabit and Two 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period . . . 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh D D Presence Detect Performance Ranges: ACCESS TIME tRAC D D D D ’124MBK36F-60 ’124MBK36F-70 ’124MBK36F-80 ’248NBK36F-60 ’248NBK36F-70 ’248NBK36F-80 (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tAA tCAC WRITE CYCLE (MAX) (MAX) (MIN) 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns Low Power Dissipation Operating Free-Air Temperature Range: 0°C to 70°C Gold-Tabbed Versions Available:† – TM124MBK36F – TM248NBK36F Tin-Lead (Solder) Tabbed Versions Available: – TM124MBK36U – TM248NBK36U description TM124MBK36F The TM124MBK36F is a 4-MByte dynamic random-access memory (DRAM) organized as four times 1 048 576 × 9 in a 72-pin single-in-line memory module (SIMM). The SIMM is composed of two TMS418160DZ, 1 048 576 × 16-bit dynamic RAMs, each in a 42-lead plastic small-outline J-lead ( SOJ) package and one TMS44460DJ, 1 048 576 × 4-bit DRAM in a 24 / 26-lead plastic small-outline J-lead ( SOJ) package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and TMS44460 data sheets, respectively. The TM124MBK36F SIMM is available in the single-sided BK leadless module for use with sockets. TM248NBK36F The TM248NBK36F is an 8-MByte DRAM organized as four times 2 097 152 × 9 in a 72-pin single-in-line memory module (SIMM). The SIMM is composed of four TMS418160DZ, 1 048 576 × 16-bit dynamic RAMs, each in a 42-lead plastic small-outline J-lead ( SOJ) package and two TMS44460DJ, 1 048 576 × 4-bit DRAMs, each in a 24 / 26-lead plastic small-outline (SOJ) package mounted on a substrate with decoupling capacitors. The TMS418160DZ and TMS44460DJ are described in the TMS418160 and TMS44460 data sheets, respectively. The TM248NBK36F SIMM is available in the double-sided BK leadless module for use with sockets. operation The TM124MBK36F operates as two TMS418160DZs and one TMS44460DJ connected as shown in the functional block diagram and NO TAG. The TM248NBK36F operates as four TMS418160DZs and two TMS44460DJs connected as shown in the functional block diagram and NO TAG. The common I / O feature dictates the use of early write cycles to prevent contention on D and Q. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 2 BK SINGLE-IN-LINE MEMORY MODULE TM124MBK36F TM248NBK36F (TOP VIEW) (SIDE VIEW) (SIDE VIEW) VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 RAS3 RAS2 DQ26 DQ8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 (TM248NBK36 only) PIN NOMENCLATURE A0 – A9 CAS0 – CAS3 DQ0 – DQ35 NC PD1 – PD4 RAS0 – RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) VSS VSS VSS VSS 80 ns VSS NC VSS NC 70 ns NC NC 60 ns NC NC 80 ns TM124MBK36F 70 ns 60 ns TM248NBK36F POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PD3 (69) PD4 (70) NC VSS NC VSS NC NC VSS NC NC VSS NC NC TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 Table 1. Connection Table DATA BLOCK RASx SIDE 1 SIDE 2† CASx DQ0 – DQ7 DQ8 RAS0 RAS2 RAS1 RAS3 CAS0 CAS0 DQ9 – DQ16 DQ17 RAS0 RAS2 RAS1 RAS3 CAS1 CAS1 DQ18 – DQ25 DQ26 RAS2 RAS2 RAS3 RAS3 CAS2 CAS2 DQ27 – DQ34 DQ35 RAS2 RAS2 RAS3 RAS3 CAS3 CAS3 † Side 2 applies to the TM248NBK36F only. single in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124MBK36F and TM248NBK36F: Nickel plate and gold plate over copper Contact area for TM124MBK36U and TM248NBK36U: Nickel plate and tin / lead over copper POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 functional block diagram [TM124MBK36F and TM248NBK36F, side 1] 10 A0 – A9 RAS0 W RAS2 1M × 16 A0 – A9 DQ0 – DQ7 RAS W LCAS DQ8 – UCAS DQ15 10 CAS0 CAS1 8 D0 – D7 8 D9 – D16 10 CAS2 CAS3 10 CAS0 CAS1 CAS2 CAS3 1M × 16 A0 – A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 1M × 4 A0 – A9 RAS W CAS1 CAS2 CAS3 CAS4 8 D18 – D25 8 D27 – D34 DQ1 DQ2 DQ3 DQ4 DQ8 DQ17 DQ26 DQ35 functional block diagram [TM248NBK36F, side 2] 10 A0 – A9 RAS1 W RAS3 10 CAS1 CAS0 1M × 16 A0 – A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 8 D9 – D16 8 D0 – D7 10 CAS3 CAS2 10 CAS0 CAS1 CAS2 CAS3 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1M × 16 A0 – A9 DQ0 – DQ7 RAS W LCAS DQ8 – UCAS DQ15 1M × 4 A0 – A9 RAS W CAS1 CAS2 CAS3 CAS4 DQ1 DQ2 DQ3 DQ4 8 D27 – D35 8 D18 – D25 DQ8 DQ17 DQ26 DQ35 TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation TM124MBK36F, TM124MBK36U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W TM248NBK36F, TM248NBK36U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage II Input current (leakage) IO ICC1 ICC2 Low-level output voltage ’124MBK36F - 60 TEST CONDITIONS MIN IOH = – 5 mA IOL = 4.2 mA ’124MBK36F - 70 MAX 2.4 MIN MAX 2.4 ’124MBK36F - 80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 10 ± 10 ± 10 µA Read- or write-cycle current VCC = 5.5 V, Minimum cycle 285 250 220 mA VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 6 6 6 mA VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 3 3 3 mA Standby current ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 285 250 220 mA ICC4 Average page current VCC = 5.5 V, tPC = MIN, CAS cycling RAS low, 250 220 190 mA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)† PARAMETER VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’248NBK36F - 60 TEST CONDITIONS MIN ’248NBK36F - 70 MAX 2.4 MIN ’248NBK36F - 80 MAX MIN 2.4 MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 20 ± 20 ± 20 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, 391 256 226 mA 12 12 12 mA 6 6 6 mA Standby current Minimum cycle VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 570 500 440 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 256 226 196 mA tPC = MIN, CAS cycling † For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) ’124MBK36F PARAMETER Ci(A) MIN Input capacitance, address inputs MAX ’248NBK36F MIN MAX 15 30 RAS2, RAS3 14 14 RAS0, RAS1 7 7 UNIT pF Ci(R) capacitance RAS inputs Input capacitance, Ci(C) Input capacitance, CAS inputs 14 28 pF Ci(W) Input capacitance, write-enable input 21 42 pF 7 14 pF Co(DQ) Output capacitance on DQ pins NOTE 5: Bias on pins under test is 0 V. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 pF TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124MBK36F - 60 ’248NBK36F - 60 PARAMETER MIN ’124MBK36F - 70 ’248NBK36F - 70 MAX MIN MAX ’124MBK36F - 80 ’248NBK36F - 80 MIN UNIT MAX tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tRAC tCPA Access time from RAS low 60 70 80 ns Access time from column precharge 35 40 45 ns tCLZ tOH CAS to output in low-impedance state 0 0 0 Output disable time from start of CAS high 3 3 3 tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven. 0 15 0 18 0 ns ns 20 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124MBK36F - 60 ’248NBK36F - 60 MIN ’124MBK36F - 70 ’248NBK36F - 70 MAX MIN MAX ’124MBK36F - 80 ’248NBK36F - 80 MIN UNIT MAX tRC tPC Cycle time, random read or write (see Note 7) 110 130 150 ns Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 50 ns tRASP tRAS Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS tCP Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns Pulse duration, CAS high (precharge) 10 10 10 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 ns Pulse duration, W low 10 10 10 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low 0 0 0 ns tCWL tRWL Setup time, W low before CAS high 15 18 20 ns Setup time, W low before RAS high 15 18 20 ns tWCS tWRP Setup time, W low before CAS low 0 0 0 ns Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH tRHCP Hold time, column address after CAS low 10 15 15 ns Hold time, RAS high from CAS precharge 35 40 45 ns tDH tRAH Hold time, data after CAS low 10 15 15 ns Hold time, row address after RAS low 10 10 10 ns tRCH tRRH Hold time, W high after CAS high (see Note 9) 0 0 0 ns Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH tWRH Hold time, W low after CAS low 10 15 15 ns Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP. 9. Either tRRH or tRCH must be satisfied for a read cycle. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124MBK36F - 60 ’248NBK36F - 60 MIN MAX ’124MBK36F - 70 ’248NBK36F - 70 MIN MAX ’124MBK36F - 80 ’248NBK36F - 80 MIN UNIT MAX tCHR tCRP Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns Delay time, CAS high to RAS low 5 5 5 ns tCSH tCSR Delay time, RAS low to CAS high 60 70 80 ns 5 5 5 tRAD tRAL Delay time, RAS low to column address (see Note 10) 15 Delay time, column address to RAS high 30 35 40 ns tCAL tRCD Delay time, column address to CAS high 30 35 40 ns Delay time, RAS low to CAS low (see Note 10) 20 tRPC tRSH Delay time, RAS high to CAS low (CBR only) tREF tT Refresh time interval Delay time, CAS low to RAS low (CBR refresh only) Delay time, CAS low to RAS high 30 45 15 20 52 ns 18 20 ns 30 -SS Year Code Month Code Assembly Site Code Speed Code NOTE: Location of symbolization may vary. 8 POST OFFICE BOX 1443 ns 15 16 3 30 device symbolization (TM124MBK36F illustrated) = = = = 60 ns 0 NOTE 10: The maximum value is specified only to assure access time. YY MM T -SS 20 ns 40 0 3 TM124MBK36F 15 0 16 Transition time 35 • HOUSTON, TEXAS 77251–1443 YYMMT 3 16 ms 30 ns IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated