UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 REVISION HISTORY REVISION Rev. 1.0 Rev. 1.1 DESCRIPTION Original 1. Revised Page 8 : 28 STSOP DIMENSION : a. Db D, b. D HD UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 DATE Oct 15,2001 Jan 20,2003 P80074 UTRON UT6164C Rev. 1.1 8K X 8 BIT HIGH SPEED CMOS SRAM FEATURES GENERAL DESCRIPTION Fast access time : 10/12/15 ns (max.) Low operating power consumption : 80 mA (typical) Single 5V power supply All inputs and outputs TTL compatible Fully static operation Three state outputs Package : 28-pin 300 mil SOJ 28-pin 8mm×13.4mm STSOP The UT6164C is a 65,536-bit high-speed CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT6164C is designed for high-speed system applications. It is particularly suited for use in high-density high-speed system applications. The UT6164C operates from a single 5V power supply and all inputs and outputs are fully TTL compatible. FUNCTIONAL BLOCK DIAGRAM A0-A12 DECODER PIN CONFIGURATION 128 × 512 MEMORY ARRAY Vcc Vss CE1 CE2 OE WE COLUMN I/O CONTROL CIRCUIT 1 28 2 27 WE A7 3 26 CE2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 A2 8 A1 9 A0 10 UT6164C I/O DATA CIRCUIT I/O1-I/O8 Vcc NC A12 22 OE 21 A10 20 CE1 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 SOJ PIN DESCRIPTION SYMBOL A0 - A12 I/O1 - I/O8 CE1 、CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input WE OE VCC VSS Write Enable Input Output Enable Input 1 28 2 27 A9 3 26 A8 4 25 I/O7 CE2 5 24 I/O6 WE 6 23 I/O5 Vcc 7 22 I/O4 UT6164C CE1 I/O8 NC 8 21 Vss A12 9 20 I/O3 A7 10 19 I/O2 A6 11 18 I/O1 A5 12 17 A0 A4 13 16 A1 A3 14 15 A2 Power Supply Ground STSOP UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 A10 OE A11 P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to +6.5 0 to +70 -65 to +150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Standby Output Disable Read Write CE2 X L H H H CE1 H X L L L OE X X H L X WE X X H H L I/O OPERATION SUPPLY CURRENT High - Z High - Z High - Z DOUT DIN ISB,ISB1 ISB,ISB1 ICC ICC ICC Note: H = VIH, L=VIL, X = Don't care. DC ELECTRICAL CHARACTERISTICS (VCC = 5V± 10%, TA = 0℃ to 70℃) PARAMETER Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Power Supply Current Standby Current (TTL) SYMBOL TEST CONDITION VIH VIL ILI VSS ≦VIN ≦VCC ILO VSS ≦VI/O ≦VCC VOH VOL ICC ISB Standby Current (CMOS) ISB1 CE1 =VIH or CE2=VIL or OE =VIH or WE =VIL IOH = - 4mA IOL = 8mA Cycle time=Min. CE1 = VIL , CE2= VIH II/O = 0mA CE1 = VIH or CE2= VIL - 10 - 12 - 15 CE1 ≧VCC-0.2V or CE2≦0.2V MIN. 2.2 - 0.5 -1 MAX. VCC+0.5 0.8 1 UNIT V V µA -1 1 µA 2.4 - 0.4 180 160 140 30 V V mA mA mA mA - 5 mA Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 8ns. 2. Undershoot : Vss-2.0v for pulse width less than 8ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 CAPACITANCE (TA=25 , f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. MAX. 8 10 - UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 3ns 1.5V CL=30pF, IOH/IOL=-4mA/8mA AC ELECTRICAL CHARACTERISTICS (VCC = 5V± 10% , TA = 0℃ to 70℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT6164C-10 UT6164C-12 UT6164C-15 UNIT MIN. MAX. MIN. MAX. MIN. MAX. 10 2 0 3 10 10 5 5 5 - 12 3 0 3 12 12 6 6 6 - 15 4 0 3 15 15 7 7 7 - ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* UT6164C-10 UT6164C-12 UT6164C-15 MIN. MAX. MIN. MAX. MIN. MAX. 10 8 8 0 8 0 6 0 2 - 6 12 10 10 0 9 0 7 0 3 - 7 15 12 12 0 10 0 8 0 4 - 8 UNIT ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2,4) tRC Address tAA tOH tOH DOUT Data Valid READ CYCLE 2 ( CE1 、CE2 and OE Controlled) (1,3,5,6) t RC Address t AA t ACE1 CE1 CE2 t ACE2 OE t CLZ1 t CLZ2 Dout HIGH-Z t CHZ1 t CHZ2 t OE t OH t OLZ t OHZ HIGH-Z Data Valid Notes : 1. WE is high for read cycle. 2. Device is continuously selected CE 1 =VIL and CE2=VIH. 3. Address must be valid prior to or coincident with CE 1 and CE2 transition; otherwise tAA is the limiting parameter. 4. OE is low. 5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state. 6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5) t WC Address t AW CE1 t CW1 CE2 t CW2 t AS t WR t WP WE t WH t OW High-Z Dout (4) (4) t DW Din t DH Data Valid WRITE CYCLE 2 ( CE1 、CE2 Controlled) (1,2,5) t WC Address t AW CE1 t AS t CW1 t WR t CW2 CE2 t WP WE t WHZ High-Z Dout t DH t DW Din Notes : 1. WE Data Valid or CE 1 must be high or CE2 must be low during all address transitions. 2. A write occurs during the overlap of a low CE 1 , a high CE2 and a low WE . 3. During a WE controlled with write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the I/O drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input singals must not be applied. 5. If the CE 1 low and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6. tOW and tWHZ are specified with CL=5pF. Transition is measured ± 500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 PACKAGE OUTLINE DIMENSION 28 pin 300 mil SOJ Package Outline Dimension 28 15 1 14 A2 UNIT SYMBOL CL A A1 A2 B B1 c D E E1 e L S Y X XX Note: 1. S/E/D DIM NOT INCLUDEING MOLD FLASH. 2. THE END FLASH IN PACKAGE LENGTHWISE IS NOT MORE THAN 10 MILS EACH SIDE UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 INCH(REF) 0.140 (MAX) 0.026 (MIN) 0.100± 0.005 0.018± 0.003 0.028 ± 0.003 0.010± 0.003 0.710± 0.010 0.337± 0.010 0.300± 0.005 0.050± 0.003 0.087± 0.010 0.030± 0.004 0.003 (MAX) MM(BASE) 3.556 (MAX) 0.660 (MIN) 2.540± 0.127 0.457± 0.076 0.711± 0.076 0.254± 0.076 18.03± 0.254 8.560± 0.254 7.620± 0.127 1.270± 0.076 2.210± 0.254 0.762± 0.102 0.076 (MAX) P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 28 pin 8x13.4mm STSOP PACKAGE OUTLINE DIMENSION HD cL 12° (2x) 28 14 15 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 14 15 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE 12° (2X) L 1 28 "A" DATAIL VIEW UNIT SYMBOL Note： E dimension is not including end flash the total of both sides’ end flash is not above 0.3mm. A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) 0.047 (MAX) 0.004± 0.002 0.039± 0.002 0.008± 0.001 0.005 (TYP) 0.465± 0.004 0.315± 0.004 0.022 (TYP) 0.528± 0.008 0.0236± 0.004 0.0315± 0.004 0.003(MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 L1 MM(REF) 1.20 (MAX) 0.10± 0.05 1.00± 0.05 0.200± 0.025 0.127(TYP) 11.80± 0.10 8.00± 0.10 0.55(TYP) 13.40± 0.20 0.50± 0.10 0.80± 0.10 0.076(MAX) o o 0 ∼5 P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 ORDERING INFORMATION PART NO. UT6164CJC-10 UT6164CJC-12 UT6164CJC-15 UT6164CLS-10 UT6164CLS-12 UT6164CLS-15 ACCESS TIME (ns) 10 12 15 10 12 15 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 PACKAGE 28 PIN SOJ 28 PIN SOJ 28 PIN SOJ 28 PIN STSOP 28 PIN STSOP 28 PIN STSOP P80074 UTRON UT6164C 8K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.1 THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80074