DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1744TP SWITCHING N-CHANNEL POWER MOS FET PACKAGE DRAWING (Unit: mm) DESCRIPTION The µ PA1744TP is N-channel MOS FET device that features a low on-state resistance and excellent switching characteristics, and designed for high voltage applications such as DC/DC converter. 8 5 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8, 9: Drain 1 0.8 ±0.2 0.05 ±0.05 +0.10 –0.05 0.12 M 4 Power HSOP8 8 1.1 ±0.2 1 2.9 MAX. µ PA1744TP 0.10 S 1.27 TYP. 0.40 2.0 ±0.2 PACKAGE 4.4 ±0.15 0.15 S ORDERING INFORMATION PART NUMBER 6.0 ±0.3 4 5.2 +0.17 –0.2 +0.10 –0.05 • Low on-state resistance RDS(on) = 30 mΩ MAX. (VGS = 10 V, ID = 5.0 A) • Low input capacitance Ciss = 3400 pF TYP. (VDS = 10 V, VGS = 0 V) • Built-in gate protection diode • Small and surface mount package (Power HSOP8) 1.44 TYP. 1.49 ±0.21 FEATURES 9 4.1 MAX. 5 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, Unless otherwise noted, all terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS 100 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V Drain Current (DC) (TC = 25°C) ID(DC) ±10 A ID(pulse) ±30 A PT1 39 W Drain Current (pulse) Note1 Total Power Dissipation (TC = 25°C) Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Single Avalanche Current Note3 Single Avalanche Energy Note3 Note2 PT2 3.0 W Tch 150 °C Tstg −55 to +150 °C IAS 10 A EAS 10 mJ EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Source Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2. Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm 3. Starting Tch = 25°C, VDD = 50 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 µH Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16410EJ1V0DS00 (1st edition) Date Published March 2003 NS CP(K) Printed in Japan 2002 µ PA1744TP ELECTRICAL CHARACTERISTICS (TA = 25°C, Unless otherwise noted, all terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 100 V, VGS = 0 V 10 µA Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±10 µA VGS(off) VDS = 10 V, ID = 1 mA 2.5 3.0 3.5 V | yfs | VDS = 10 V, ID = 5.0 A 7 14 RDS(on) VGS = 10 V, ID = 5.0 A Gate Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note S 23 30 mΩ Input Capacitance Ciss VDS = 10 V 3400 pF Output Capacitance Coss VGS = 0 V 390 pF Reverse Transfer Capacitance Crss f = 1 MHz 200 pF Turn-on Delay Time td(on) VDD = 50 V, ID = 5.0 A 22 ns tr VGS = 10 V 10 ns td(off) RG = 10 Ω 55 ns 7 ns Rise Time Turn-off Delay Time Fall Time tf Total Gate Charge QG VDD = 80 V 66 nC Gate to Source Charge QGS VGS = 10 V 12 nC QGD ID = 10 A 22 nC VF(S-D) IF = 10 A, VGS = 0 V 0.8 V Reverse Recovery Time trr IF = 10 A, VGS = 0 V 65 ns Reverse Recovery Charge Qrr di/dt = 100 A/µs 170 nC Gate to Drain Charge Body Diode Forward Voltage Note Note Pulsed: PW ≤ 350 µs, Duty Cycle ≤ 2% TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% BVDSS IAS VDS VDS ID Starting Tch τ τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE PG. 2 50 Ω 10% 0 10% Wave Form VDD D.U.T. IG = 2 mA 90% VDS VGS 0 RL VDD Data Sheet G16410EJ1V0DS td(on) tr ton td(off) tf toff µ PA1744TP TYPICAL CHARACTERISTICS (TA = 25°C, Unless otherwise noted, all terminals are connected.) TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 40 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 30 20 10 0 0 0 25 50 75 100 125 150 0 175 TC - Case Temperature - °C 25 50 75 100 125 150 175 TC - Case Temperature - °C FORWARD BIAS SAFE OPERATING AREA R DS(on) Lim ited (V GS = 10 V) I D(pulse) = 30 A T C = 25°C Single pulse PW = 1 m s 10 I D(DC) = 10 A 1 0.1 0.01 10 m s Power Dissipation Lim ited 0.1 1 10 100 m s 100 1000 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 10 rth(t) - Transient Thermal Resistance - °C/W ID - Drain Current - A 100 Rth(ch-C) = 3.2°C/W 1 Single Pulse 0.1 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s Data Sheet G16410EJ1V0DS 3 µ PA1744TP DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 35 100 ID - Drain Current - A 30 ID - Drain Current - A V DS = 10 V Pulsed V GS = 10 V Pulsed 25 20 15 10 10 T A = 150°C 125°C 75°C 25°C −25°C 1 0.1 0.01 5 0 0.001 0 0.2 0.4 0.6 0.8 3 4 5 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT | yfs | - Forward Transfer Admittance - S GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE V DS = 10 V ID = 1 m A 3.5 3 2.5 2 1.5 1 0.5 0 25 50 75 100 125 150 100 V D S = 10 V P ulsed T A = −25°C 25°C 75°C 125°C 150°C 10 1 0.1 0.01 0.001 0.01 0.1 1 10 100 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 30 V GS = 10 V Pulsed 25 20 15 0.1 1 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ VGS(off) - Gate Cut-off Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ 2 VGS - Gate to Source Voltage - V 0 40 ID = 5.0 A Pulsed 35 30 25 20 15 10 0 5 10 15 VGS - Gate to Source Voltage - V ID - Drain Current - A 4 1 VDS - Drain to Source Voltage - V 4 -25 0 Data Sheet G16410EJ1V0DS 20 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 60 1 00 00 V GS = 10 V I D = 5.0 A Pulsed 40 30 20 10 C iss 1 00 0 C oss 1 00 C rs s VGS = 0 V f = 1 MHz 0 -25 0 25 50 75 100 125 10 0 .01 150 0 .1 Tch - Channel Temperature - °C SWITCHING CHARACTERISTICS 1 00 1 20 V D D = 50 V V G S = 10 V RG = 0 Ω 100 t d(off) t d(on) tr 10 tf VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns 10 DYNAMIC INPUT/OUTPUT CHARACTERISTICS 1000 12 ID = 1 0 A 1 10 1 00 10 90 V DD = 80 V 50 V 20 V 80 70 8 60 6 50 V GS 40 4 30 20 2 V DS 10 0 1 0.1 1 10 0 0 100 10 30 40 50 60 70 REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT SOURCE TO DRAIN DIODE FORWARD VOLTAGE VGS = 0 V Pulsed 10 1 0.1 100 di/dt = 100 A/µs V GS = 0 V trr - Reverse Recovery Time - ns 100 20 QG - Gate Charge - nC ID - Drain Current - A IF - Diode Forward Current - A 1 VDS - Drain to Source Voltage - V 0.01 10 0 0.5 1 1.5 VF(S-D) - Source to Drain Voltage - V Data Sheet G16410EJ1V0DS 0.1 1 10 100 IF - Diode Forward Current - A 5 VGS - Gate to Source Voltage - V 50 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ µ PA1744TP µ PA1744TP SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD 100 V D D = 50 V R G =25 Ω V G S = 20 → 0 V Energy Derating Factor - % IAS - Single Avalanche Current - A 100 SINGLE AVALANCHE ENERGY DERATING FACTOR I AS = 10 A 10 E AS = 10 m J 1 0.001 80 60 40 20 0 0.01 0.1 1 10 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - °C L - Inductive Load - mH 6 V DD = 50 V R G = 25 Ω V G S = 20 → 0 V I AS ≤ 10 A Data Sheet G16410EJ1V0DS µ PA1744TP • The information in this document is current as of March, 2003. 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