ETC CS8151C/D

CS8151C
5.0 V, 100 mA Low Dropout
Linear Regulator
with Watchdog, RESET,
and Wake Up
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DIP–8
N SUFFIX
CASE 626
8
1
PIN CONNECTIONS AND
MARKING DIAGRAM
8
1
VIN
WDI
Wake Up
RESET
A
WL, L
YY, Y
WW, W
VOUT
CS8151C
AWL
YYWW
The CS8151C is a precision 5.0 V, 100 mA micro–power voltage
regulator with very low quiescent current (400 µA typical at 200 µA
load). The 5.0 V output is accurate within ±1.0% and supplies 100 mA
of load current with a typical dropout voltage of 400 mV.
Microprocessor control logic includes Watchdog, Wake Up and
RESET. This unique combination of low quiescent current and full
microprocessor control makes the CS8151C ideal for use in battery
operated, microprocessor controlled equipment.
The CS8151C Wake Up function brings the microprocessor out of
Sleep mode. The microprocessor in turn, signals its Wake Up status
back to the CS8151C by issuing a Watchdog signal.
The Watchdog logic function monitors an input signal (WDI) from
the microprocessor. The CS8151C responds to the falling edge of the
Watchdog signal which it expects at least once during each wake–up
period. When the correct Watchdog signal is received, a falling edge is
issued on the wake–up signal line.
RESET is independent of VIN and operates correctly to an output
voltage as low as 1.0 V. A RESET signal is issued in any of three
situations. During power up the RESET is held low until the output
voltage is in regulation. During operation if the output voltage shifts
below the regulation limits, the RESET toggles low and remains low
until proper output voltage regulation is restored. And finally, a
RESET signal is issued if the regulator does not receive a Watchdog
signal within the Wake Up period.
The RESET pulse width, Wake Up signal frequency, and Wake Up
delay time are all set by one external capacitor CDelay.
The regulator is protected against short circuit, over voltage, and
thermal runaway conditions. The device can withstand 74 volt peak
transients, making it suitable for use in automotive environments.
GND
NC
Delay
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
CS8151CGN8
DIP–8
50 Units/Rail
Features
• 5.0 V ± 1.0%/100 mA Output Voltage
• Micropower Compatible Control Functions
– Wake Up
– Watchdog
– RESET
• Low Dropout Voltage: 400 mV @ 100 mA
• Low Sleep Mode Quiescent Current (400 µA Typ)
• Protection Features
– Thermal Shutdown
– Short Circuit
– 74 V Peak Transient Capability
– Reverse Transient (–50 V)
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 3
1
Publication Order Number:
CS8151C/D
CS8151C
VOUT
VIN
Current Source
(Circuit Bias)
Delay
Overvoltage
Shutdown
VOUT
Current
Limit
Sense
Timing
Circuit
Wake Up
Circuit
+ –
Watchdog
Circuit
WDI
Wake Up
Sense
Error
Amplifier
Thermal
Shutdown
Falling Edge
Detector
Bandgap
Reference
VOUT
RESET
RESET
Circuit
GND
Figure 1. Block Diagram
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2
CS8151C
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Power Dissipation
Internally Limited
–
Output Current (VOUT, RESET, Wake Up)
Internally Limited
–
Reverse Battery
–15
V
Peak Transient Voltage (60 V Load Dump @ VIN = 14 V)
+74
V
Maximum Negative Transient (t < 2.0 ms)
–50
V
ESD Susceptibility (Human Body Model)
2.0
kV
ESD Susceptibility (Machine Model)
200
V
Logic Inputs/Outputs
–0.3 to +6.0
V
Storage Temperature Range
–55 to +150
°C
260 peak
°C
Lead Temperature Soldering
Wave Solder (through hole styles only) Note 1.
1. 10 seconds max.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ 70°C, 0°C ≤ TJ ≤ 125°C, 6.0 V ≤ VIN ≤ 26 V,
100 µA ≤ IOUT ≤ 100 mA, C2 = 47 µF (ESR < 8.0 Ω), CDelay = 0.1 µF; unless otherwise specified.)
Test Conditions
Min
Typ
Max
Unit
Output Voltage, VOUT
9.0 V < VIN < 16 V
6.0 V < VIN < 26 V, 0 < IOUT < 100 mA
4.95
4.90
5.0
5.0
5.05
5.10
V
V
Dropout Voltage (VIN – VOUT)
IOUT = 100 mA
IOUT = 100 µA
–
–
400
100
600
150
mV
mV
Load Regulation
VIN = 14 V, 100 µA < IOUT < 100 mA
–
10
50
mV
Line Regulation
IOUT = 1.0 mA, 6.0 V < VIN < 26 V
–
10
50
mV
Ripple Rejection
7.0 V < VIN < 17 V @ f = 120 Hz,
IOUT = 100 mA
60
75
–
dB
Current Limit
VOUT = 4.5 V
100
250
–
mA
150
180
210
°C
Characteristic
Output Section
Thermal Shutdown
–
Overvoltage Shutdown
VOUT < 1.0 V
50
56
62
V
Quiescent Current
IOUT = 200 µA (Sleep)
IOUT = 50 mA
IOUT = 100 mA (Wake Up)
–
–
–
0.4
4.0
12
0.75
–
20
mA
mA
mA
Reverse Current
VOUT = 5.0 V, VIN = 0 V
–
1.0
1.5
mA
RESET
Threshold High (RTH)
RTH VOUT Increasing
VOUT – 0.3
–
VOUT – 0.04
V
Threshold Low (RTL)
RTL VOUT Decreasing
4.5
4.7
4.91
V
Hysteresis
RTH – RTL
150
200
250
mV
Output Low
1.0 V < VOUT RTL, IOUT = 25 µA
–
0.2
0.8
V
Output High
IOUT = 25 µA, VOUT > RTH
3.8
4.2
5.1
V
Current Limit
RESET = 0 V, VOUT > VRTH (Sourcing)
RESET = 5.0 V, VOUT > 1.0 V (Sinking)
0.025
0.1
0.5
12
1.30
80
mA
mA
Delay Time
POR Mode
3.0
5.0
7.0
ms
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3
CS8151C
ELECTRICAL CHARACTERISTICS (continued) (0°C ≤ TA ≤ 70°C, 0°C ≤ TJ ≤ 125°C, 6.0 V ≤ VIN ≤ 26 V,
100 µA ≤ IOUT ≤ 100 mA, C2 = 47 µF (ESR < 8.0 Ω), CDelay = 0.1 µF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Threshold High
–
–
1.4
2.0
V
Threshold Low
–
0.8
1.3
–
V
Hysteresis
–
25
100
–
mV
Watchdog Input
Input Current
0 < WDI < 6.0 V
–10
0
+10
µA
Pulse Width
50% WDI Falling Edge to
50% WDI Rising Edge and
50% WDI Rising Edge to
50% WDI Falling Edge
(see Figures 2, 3, and 4)
5.0
–
–
µs
Wake Up Period
See Figure 2.
30
40
50
ms
Wake Up Duty Cycle Nominal
See Figure 4.
40
50
60
%
RESET High to
Wake Up Rising Delay Time
50% RESET Rising Edge to
50% Wake Up Edge
(see Figures 2, 3, and 4)
15
20
25
ms
Wake Up Response to
Watchdog Input
50% WDI Falling Edge to
50% Wake Up Falling Edge
–
2.0
10
µs
Wake Up Response to RESET
50% RESET Falling Edge to
50% Wake Up Falling Edge,
VOUT = 5.0 V → 4.5 V
–
2.0
10
µs
Output Low
IOUT = 25 µA (Sinking)
–
0.2
0.8
V
Output High
IOUT = 25 µA (Sourcing)
3.8
4.2
5.1
V
Current Limit
Wake Up = 5.0 V
Wake Up = 0 V
0.025
0.5
1.0
–
7.0
3.5
mA
mA
Wake Up Output
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
DIP–8
PIN SYMBOL
1
VIN
Supply voltage to the IC.
2
WDI
CMOS/TTL compatible input lead. The Watchdog function monitors the falling edge of the
incoming signal.
3
Wake Up
CMOS/TTL compatible output consisting of a continuously generated signal used to Wake
Up the microprocessor from sleep mode.
4
RESET
CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by more than
6.0% from nominal, or during the absence of a correct watchdog signal.
5
Delay
6
NC
7
GND
Ground connection.
8
VOUT
Regulated output voltage 5.0 V ± 2%.
FUNCTION
Input lead from timing capacitor for RESET and Wake Up signal.
No connection.
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CS8151C
TIMING DIAGRAMS
VIN
RESET
Wake Up
Duty Cycle = 50%
Wake Up
WDI
VOUT
POR
RESET High
to Wake Up
Delay Time
Power Up
Sleep Mode
Normal Operation with Varying Watchdog Signal
Figure 2. Power Up, Sleep Mode and Normal Operation
VIN
RESET Delay Time
RESET
Wake Up
WDI
VOUT
POR
RESET High
to Wake Up
Delay Time
Wake Up
Period
RESET High
to Wake Up
Delay Time
Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued
RESET
Wake Up Period
Wake Up
WDI
RTL
VOUT
Watchdog
Pulse Width
Power Down
POR
POR
Watchdog Pulse Width
Figure 4. Power Down and Restart Sequence
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CS8151C
DEFINITION OF TERMS
techniques such that the average chip temperature is not
significantly affected.
Load Regulation: The change in output voltage for a
change in load current at constant chip temperature.
Quiescent Current: The part of the positive input current
that does not contribute to the positive load current. The
regulator ground lead current.
Ripple Rejection: The ratio of the peak–to–peak input
ripple voltage to the peak–to–peak output ripple voltage.
Current Limit: Peak current that can be delivered to the
output.
Dropout Voltage: The input–output voltage differential
at which the circuit ceases to regulate against further
reduction in input voltage. Measured when the output
voltage has dropped 100mV from the nominal value
obtained at 14V input, dropout voltage is dependent upon
load current and junction temperature.
Input Voltage: The DC voltage applied to the input
terminals with respect to ground.
Line Regulation: The change in output voltage for a
change in the input voltage. The measurement is made
under conditions of low dissipation or by using pulse
CIRCUIT DESCRIPTION
Functional Description
The first falling edge of the watchdog signal causes the
Wake Up to go low within 2.0 µs (typ) and remain low until
the next Wake Up cycle (see Figure 5). Other watchdog
pulses received within the same cycle are ignored (Figures
2, 3, and 4).
During power up, RESET is held low until the output
voltage is in regulation. During operation, if the output
voltage shifts below the regulation limits, the RESET
toggles low and remains low until proper output voltage
regulation is restored. After the RESET delay, RESET
returns high.
The Watchdog circuitry continuously monitors the input
watchdog signal (WDI) from the microprocessor. The
absence of a falling edge on the Watchdog input during one
Wake Up cycle will cause a RESET pulse to occur at the end
of the Wake Up cycle (see Figure 3).
The Wake Up output is pulled low during a RESET
regardless of the cause of the RESET. After the RESET
returns high, the Wake Up cycle begins again (see Figure 3).
The RESET pulse width, Wake Up signal frequency and
RESET high to Wake Up delay time are all set by one
external capacitor CDelay.
Wake Up Period = (4 × 105)CDelay
RESET Delay Time = (5 × 104)CDelay
RESET High to Wake Up Delay Time = (2 × 105)CDelay
Capacitor temperature coefficient and tolerance as well as
the tolerance of the CS8151C must be taken into account in
order to get the correct system tolerance for each parameter.
To reduce the drain on the battery a system can go into a
low current consumption mode when ever its not performing
a main routine. The Wake Up signal is generated
continuously and is used to interrupt a microcontroller that
is in sleep mode. The nominal output is a 5.0 volt square
wave with a duty cycle of 50% at a frequency that is
determined by a timing capacitor, CDelay.
When the microprocessor receives a rising edge from the
Wake Up output, it must issue a watchdog pulse and check
its inputs to decide if it should resume normal operations or
remain in the sleep mode.
Wake Up
WDI
Wake Up
Response
to WDI
Figure 5. Wake Up Response to WDI
RESET
Wake Up
Wake Up
Response
to RESET
Figure 6. Wake Up Response to RESET (Low Voltage)
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CS8151C
APPLICATION NOTES
Output Stage Protection
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (–25°C to –40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provide this information.
The value for the output capacitor C2 shown in the test and
applications circuit should work for most applications,
however it is not necessarily the optimized solution.
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (see Figure 7).
If the input voltage rises above the overvoltage shutdown
threshold (e.g. load dump), the output shuts down. This
response protects the internal circuitry and enables the IC to
survive unexpected voltage transients.
Should the junction temperature of the power device
exceed 180°C (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
> 50 V
VIN
VOUT
IOUT
Load
Dump
Short
Circuit
Thermal
Shutdown
Figure 7. Typical Circuit Waveforms for Output
Stage Protection
Stability Considerations
The output or compensation capacitor C2 (see Figure 8)
helps determine three main characteristics of a linear
regulator: start–up delay, load transient response and loop
stability.
VIN
VOUT
C1*
0.1 µF
CS8151C
RRST
C2**
10 µF
RESET
*C1 required if regulator is located far from the power
supply filter.
**C2 required for stability.
Figure 8. Test and Application Circuit Showing
Output Compensation
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CS8151C
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ±20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
IQ
Figure 9. Single Output Regulator with Key
Performance Parameters Labeled
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
(1)
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RΘJA can be calculated:
Heat Sinks
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RΘJA:
RJA RJC RCS RSA
The value of RΘJA can then be compared with those in the
package section of the data sheet. Those packages with
RΘJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Battery
VOUT
C1
VCC
C2
Microprocessor
CS8151C
WDI
CDelay
RESET
I/O
RESET
CDelay
GND
(3)
where:
RΘJC = the junction–to–case thermal resistance,
RΘCS = the case–to–heatsink thermal resistance, and
RΘSA = the heatsink–to–ambient thermal resistance.
RΘJC appears in the package section of the data sheet. Like
RΘJA, it too is a function of package type. RΘCS and RΘSA
are functions of the package type, heatsink and the interface
between them. These values appear in heatsink data sheets
of heatsink manufacturers.
(2)
VIN
VOUT
} Control
Features
The maximum power dissipation for a single output
regulator (Figure 9) is:
RJA 150°C TA
PD
SMART
REGULATOR
VIN
Calculating Power Dissipation
In a Single Output Linear Regulator
PD(max) (VIN(max) VOUT(min))IOUT(max)
VIN(max)IQ
IOUT
IIN
Wake Up
I/O
Figure 10. Application Diagram
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CS8151C
PACKAGE DIMENSIONS
DIP–8
N SUFFIX
CASE 626–05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
PACKAGE THERMAL DATA
DIP–8
Unit
RΘJC
Typical
52
°C/W
RΘJA
Typical
100
°C/W
Parameter
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MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
CS8151C
Notes
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CS8151C
Notes
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CS8151C
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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CS8151C/D