CTLDM7002A-M621 SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CTLDM7002A-M621 is a Silicon N-Channel Enhancement-mode MOSFET in a small, thermally efficient, TLM™ 2x1mm package. MARKING CODE: CP TLM621 CASE FEATURES: • Load/Power Switches • Power Supply Converter Circuits • Battery Powered Portable Equipment • • • • • • MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Drain-Gate Voltage Gate-Source Voltage Continuous Drain Current Continuous Source Current (Body Diode) Maximum Pulsed Drain Current Maximum Pulsed Source Current Power Dissipation (Note 1) Operating and Storage Junction Temperature Thermal Resistance (Note 1) SYMBOL VDS VDG VGS ID IS IDM ISM PD TJ, Tstg ΘJA • Device is Halogen Free by design APPLICATIONS: Low rDS(ON) Low VDS(ON) Low Threshold Voltage Fast Switching Logic Level Compatible Small TLM™ 2x1mm Package ELECTRICAL CHARACTERISTICS: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN IGSSF, IGSSR IDSS VGS=20V, VDS=0 VDS=60V, VGS=0 IDSS ID(ON) VDS=60V, VGS=0, TJ=125°C VGS=10V, VDS=10V BVDSS VGS(th) VGS=0, ID=10μA VDS=VGS, ID=250μA VGS=10V, ID=500mA VDS(ON) VDS(ON) VSD 60 60 40 280 280 1.5 1.5 0.9 -65 to +150 139 UNITS V V V mA mA A A W °C °C/W MAX UNITS 100 nA 1.0 μA 500 500 60 1.0 VGS=5.0V, ID=50mA VGS=0, IS=400mA μA mA V 2.5 V 1.0 V 0.15 V 1.2 V Notes: (1) FR-4 Epoxy PCB with copper mounting pad area of 33mm2. R2 (17-February 2010) CTLDM7002A-M621 SURFACE MOUNT N-CHANNEL ENHANCEMENT-MODE SILICON MOSFET ELECTRICAL CHARACTERISTICS - Continued: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX rDS(ON) VGS=10V, ID=500mA 2.0 rDS(ON) VGS=10V, ID=500mA, TJ=125°C 3.5 rDS(ON) rDS(ON) gFS Crss Ciss Coss ton, toff VGS=5.0V, ID=50mA VGS=5.0V, ID=50mA, TJ=125°C VDS=10V, ID=200mA VDS=25V, VGS=0, f=1.0MHz UNITS Ω Ω 3.0 Ω 5.0 Ω 80 mS 5.0 pF VDS=25V, VGS=0, f=1.0MHz VDS=25V, VGS=0, f=1.0MHz VDD=30V, VGS=10V, ID=200mA, 50 pF 15 pF RG=25Ω, RL=150Ω 20 ns TLM621 CASE - MECHANICAL OUTLINE SUGGESTED MOUNTING PADS (Dimensions in mm) R0 PIN CONFIGURATION *Exposed pad P connects pins 1, 2, 5, and 6 LEAD CODE: 1) Drain 2) Drain 3) Gate 4) Source 5) Drain 6) Drain MARKING CODE: CP R2 (17-February 2010) w w w. c e n t r a l s e m i . c o m