CXD2408AR Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2408AR is an IC developed to generate the timing pulses required by the Progressive Scan CCD image sensors as well as signal processing circuits. Features • EIA support • Electronic shutter function • Random trigger shutter function • Sync signal generator • Supports external synchronization • Supports non-interlaced operation • Base oscillation 1560fh (24.5454MHz) 64 pin LQFP (Plastic) Absolute Maximum Ratings V • Supply voltage VDD VSS – 0.5 to +7.0 • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Applications Progressive Scan CCD cameras Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 Structure Silicon gate CMOS IC • Operating temperature Topr –20 to +75 V °C Applicable CCD Image Sensors ICX074AK, ICX074AL Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96402A68 CXD2408AR CL CLD O2FH FLD BLK SYNC VDO HDO HDI VDI EXT REVH REND RDM OCTL RM XCPDM XCPOB PBLK ID WEN Block Diagram 47 46 45 44 43 42 41 39 38 37 36 59 58 61 60 57 54 53 51 50 49 RG 11 XH1 13 XSHP 28 62 HRI TG GATE XH2 14 63 VRI OUTPUT CONTROL V-CONTROL PULSE GENERATOR XSHD 29 H-DECODER V-DECODER 1/390 1/525 XRS 30 XV1 26 20 TEST1 XV2 25 21 TEST2 XV3 22 31 XSG 27 TEST3 32 TEST4 XHHG1A 15 1/2 XHHG1B 16 COUNTER 48 TEST8 XHHG2 17 35 TEST7 TEST CIRCUIT 34 TEST6 DECODE XVOG 18 33 TEST5 XVHOLD 19 52 NC 9 12 23 24 40 55 56 SMD1 SMD2 XSUB VSS VDD VSS 24.5MHz –2– VDD 7 VSS 6 ED2 5 ED1 VSS 4 ED0 8 10 3 PS 2 TRIG 1 OSCI CKI 64 OSCO GATE CXD2408AR 41 40 39 38 37 36 35 TEST5 TEST6 TEST7 EXT 43 42 REND XCPDM 44 REVH XCPOB 45 OCTL PBLK 46 VSS ID 47 RDM WEN 48 RM TEST8 Pin Configuration 34 33 CL 49 32 TEST4 CLD 50 31 TEST3 O2FH 51 30 XRS NC 52 29 XSHD FLD 53 28 XSHP BLK 54 27 XSG VSS 55 26 XV1 VDD 56 25 XV2 SYNC 57 24 VDD HDI 58 23 VSS VDI 59 22 XV3 HDO 60 21 TEST2 VDO 61 20 TEST1 HRI 62 19 XVHOLD VRI 63 18 XVOG CKI 64 17 XHHG2 8 9 10 11 12 13 14 15 16 SMD2 TRIG RG XSUB XH1 XH2 XHHG1A XHHG1B 7 VSS PS 6 SMD1 OSCI 4 5 ED2 3 ED1 2 ED0 1 OSCO CXD2408AR (G/A) –3– CXD2408AR Pin Description Pin No. Symbol I/O Description 1 OSCO O Inverter output for oscillation. 2 OSCI I Inverter input for oscillation. 3 PS I Switching for electronic shutter speed input method. (With pull-down resistor) Low: Parallel input, High: Serial input 4 ED0 I Shutter speed setting. Strobe input for serial mode. (With pull-up resistor) 5 ED1 I Shutter speed setting. Clock input for serial mode. (With pull-up resistor) 6 ED2 I Shutter speed setting. Data input for serial mode. (With pull-up resistor) 7 SMD1 I Shutter mode setting. (With pull-up resistor) 8 Vss 9 SMD2 I Shutter mode setting. (With pull-up resistor) 10 TRIG I Trigger input for random trigger shutter. 11 RG O Reset gate pulse output. 12 XSUB O CCD discharge pulse output. 13 XH1 O Clock output for CCD horizontal register drive. 14 XH2 O Clock output for CCD horizontal register drive. 15 XHHG1A O Clock output for transfer between CCD horizontal registers. 16 XHHG1B O Clock output for transfer between CCD horizontal registers. 17 XHHG2 O Clock output for transfer between CCD horizontal registers. 18 XVOG O Clock output for transfer from CCD vertical register to CCD horizontal register. 19 XVHOLD O Clock output for adjusting timing of transfer to CCD horizontal register. 20 TEST1 O Test output. Normally open. 21 TEST2 O Test output. Normally open. 22 XV3 O Clock output for CCD vertical register drive. 23 Vss — GND 24 VDD — Power supply. 25 XV2 O Clock output for CCD vertical register drive. 26 XV1 O Clock output for CCD vertical register drive. 27 XSG O CCD sensor charge readout pulse output. 28 XSHP O Precharge level sample-and-hold pulse. 29 XSHD O Data sample-and-hold pulse. 30 XRS O Sample-and-hold pulse. 31 TEST3 O Test output. Normally open. 32 TEST4 O Test output. Normally open. 33 TEST5 O Test output. Normally open. 34 TEST6 O Test output. Normally open. 35 TEST7 I Test input. Set at Low in normal operation. (With pull-down resistor) — GND –4– CXD2408AR Pin No. Symbol I/O Description 36 EXT I Internal synchronization/external synchronization switching. (With pull-down resistor) Low: Internal synchronization, High: External synchronization 37 REND I Normal reset/direct reset switching. (With pull-down resistor) Low: Normal reset, High: Direct reset 38 REVH I V reset/HV reset switching. (With pull-down resistor) Low: V reset, High: HV reset 39 OCTL I O2FH output control. (With pull-down resistor) Low: No output, High: Output 40 Vss 41 RDM I Normal operation/random trigger shutter switching. (With pull-down resistor) Low: Normal operation, High: Random trigger shutter 42 RM I Switching for output mode. (With pull-down resistor) Low: Non-interlaced, High: Interlaced 43 XCPDM O Clamp pulse output. 44 XCPOB O Clamp pulse output. 45 PBLK O Blanking cleaning pulse output. 46 ID O Line identification output. 47 WEN O Write enable output. 48 TEST8 I Test input. (With pull-down resistor) 49 CL O fck clock output. (0°) 50 CLD O fck clock output. (180°) 51 O2FH O 2 fH output. 52 NC — 53 FLD O Field pulse output. 54 BLK O Composite blanking output. 55 Vss — GND 56 VDD — Power supply. 57 SYNC O Composite sync output. 58 HDI I Horizontal sync signal input. 59 VDI I Vertical sync signal input. 60 HDO O Horizontal sync signal output. 61 VDO O Vertical sync signal output. 62 HRI I Horizontal reset signal input. 63 VRI I Vertical reset signal input. 64 CKI I 2 fck clock input. — GND –5– CXD2408AR Electrical Characteristics DC Characteristics Item (VDD = 4.75 to 5.25V, Topr = –20 to +75°C) Symbol Conditions Min. Typ. Max. Unit 5.0 5.25 V Supply voltage VDD 4.75 Input voltage 1 (Input pins other than those below) VIH1 0.7VDD Input voltage 2 (Pins 7, 9, 10, 58, 59, 62, 63, and 64) VIH2 Output voltage 1 (Output pins other than those below) VOH1 IOH = –2mA VOL1 IOL = 4mA Output voltage 2 (Pins 28, 29, 30, 31, 32, 33, 34, 49 and 50) VOH2 IOH = –4mA VOL2 IOL = 8mA Output voltage 3 (Pins 11, 13, and 14) VOH3 IOH = –12mA VOL3 IOL = 12mA VOH4 IOH = –12mA VOL4 IOL = 12mA Feedback resistor RFB VIN = Vss or VDD Pull-up resistor RPU VIL = 0V 50k Ω Pull-down resistor RPD VIN = VDD 50k Ω Current consumption IDD VDD = 5V ICX074AL in normal operating state 35 mA Output voltage 4 (Pin 1) VIL1 0.3VDD 0.7VDD 0.3VDD –0.8 0.4 –0.8 V V 0.4 VDD – 0.8 VDD/2 250k Typ. Max. Unit Input pin capacitance CIN — — 9 pF Output pin capacitance COUT — — 11 pF V V 0.4 Min. –6– V V (VDD = VI = 0V, fM = 1MHz) Symbol V V VIL2 I/O Pin Capacitances Item V V V 1M VDD/2 V 2.5M Ω CXD2408AR AC Characteristics 1) Phase characteristics of XH1, RG, XSHP, XSHD, XRS, CL, and CLD tCK CK Vpp/2 tpd1 XH1 tpd2 0.7VDD 0.3VDD tpd3 tpd4 0.7VDD RG 0.3VDD tpd6 tpd5 XSHP 0.7VDD 0.3VDD tpd8 tpd7 XSHD 0.7VDD 0.3VDD tpd10 tpd9 0.7VDD XRS 0.3VDD tpd11 tpd12 CL 0.7VDD 0.3VDD tpd14 tpd13 0.7VDD CLD 0.3VDD (VDD = 5.0V, Topr = 25°C, Load capacity of CL and CLD = 30pF, Load capacity of XH1, XSHP, XSHD, XRS, and RG = 10pF) Definition Symbol Typ. Unit tCK CK cycle 41 ns tpd1 tpd2 tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 XH1 rising delay, activated by the falling edge of CK 28 ns XH1 falling delay, activated by the falling edge of CK 29 ns RG falling delay, activated by the rising edge of CK 27 ns RG rising delay, activated by the falling edge of CK 33 ns XSHP falling delay, activated by the rising edge of CK 36 ns XSHP rising delay, activated by the falling edge of CK 30 ns XSHD falling delay, activated by the rising edge of CK 36 ns XSHD rising delay, activated by the falling edge of CK 29 ns XRS falling delay, activated by the falling edge of CK 34 ns XRS rising delay, activated by the rising edge of CK 28 ns CL falling delay, activated by the rising edge of CK 15 ns CL rising delay, activated by the rising edge of CK 17 ns tpd13 tpd14 CLD falling delay, activated by the rising edge of CK 30 ns CLD rising delay, activated by the falling edge of CK 33 ns –7– CXD2408AR Waveform Characteristics of XH1 and RG 0.9VDD XH1 0.1VDD tfH1 trH1 0.9VDD RG 0.1VDD trRG tfRG (VDD = 5.0V, Topr = 25°C, Load capacity of XH1 = 10pF, Load capacity of RG = 10pF) Symbol trH1 tfH1 trRG tfRG Definition Typ. Unit XH1 rise time 2 ns XH1 fall time 2 ns RG rise time 2 ns RG fall time 2 ns –8– CXD2408AR • In the normal reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 2 1 HDO tp1 tp2 tp3 fH tp4 VDO fH tp5 L: ODD H: EVEN 1 ODD 259H VDO EVEN 2 259H Symbol tp1 tp2 tp3 tp4 tp5 Definition Specified value Unit Range of resetting to ODD 21.9 µs Range of resetting to EVEN 31.6 µs Range of resetting to ODD 9.7 µs Prohibited area 200 ns Prohibited area 200 ns –9– CXD2408AR • In the direct reset mode, the signal output is reset to ODD or EVEN field depending on the input timing of the vertical reset signal as shown in the figure below. Field identification VRI 1 2 HDO tp2 tp1 tp3 fH tp4 tp5 fH L: ODD H: EVEN VDO 1 ODD VDO 2 EVEN Symbol tp1 tp2 tp3∗ tp4 tp5 Definition Specified value Unit Range of resetting to ODD 21.9 µs Range of resetting to EVEN 31.6 µs Range of resetting to ODD — µs Prohibited area 200 ns Prohibited area 200 ns ∗ In the direct reset mode, the cycle of HD can be arbitrary. Therefore, tp3 is not specified. – 10 – CXD2408AR Description of Operation 1. Mode Control Symbol Pin No. L H Remarks RM 42 1/30s non-interlaced 1/60s interlaced RDM 41 Normal operation Random trigger shutter PS 3 Parallel Serial EXT 36 Internal synchronization External synchronization REND 37 Normal reset Direct reset REVH 38 V reset HV reset Electronic shutter speed input method 2. Mode Relationships RM EXT RDM L H 1/30s non-interlaced 1/60s interlaced L H L H Internal synchronization External synchronization Internal synchronization External synchronization L H Normal operation Random trigger shutter REND Normal operation Direct reset REVH L H Normal operation Random trigger shutter Normal operation L H Normal reset Direct reset L H L H V reset HV reset V reset HV reset : Disabled – 11 – CXD2408AR 3. Electronic Shutter <Shutter Modes> SMD1 SMD2 L L L H H L H H Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/60 Low-speed shutter: Shutter speed slower than 1/60 No shutter operation <Shutter Mode and Speed Setting Method> PS = Low : Parallel input; set by ED0 to ED2, SMD1, and SMD2. PS = High : Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin. 3-1. Parallel input Shutter Speed Compatibility Chart Mode PS SMD1 SMD2 ED0 ED1 ED2 OFF L H H X X X Shutter speed Shutter off∗ Flickerless L L L X X X 1/100 (s) L L H H H H 1/60 (s) L L H L H H 1/125 (s) L L H H L H 1/250 (s) L L H L L H 1/500 (s) L L H H H L 1/1000 (s) L L H L H L 1/2000 (s) L L H H L L 1/4000 (s) L L H L L L 1/10000 (s) L H L H H H 2FLD L H L L H H 4FLD L H L H L H 6FLD L H L L L H 8FLD L H L H H L 10FLD L H L L H L 12FLD L H L H L L 14FLD L H L L L L 16FLD High-speed shutter Low-speed shutter ∗ Shutter speed is 1/30s in 1/30s mode, and 1/60s in 1/60s mode. – 12 – CXD2408AR 3-2. Serial input • For serial input (PS = High), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) D0 ED2 (DATA) D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within at the rise of ED0. AC Characteristics ED2 ts2 th2 ED1 tw1 ts0 ts1 ED0 tw0 Definition Symbol Min. Max. ts2 th2 ts1 tw0 ts0 ED2 set-up time, activated by the falling edge of ED1 20ns — ED2 hold time, activated by the rising edge of ED1 20ns — ED1 rising set-up time, activated by the rising edge of ED0 20ns — ED0 pulse width 20ns 50µs ED0 rising set-up time, activated by the rising edge of ED1 20ns — tw1 ED1 pulse width (serial input) 20ns — – 13 – CXD2408AR 3-3. Shutter speed calculation formula High-speed shutter T = [26210 – (1FF16 – L16)] × 63.56 + 34.78 (µs) (∗L16 = Load value) Load value Shutter speed Calculated value 0FA16 1/10000 1/10169 0FC16 1/4000 1/4435 10016 1/2000 1/2085 10816 1/1000 1/1012 11816 1/500 1/499 13716 1/250 1/252 17616 1/125 1/125 19616 1/100 1/100 Low-speed shutter N = 2 × (1FF16 – L16) FLD However, the load value of FF16 cannot be used . Load value Shutter speed (FLD) 1FE16 2 1FD16 4 : : 10116 508 10016 510 ∗ In case of starting with serial input setting (PS = H), be sure to transfer shutter speed data in the range of specification after power is turned on, and then use it.. – 14 – CXD2408AR 4. Random Trigger Shutter The random trigger shutter is different from the conventional electronic shutter in that the exposure beginning can be freely set. The exposure period (shutter speed) can be set as with the conventional electronic shutter. In this mode, XSUB rises for each 1H, and the charge stored in the sensor is discharged. Because the V clock (XV1 to XV3) is continuously operating, any unneeded charge in the vertical CCD is eliminated. XSG pulse is stopped until the external trigger is detected. The image cannot be monitored until the external trigger is detected and the signal is read out. When an external trigger is input in this state, HD is forcibly reset when the trigger falls, and XSUB falls once to clear the charge and then halts. XV1 to XV3, XCPDM, XCPOB, and PBLK are reset with HD. From this point, exposure begins, and after the preset exposure period has passed, the XSG pulse falls, the charge is transferred from the sensor to the vertical CCD, and exposure ends. The XSG pulse falls with the time set as in conventional electronic shutters, regardless of VD. Because HD is reset, the exposure period is accurate in 1H units. The WEN pulse is generated synchronously with the XSG pulse. As the WEN pulse specifies the signal start, it can be used as the sync signal for writing image data into the frame memory. In the random trigger shutter mode, V-direction functions of a sync signal generator are halted. As a result, sync signals VD and FLD are also halted. TRIG HD reset HD XSG XSUB reset XSUB Shutter speed XV1 XV2 XV3 WEN – 15 – CXD2408AR 5. External Synchronization - Reset HD and VD are reset to synchronize with the external sync signal. Resetting is done to synchronize a plural number of camera systems whose clock frequencies are the same. There are two reset inputs: HRI and VRI. When their falling edge is detected, resetting is carried out. The CXD2408AR has two reset modes: normal reset and direct reset. Details of the reset modes are described in the following pages. In the 1/30s non-interlaced readout mode, the normal reset mode is not supported, and although the direct reset mode is supported, the field is not identified. – 16 – CXD2408AR 5-1. Normal reset In the normal reset mode, the reset signal is input for resetting, and the sync signal is output continuously from that time. Only the mode which resets both HD and VD (HV reset) is supported. When the H reset signal HRI is continuously with an H cycle, resetting is triggered at the first falling edge, and after that point no resets are triggered at edges unless HD after resetting exceeds 2bits (163ns) on the internal clock. In other words, the HRI input jitter is absorbed when it is up to 163 ns. The HRI minimum reset pulse width is 0.3µs. In the V direction, counting begins from VRI fall, and V is reset to cause VDO to fall after 262.5 – 3.5 = 259H. The VRI minimum reset pulse width is 2H. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics (Field identification). FIELD.E FIELD.O HRI HDO VRI 9H VDO 259H FIELD.O FIELD.E HRI HDO VRI 9H VDO 259H H reset 57.1 to 57.2µs (701 to 702 bit) HRI HD OUT Reset 6.3 to 6.37µs – 17 – CXD2408AR 5-2. Direct reset In the direct reset mode, when the reset signal is input for resetting, a sync signal is output, but there is no continuous output. There are two direct reset modes: one to direct reset VD only (V reset), and one to reset both HD and VD (HV reset). (However, note that even for V reset, the HRI signal is acceptable and the reset timing is the same as in normal reset mode.) In both modes, the VD reset timing is the same. When the external input V reset signal VRI fall is detected, a judgment is made as to ODD or EVEN. If ODD, V is reset to cause VDO to fall simultaneously with HD fall, and if EVEN, V is reset to cause VDO to fall simultaneously in the middle of HD. VRI requires a minimum pulse width of 2H. H direct reset detects the fall of H reset signal HRI, and resets H so that HDO falls at the next CL falling edge. The minimum HRI reset pulse width is 0.3µs. Resetting is done for ODD or EVEN field, depending on the input timing of the V reset signal. The identification timing is shown in Electrical Characteristics (Field identification). 5-2-1. V reset FIELD.E FIELD.O HRI HDO VRI 9H VDO FIELD.O FIELD.E HRI HDO VRI 9H VDO – 18 – CXD2408AR 5-2-2. HV reset (1/60s interlaced readout mode) FIELD.E FIELD.O HDO HRI 9H VDO VRI XSG ID FIELD.O FIELD.E HDO HRI 9H VDO VRI XSG ID CL HRI HDO – 19 – CXD2408AR 5-2-3. HV reset (1/30s non-interlaced readout mode) HDO HRI 9H VDO VRI XSG ID HDO HRI 9H VDO VRI XSG ID CL HRI HDO – 20 – CXD2408AR Timing Chart (1) <Vertical direction> 1/60s interlaced readout (RM = High) FLD VDO BLK 285 280 275 270 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 260 261 262 263 264 265 HDO XV1 XV2 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 21 – 1 3 5 7 1 3 5 7 9 11 13 15 2 4 6 8 2 4 6 8 10 12 14 16 493 494 1 3 5 7 1 3 5 7 9 11 13 15 494 OUT2 2 4 6 8 2 4 6 8 10 12 14 16 OUT1 493 XV3 CXD2408AR Timing Chart (2) <Vertical direction> 1/30s non-interlaced readout (RM = Low) FLD VDO BLK 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 HDO XV1 XV2 XSG XVHOLD XVOG XHHG1A XHHG1B XHHG2 PBLK XCPOB XCPDM ID WEN – 22 – 1 2 3 4 5 6 7 8 1 2 3 493 494 1 2 3 4 5 6 7 8 1 2 3 4 OUT1 493 494 XV3 – 23 – WEN ID XCPDM XCPOB PBLK XSUB XSHD XSHP RG XH2 XH1 XHHG2 13 41 40 37 35 35 35 31 30 XHHG1B 20 35 OPB (31 bits) 10 XHHG1A XVOG XVHOLD XV3 XV2 XV1 CL BLK/HD 0 47 47 52 47 53 50 56 58 59 63 59 60 65 69 65 Timing Chart (3) <Horizontal direction> 1/60s interlaced readout (RM = High) 70 72 75 77 76 71 78 77 77 78 83 80 83 89 89 90 93 93 95 95 100 101 95 101 95 100 120 105 114 115 Dummy (16 bits) 110 132 OPB (2 bits) 130 CXD2408AR – 24 – WEN ID XCPDM XCPOB PBLK XSUB XSHD XSHP RG XH2 XH1 XHHG2 13 35 35 XHHG1B 35 35 31 30 XHHG1A 20 35 OPB (31 bits) 10 XVOG XVHOLD XV3 XV2 XV1 CL BLK/HD 0 40 47 50 59 59 60 65 65 70 78 72 Timing Chart (4) <Horizontal direction> 1/30s non-interlaced readout (RM = Low) 77 80 89 93 93 95 95 89 90 100 101 100 120 105 114 115 Dummy (16 bits) 110 132 OPB (2 bits) 130 CXD2408AR CXD2408AR Timing Chart (5) <V2/V3 simultaneous readout timing> 1/60s interlaced (RM = High) HD 2.53µs (31 bits) 2.53µs (31 bits) 2.94µs (36 bits) ODD Field 42.4µs (520 bits) 16.1µs (198 bits) XV1 XV2 XV3 XSG EVEN Field XV1 XV2 XV3 XSG Timing Chart (6) <V2/V3 simultaneous readout timing> 1/30s non-interlaced (RM = Low) HD ODD Field 2.53µs (31 bits) 2.53µs (31 bits) 16.1µs (198 bits) 42.4µs (520 bits) XV1 XV2 XV3 XSG – 25 – 2.94µs (36 bits) CXD2408AR Timing Chart (7) <High-speed phase> HD CKI CL XH1 XH2 RG XSHP XSHD XRS CLD – 26 – CXD2408AR Timing Chart (8) <SG vertical direction> Field E O : ODD E : EVEN Field O HDO 9H VDO SYNC 20H BLK FLD Field E Field O HDO 9H VDO SYNC BLK 20H FLD – 27 – CXD2408AR Timing Chart (9) <SG horizontal direction> HDO 6.36µs (78 bits) 10.76µs (132 bits) BLK 1.47µs (18 bits) 4.89µs (60 bits) HSYNC EQ 2.45µs (30 bits) 4.89µs (60 bits) VSYNC 26.89µs (330 bits) VDO FLD ODD EVEN 11.82µs (145 bits) 10.14µs (124 bits) 2FH 9.86µs (121 bits) 63.56µs (780 bits) 1/2H 31.78µs (390 bits) 9.78µs (120 bits) FH 22.00µs (27 bits) – 28 – – 29 – 47p 2.2K 47p 2.2K 37 36 35 34 33 1 2 3 4 5 6 CXD2408AR 10 11 12 13 14 15 16 To MEMORY CONTROLLER Input only for random trigger shutter mode. 12p 20p 0.01 VSUB ADJ. 10/10V CXD1250M ICX074AK/AL CXD1268M CCD OUT2 CCD OUT1 21 22 14 24 15 13 21 22 14 CXA1690Q CXA1690Q DIGITAL OUT2 (10bit) CXD2311AR DIGITAL OUT1 (10bit) CXD2311AR Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 74HC04 17 64 9 18 N.C. 63 8 20 N.C. 19 61 2.2K N.C. 62 47p 7 21 N.C. 22 60 23 58 59 2.2K 24 25 56 57 26 55 47p 2.2K 2.2K 28 27 53 54 29 47p 13 24 38 31 N.C. 39 50 40 15 42 41 32 N.C. 43 30 2.2K 47p 47p 2.2K 45 44 47p 2.2K 49 46 47p 2.2K 47 N.C. N.C. 52 47p +5V 0.01 10/10V N.C. 48 N.C. N.C. 51 1000p ANALOG OUT1 ANALOG OUT2 Application Circuit (1/60s interlaced, internal synchronization, normal continuous operation) 22 22 CXD2408AR CXD2408AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 16 1 0.5 b 0.13 M + 0.2 1.5 – 0.1 0.1 + 0.08 b = 0.18 – 0.03 0.125 ± 0.04 DETAIL B : SOLDER DETAIL B : PALLADIUM 0.5 ± 0.2 0° to 10° DETAIL A b = 0.18 ± 0.03 (0.127) ( 0.18 ) + 0.05 0.127 – 0.02 0.1 ± 0.1 NOTE: Dimension "∗" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT EIAJ CODE LQFP064-P-1010 LEAD MATERIAL SOLDER/PALLADIUM PLATING 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 30 – Sony Corporation