CYPRESS CY7C1011CV33

CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
❐ Automotive-E: –40 °C to 125 °C
The CY7C1011CV33 is a high performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
131,072 words by 16 bits. This device has an automatic power
down feature that significantly reduces power consumption when
deselected.
■
Pin and function compatible with CY7C1011BV33
■
High speed
❐ tAA = 10 ns (Industrial and Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■
Low active power
❐ 360 mW (max) (Industrial and Automotive-A)
■
2.0 V data retention
■
Automatic power down when deselected
■
Independent control of upper and lower bits
■
Easy memory expansion with Chip Enable (CE) and Output
Enable (OE) features
■
Available in Pb-free 44-pin thin small outline package
(TSOP) II, 44-pin thin quad flat package (TQFP), and non
Pb-free 48-ball very fine ball grid array (VFBGA) packages
To write to the device, take CE and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins
(I/O0 through I/O7), is written into the location specified on the
address pins (A0 through A16). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A16).
To read from the device, take CE and OE LOW while forcing the
Write Enable (WE) HIGH. If BLE is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the “Truth
Table” on page 10 for a complete description of Read and Write
modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress 
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
•
BHE
WE
CE
OE
BLE
A16
A15
A14
A12
A13
A9
Cypress Semiconductor Corporation
Document Number: 38-05232 Rev. *K
A10
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 18, 2010
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CY7C1011CV33
Contents
Features ..............................................................................
Functional Description.......................................................
Logic Block Diagram..........................................................
Contents ..............................................................................
Pin Configuration ...............................................................
Selection Guide ..................................................................
Maximum Ratings...............................................................
Operating Range.................................................................
Electrical Characteristics...................................................
Capacitance ........................................................................
Thermal Resistance............................................................
Switching Characteristics..................................................
Switching Waveforms ........................................................
Document Number: 38-05232 Rev. *K
1
1
1
2
3
4
5
5
5
6
6
7
8
Truth Table........................................................................
Ordering Information .......................................................
Ordering Code Definition.............................................
Package Diagrams ...........................................................
Acronyms..........................................................................
Document History Page...................................................
Sales, Solutions, and Legal Information ........................
Worldwide Sales and Design Support.........................
Products ......................................................................
PSoC Solutions ...........................................................
10
11
11
12
14
15
16
16
16
16
Page 2 of 16
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CY7C1011CV33
Pin Configuration
Figure 1. 44-Pin TSOP II [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Figure 2. 48-Ball VFBGA Pinout [1]
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS I/O11
NC
A7
VCC
D
VCC
NC
A16
I/O4
VSS
E
I/O14 I/O13 A14
A15
I/O5
I/O6
F
I/O12
I/O3
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
A12
A11
A10
A9
OE
BHE
BLE
40
39
38
37
36
35
34
A13
A14
A15
A16
Figure 3. 44-Pin TQFP
42
41
43
44
1
8
I/O10
I/O5
9
25
I/O9
I/O6
10
24
I/O8
I/O7
11
23
NC
21
I/O4
22
I/O11
26
A8
27
A7
7
20
VSS
A5
VCC
A6
6
18
VCC
19
VSS
28
NC
29
17
5
16
4
I/O3
A4
I/O2
I/O12
A3
I/O13
30
14
31
15
3
A1
2
I/O1
A2
I/O0
I/O14
13
I/O15
32
12
33
WE
A0
1
CE
Note
1. NC pins are not connected on the die.
Document Number: 38-05232 Rev. *K
Page 3 of 16
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CY7C1011CV33
Selection Guide
Description
-10
Maximum access time
Maximum operating current
10
12
ns
100
95
mA
Automotive-A
100
Industrial
10
Automotive-A
10
Automotive-E
Document Number: 38-05232 Rev. *K
Unit
Industrial
Automotive-E
Maximum CMOS standby current
-12
mA
120
mA
10
mA
mA
15
mA
Page 4 of 16
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CY7C1011CV33
Maximum Ratings
Current into outputs (LOW) ......................................... 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Static discharge voltage............................................ >2001 V
(MIL-STD-883, method 3015)
Latch up current ...................................................... >200 mA
Operating Range
Ambient temperature with
power applied ........................................... –55 C to +125 C
Range
Supply voltage on VCC relative to GND[2] .....–0.5 V to +4.6 V
Ambient
Temperature (TA)
VCC
–40 C to +85 C
3.3 V  10%
DC voltage applied to outputs
in High Z state[2] .................................... –0.5 V to VCC+0.5 V
Industrial
Automotive-A
–40 C to +85 C
DC input voltage[2] ................................. –0.5 V to VCC+0.5 V
Automotive -E
–40 C to +125 C
Electrical Characteristics
Over the Operating Range
Parameter
Description
-10
Test Conditions
Min
-12
Max
VOH
Output HIGH voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW voltage
VCC = Min, IOL = 8.0 mA
VIH
Input HIGH voltage
2.0
VCC
+ 0.3
VIL
Input LOW voltage[2]
–0.3
IIX
Input leakage current
Industrial
Automotive-A
GND < VI < VCC
2.4
Output leakage current
GND < VI < VCC,
Output disabled
VCC operating supply current
VCC = Max, IOUT = 0 mA,
f = fMAX = 1/tRC
Automatic CE power down
current — TTL Inputs
Max VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
2.0
VCC
+ 0.3
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
A
–1
+1
–20
+20
–1
+1
–20
+20
Industrial
–1
+1
Automotive-A
–1
+1
Industrial
100
Automotive-A
100
Automatic CE power down
current — CMOS inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or
VIN < 0.3 V, f = 0
Industrial
40
Automotive-A
40
mA
40
mA
45
Industrial
10
Automotive-A
10
Automotive -E
95
A
120
Automotive -E
ISB2
V
V
Automotive -E
ISB1
Unit
0.4
Automotive -E
ICC
Max
2.4
0.4
Automotive -E
IOZ
Min
10
mA
15
Note
2. VIL (min) = –2.0 V for pulse durations of less than 20 ns.
Document Number: 38-05232 Rev. *K
Page 5 of 16
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CY7C1011CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25C, f = 1 MHz, VCC = 3.3 V
Unit
8
pF
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
JA
JC
Description
Test Conditions
Thermal resistance
(Junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Thermal resistance
(Junction to case)
TSOP II
TQFP
VFBGA
Unit
44.56
42.66
46.98
C/W
10.75
14.64
9.63
C/W
Figure 4. AC Test Loads and Waveforms [3]
10-ns devices:
12-ns devices:
Z = 50
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317
3.3 V
OUTPUT
30 pF*
OUTPUT
R2
351
30 pF*
1.5 V
(b)
(a)
High-Z characteristics:
R 317
3.0 V0 V
ALL INPUT PULSES
90%
GND
90%
10%
Rise Time: 1 V/ns
3.3 V
10%
(c)
Fall Time: 1 V/ns
OUTPUT
R2
351
5 pF
(d)
Note
3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure 4 (a). All other speeds are tested using the Thevenin load shown
in Figure 4 (b). High-Z characteristics are tested for all speeds using the test load shown in Figure 4 (d).
Document Number: 38-05232 Rev. *K
Page 6 of 16
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CY7C1011CV33
Switching Characteristics
Over the Operating Range [4]
Parameter
-10
Description
Min
-12
Max
Min
Max
Unit
Read Cycle
tpower[5]
VCC (typical) to the first access
1
1
s
tRC
Read cycle time
10
12
ns
tAA
Address to data valid
tOHA
Data hold from address change
tACE
CE LOW to data valid
tDOE
OE LOW to data valid
10
3
Industrial/Automotive-A
12
3
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[6, 7]
12
ns
5
6
ns
CE LOW to Low
tLZCE
tHZCE
CE HIGH to High
8
0
3
Z[6, 7]
tPU
CE LOW to power up
tPD
CE HIGH to power down
tDBE
Byte enable to data valid
0
5
Z[6]
Byte enable to Low Z
tHZBE
Byte disable to High Z
ns
3
5
0
Industrial/Automotive-A
ns
6
ns
6
ns
0
ns
10
12
ns
5
6
ns
Automotive-E
tLZBE
ns
10
Automotive-E
Z[6]
ns
8
0
0
5
ns
6
ns
[8, 9]
Write Cycle
tWC
Write cycle time
10
12
ns
tSCE
CE LOW to write end
7
8
ns
tAW
Address setup to write end
7
8
ns
tHA
Address hold from write end
0
0
ns
tSA
Address setup to write start
0
0
ns
tPWE
WE pulse width
7
8
ns
tSD
Data setup to write end
5
6
ns
tHD
Data hold from write end
0
0
ns
3
3
ns
WE HIGH to Low
Z[6]
tHZWE
WE LOW to High
Z[6, 7]
tBW
Byte enable to end of write
tLZWE
5
7
6
8
ns
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms [3]” on page 6. Transition is measured
500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05232 Rev. *K
Page 7 of 16
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CY7C1011CV33
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05232 Rev. *K
Page 8 of 16
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CY7C1011CV33
Switching Waveforms
(continued)
Figure 7. Write Cycle No. 1 (CE Controlled)[13, 14]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA IO
Figure 8. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
tBW
BHE, BLE
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
13. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05232 Rev. *K
Page 9 of 16
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CY7C1011CV33
Switching Waveforms
(continued)
Figure 9. Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
L
I/O0– I/O7 I/O8 – I/O15
Mode
Power
X
X
X
X
High Z
High Z
Power down
Standby (ISB)
L
H
L
L
Data Out
Data Out
Read – all bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read – lower bits only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read – upper bits only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write – all bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write – lower bits only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write – upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, outputs disabled
Active (ICC)
Document Number: 38-05232 Rev. *K
Page 10 of 16
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CY7C1011CV33
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
10
CY7C1011CV33-10ZSXA
51-85087 44-pin TSOP II (Pb-free)
Automotive-A
12
CY7C1011CV33-12AXI
51-85064 44-pin TQFP (Pb-free)
Industrial
CY7C1011CV33-12ZSXE
51-85087 44-pin TSOP II (Pb-free)
Automotive-E
CY7C1011CV33-12BVXE
51-85150 48-ball (6 x 8 x 1 mm) VFBGA
Ordering Code Definition
CY 7 C 101 1 C V33
Voltage: 3.3 V
Technology: 150 nm
Bus Width: x16
Density: 2 Mbit
Technology: CMOS
Marketing Code: 7= SRAM
Company ID : CY = Cypress
Document Number: 38-05232 Rev. *K
Page 11 of 16
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CY7C1011CV33
Package Diagrams
Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087 *C
Document Number: 38-05232 Rev. *K
Page 12 of 16
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CY7C1011CV33
Package Diagrams
(continued)
Figure 11. 44-Pin Thin Plastic Quad Flat Pack, 51-85064
51-85064 *D
Document Number: 38-05232 Rev. *K
Page 13 of 16
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CY7C1011CV33
Package Diagrams
(continued)
Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150
51-85150 *F
51-85150 *E
Acronyms
Acronym
Description
BHE
Bye High Enable
BLE
Byte Low Enable
CE
Chip Enable
CMOS
complementary metal oxide semiconductor
I/O
input/output
SRAM
static random access memory
VFBGA
very fine ball gird array
TQFP
thin quad flat pack
TSOP
thin small outline package
WE
Write Enable
Document Number: 38-05232 Rev. *K
Page 14 of 16
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CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM
Document Number: 38-05232
Orig. of
REV. ECN NO. Issue Date
Description of Change
Change
**
117132
07/31/02
HGK
New Data Sheet
*A
118057
08/19/02
HGK
Pin configuration for 48-ball FBGA correction
*B
119702
10/11/02
DFP
Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated
address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page 1
from 8 to 10 mA
*C
386106
See ECN
PCI
Added lead-free parts in Ordering Information Table
*D
498501
See ECN
NXR
Corrected typo in the Logic Block Diagram on page# 1
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current on
page# 3
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*E
522620
See ECN
VKN
Added Thermal Resistance Table
*F
1891366 See ECN VKN/AESA Added -10ZSXA part
Updated Ordering Information table
*G
2428606 See ECN VKN/PYRS Corrected typo in the 44-Pin TSOP and 48-Ball FBGA pinout
Removed Commercial parts
Removed 15 ns speed bin
Removed inactive parts from the Ordering Information table
*H
2664421
02/25/09
VKN/AESA Added Automotive-E specs for 12 ns speed
Updated Ordering Information table
*I
2898399 03/24/2010 KAO/AJU Updated Package Diagrams
*J
2950666 06/11/2010
VKN
Included “CY7C1011CV33-12BVXE” in Ordering Information
Added Contents and Acronyms
Updated Sales, Solutions, and Legal Information
Added Ordering Code Definition.
*K
3089939 11/13/2010
PRAS
Removed inactive part from Ordering Information.
Document Number: 38-05232 Rev. *K
Page 15 of 16
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CY7C1011CV33
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05232 Rev. *K
Revised November 18, 2010
Page 16 of 16
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