ICS ICS83940DYI-01T

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83940I-01 is a low skew, 1-to-18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer and a
HiPerClockS™ member of the HiPerClockS™ family of High Perfor mance Clock Solutions from ICS. The
ICS83940I-01 has two selectable clock inputs.
The PCLK, nPCLK pair can accept LVPECL, CML or SSTL
input levels. The single ended clock input accepts LVCMOS
or LVTTL input levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased
from 18 to 36 by utilizing the ability of the outputs to drive two
series terminated lines.
• 18 LVCMOS/LVTTL outputs, 23Ω typical output impedance
The ICS83940I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the
ICS83940I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC940L in single supply
applications
GND
Q5
Q4
Q3
VDDO
Q2
Q1
Q0
32 31 30 29 28 27 26 25
CLK_SEL
PCLK
nPCLK
0
18
Q0:Q17
LVCMOS_CLK
1
GND
1
24
Q6
GND
2
23
Q7
LVCMOS_CLK
3
22
Q8
CLK_SEL
4
21
VDDO
PCLK
5
20
Q9
nPCLK
6
19
Q10
VDD
7
18
Q11
VDDO
8
17
GND
ICS83940I-01
9 10 11 12 13 14 15 16
VDDO
Q12
Q13
Q14
GND
Q15
Q16
Q17
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940DYI-01
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2, 12, 17, 25
GND
Power
Type
Description
3
LVCMOS_CLK
Input
4
CLK_SEL
Input
5
PCLK
Input
6
nPCLK
Input
Inver ting differential LVPECL clock input.
VDD/2 default when left floating.
7
VDD
Power
Core supply pins.
8, 16, 21, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
VDDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Power
Output supply pins.
Output
Clock outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
Pulldown Non-inver ting differential LVPECL clock input.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
RPULLDOWN
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
ROUT
Output Impedance
C PD
Test Conditions
Minimum
Typical
Maximum
Units
4
pF
6
pF
51
18
KΩ
28
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
PCLK, nPCLK
LVCMOS_CLK
0
Selected
De-selected
1
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK_SEL
Outputs
LVCMOS_CLK
PCLK
nPCLK
Input to Output Mode
Q0:Q17
Polarity
0
—
0
1
LOW
Differential to Single Ended
Non Inver ting
0
—
1
HIGH
Differential to Single Ended
Non Inver ting
0
—
0
LOW
Single Ended to Single Ended
Non Inver ting
0
—
1
HIGH
Single Ended to Single Ended
Non Inver ting
0
—
Biased; NOTE 1
0
Biased;
NOTE 1
Biased;
NOTE 1
0
HIGH
Single Ended to Single Ended
Inver ting
0
—
Biased; NOTE 1
1
LOW
Single Ended to Single Ended
Inver ting
1
0
—
—
LOW
Single Ended to Single Ended
Non Inver ting
1
1
—
—
HIGH
Single Ended to Single Ended
Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83940DYI-01
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2
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
3.6V
Inputs, VI
-0.3V to VDD + 0.3V
Outputs, VO
-0.3V to VDDO + 0.3V
Input Current, IIN
±20mA
Storage Temperature, TSTG
-40°C to 125°C
83940DYI-01
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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3
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
2.4
VDD
V
VIH
Input High Voltage
VIL
Input Low Voltage
LVCMOS_CLK
0.8
V
V PP
PCLK, nPCLK
500
1000
mV
PCLK, nPCLK
VDD - 1.4
VDD - 0.6
V
IIN
Peak-to-Peak Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
Input Current
±200
µA
VOH
Output High Voltage
IOH = -20mA
VOL
Output Low Voltage
IOL = 20mA
VCMR
LVCMOS_CLK
2.4
V
IDD
Core Supply Current
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
0.5
V
25
mA
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40° TO 85°
Symbol
Parameter
fMAX
Output Frequency
tpLH
tpLH
tsk(o)
Propagation Delay
Propagation Delay
Output Skew;
NOTE 3, 5
Test Conditions
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
Minimum Typical
Maximum
Units
250
MHz
f ≤ 150MHz
ns
f ≤ 150MHz
ns
f > 150MHz
ns
f > 150MHz
ns
ps
LVCMOS_CLK
Measured on
rising edge @VDDO/2
f ≤ 150MHz
ns
ns
ps
tsk(pp)
Par t-to-Par t Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f ≤ 150MHz
tsk(pp)
Par t-to-Par t Skew;
NOTE 6
PCLK, nPCLK
f > 150MHz
ns
LVCMOS_CLK
f > 150MHz
ns
tsk(pp)
Par t-to-Par t Skew;
NOTE 4, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
tR, tF
Output Rise/Fall Time
1.1
ps
ps
ns
odc
Output Duty Cycle
55
%
0.5 to 2.4V
0.3
f < 134MHz
45
50
134MHz ≤ f ≤ 250MHz
40
50
60
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
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4
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
V
0.8
V
VIH
Input High Voltage
LVCMOS_CLK
VIL
Input Low Voltage
LVCMOS_CLK
V PP
PCLK, nPCLK
300
1000
mV
PCLK, nPCLK
VDD - 1.4
VDD - 0.6
V
IIN
Peak-to-Peak Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
Input Current
±200
µA
VOH
Output High Voltage
IOH = -20mA
VOL
Output Low Voltage
IOL = 20mA
VCMR
2.4
1.8
V
Core Supply Current
IDD
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
0.5
V
25
mA
Maximum
Units
250
MHz
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
fMAX
tpLH
tpLH
Test Conditions
Minimum
Output Frequency
Propagation Delay
Propagation Delay
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
Typical
f ≤ 150MHz
ns
f ≤ 150MHz
ns
f > 150MHz
ns
f > 150MHz
ns
Measured on
rising edge @VDDO/2
ps
ps
tsk(o)
Output Skew;
NOTE 3, 5
tsk(pp)
Par t-to-Par t Skew;
NOTE 6
PCLK, nPCLK
f ≤ 150MHz
ns
LVCMOS_CLK
f ≤ 150MHz
ns
tsk(pp)
Par t-to-Par t Skew;
NOTE 6
PCLK, nPCLK
f > 150MHz
ns
tsk(pp)
Par t-to-Par t Skew;
NOTE 4, 5
t R, t F
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
Output Rise/Fall Time
f > 150MHz
ns
Measured on
rising edge @VDDO/2
ps
ps
ns
0.5 to 1.8V
0.3
1.2
odc
Output Duty Cycle
f < 134MHz
45
50
55
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
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5
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
VIH
Input High Voltage
LVCMOS_CLK
VIL
LVCMOS_CLK
IIN
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
Input Current
V OH
Output High Voltage
IOH = -12mA
VOL
Output Low Voltage
IOL = 12mA
V PP
VCMR
Minimum
Typical
2
Maximum
Units
VDD
V
0.8
V
PCLK, nPCLK
300
1000
mV
PCLK, nPCLK
VDD - 1.4
VDD - 0.6
V
±200
µA
1.8
V
Core Supply Current
IDD
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
0.5
V
25
mA
Maximum
200
Units
MHz
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
fMAX
Output Frequency
tpLH
tpLH
Propagation Delay;
Propagation Delay;
Test Conditions
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK
Minimum
Typical
f ≤ 150MHz
ns
f ≤ 150MHz
ns
f > 150MHz
ns
f > 150MHz
ns
Measured on
rising edge @VDDO/2
ps
LVCMOS_CLK
tsk(o)
Output Skew;
NOTE 3, 5
tsk(pp)
Par t-to-Par t Skew;
NOTE 6
PCLK, nPCLK
f ≤ 150MHz
ns
LVCMOS_CLK
f ≤ 150MHz
ns
tsk(pp)
Par t-to-Par t Skew;
NOTE 6
PCLK, nPCLK
f > 150MHz
ns
tsk(pp)
Par t-to-Par t Skew;
NOTE 4, 5
tR, tF
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
Output Rise/Fall Time
ps
f > 150MHz
ns
Measured on
rising edge @VDDO/2
ns
ns
ns
0.5 to 1.8V
0.3
1.2
odc
Output Duty Cycle
f < 134MHz
45
55
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
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6
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.05V±5% 1.25V±5%
1.65V±5%
SCOPE
VDD,
VDDO
VDDO
Qx
LVCMOS
SCOPE
VDD
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V OUTPUT LOAD AC TEST CIRCUIT
1.25V±5%
V DD
SCOPE
VDD,
VDDO
nPCLK
V
Cross Points
PP
Qx
LVCMOS
V
CMR
PCLK
GND
GND
-1.25V±5%
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
V
V
DDO
DDO
Qx
PART 2
Qx
2
2
V
V
DDO
DDO
Qy
Qy
2
t sk(pp)
PART-TO-PART SKEW
83940DYI-01
2
t sk(o)
OUTPUT SKEW
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REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
VDDO
2
LVCMOS_CLK
nPCLK
PCLK
VDDO
2
Q0:Q17
➤
tPD
➤
PROPAGATION DELAY
2.4V
1.8V
1.8V
0.5V
0.5V
Clock
Outputs
Clock Outputs
t
t
R
F
2.4V
0.5V
0.5V
tR
tF
3.3V OUTPUT RISE/FALL TIME
2.5V OUTPUT RISE/FALL TIME
V
DDO
2
Q0:Q17
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
odc & tPERIOD
83940DYI-01
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8
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83940DYI-01
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REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination requirements.
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 2A to 2E show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R3
120
R2
50
SSTL
R4
120
Zo = 60 Ohm
Zo = 50 Ohm
PCLK
PCLK
Zo = 60 Ohm
nPCLK
Zo = 50 Ohm
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 2A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 2B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R4
125
R3
125
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R3
1K
R4
1K
PCLK
PCLK
R5
100
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerClockS
Input
R1
1K
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PCL K/n PC LK
R2
1K
FIGURE 2D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
83940DYI-01
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REV. A MARCH 1, 2004
PRELIMINARY
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Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940I-01 is: 819
83940DYI-01
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REV. A MARCH 1, 2004
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Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
0.80 BASIC
e
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
83940DYI-01
www.icst.com/products/hiperclocks.html
12
REV. A MARCH 1, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS83940DYI-01
ICS83940DI01
32 Lead LQFP
250 per tray
-40°C to 85°C
ICS83940DYI-01T
ICS83940DI01
32 Lead LQFP on Tape and Reel
1000
-40°C to 85°C
ICS83940DYI-01LF
ICS83940DI01L
250 per tray
-40°C to 85°C
ICS83940DYI-01LFT
ICS83940DI01L
32 Lead "Lead Free" LQFP
32 Lead "Lead Free" LQFP on
Tape and Reel
1000
-40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
83940DYI-01
www.icst.com/products/hiperclocks.html
13
REV. A MARCH 1, 2004