Ordering number : EN*5083 CMOS LSI LC321667BJ, BM, BT-70/80 1 MEG (65536 Words × 16 Bits) DRAM EDO Page Mode Byte Write Preliminary Overview The LC321667BJ series is a CMOS dynamic RAM operating on a single 5 V power source and having a 65536 words × 16 bits configuration. Equipped with large capacity capabilities, high speed transfer rates and low power dissipation, this series is suited for a wide variety of applications ranging from computer main memory and expansion memory to commercial equipment. Address input utilizes a multiplexed address bus which permits it to be enclosed in a compact plastic package of 40-pin SOJ. Refresh rates are within 4 ms with 256 row address (A0 to A7) selection and support Row Address Strobe (RAS)-only refresh, Column Address Strobe (CAS)-before-RAS refresh and hidden refresh settings. There are functions such as Extended Data Out (EDO) page mode, read-modify-write and byte write. • 4 ms refresh using 256 refresh cycles. • Supports RAS-only refresh, CAS-before-RAS refresh and hidden refresh. • Packages SOJ 40-pin plastic package (400 mil): LC321667BJ SOP 40-pin plastic package (525 mil): LC321667BM TSOP 44-pin plastic package (400 mil): LC321667BT • RAS access time/column address access time/CAS access time/cycle time/power dissipation. Package Dimensions unit: mm 3200-SOJ40 II [LC321667BJ] Features 65536 words × 16 bits configuration. Single 5 V ± 10% power supply. All input and output (I/O) TTL compatible. Supports EDO page mode, read-modify-write and byte write. • Supports output buffer control using early write and Output Enable (OE) control. • • • • SANYO: SOJ40 II LC321667BJ, BM, BT-70 LC321667BJ, BM, BT-80 RAS access time Parameter 70 ns 80 ns Column address access time 40 ns 45 ns CAS access time 25 ns 25 ns Cycle time Power consumption (max) During operation During standby 125 ns 135 ns 688 mW 633 mW 5.5 mW (CMOS level)/11 mW (TTL level) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 40695TH (OT) No. 5083-1/31 LC321667BJ, BM, BT-70/80 Package Dimensions Package Dimensions unit: mm unit: mm 3195-SOP40 3207-TSOP44 II [LC321667BM] [LC321667BT] SANYO: SOP40 SANYO: TSOP44 II Pin AssignmentS No. 5083-2/31 LC321667BJ, BM, BT-70/80 Block Diagram Specifications Absolute Maximum Ratings Parameter Symbol Ratings Unit Note VCC max –1.0 to +7.0 V 1 VIN –1.0 to +7.0 V 1 Output voltage VOUT –1.0 to +7.0 V 1 Operating temperature range Topr 0 to +70 °C 1 Storage temperature range Tstg –55 to +150 °C 1 mW 1 mA 1 Maximum supply voltage Input voltage Allowable power dissipation LC321667BJ, BM-70/80 LC321667BT-70/80 Output short-circuit current 800 Pd max 700 IOUT 50 Note: 1. Stresses greater than the above listed maximum values may result in damage to the device. DC Recommended Operating Ranges at Ta = 0 to +70°C min typ max Unit Note Power supply voltage Parameter Symbol VCC 4.5 5.0 5.5 V 2 Input high level voltage VIH 2.4 6.5 V 2 Input low level voltage (A0 to A7, RAS, CAS, UW, LW, OE) VIL –1.0*1 +0.8 V 2 Input low level voltage (I/O1 to I/O16) VIL –0.5*1 +0.8 V 2 Note: 2. All voltages are referenced to VSS. A bypass capacitor of about 0.1 µF should be connected between VCC and VSS of the device. *1: –2.0 V when pulse width is less than 20 ns. No. 5083-3/31 LC321667BJ, BM, BT-70/80 DC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ± 10% Parameter Symbol LC321667 BJ, BM, BT-70 Conditions min max LC321667 BJ, BM, BT-80 min Unit Note mA 3, 4, 5 max Operating current (Average current during operation) ICC1 RAS, CAS, address cycling: tRC = tRC min Standby current ICC2 RAS = CAS = VIH 2 2 mA RAS-only refresh current ICC3 RAS cycling, CAS = VIH: tRC = tRC min 125 115 mA 3, 5 EDO page mode current ICC4 RAS = VIL, CAS, address cycling: tPC = tPC min 110 100 mA 3, 4, 5 Standby current ICC5 RAS = CAS = VCC – 0.2 V CAS-before-RAS refresh current ICC6 RAS, CAS cycling: tRC = tRC min IIL 0 V ≤ VIN ≤ 6.5 V, pins other than test pin = 0 V –10 +10 Output leakage current IOL DOUT disable, 0 V ≤ VOUT ≤ 5.5 V –10 +10 Output high level voltage VOH IOUT = –2.5 mA 2.4 Output low level voltage VOL IOUT = 2.1 mA Input leakage current 125 115 1 1 mA 125 115 mA –10 +10 µA –10 +10 µA 2.4 0.4 3 V 0.4 V Note: 3. All current values are measured at minimum cycle rate. Since current flows immoderately, if cycle time is longer than shown here, current value becomes smaller. 4. ICC1 and ICC4 are dependent on output loads. Maximum values for ICC1 and ICC4 represent values with output open. 5. Address change is less than or equal to one time during RAS = VIL. Concerning ICC4, it is less than or equal to one time during 1 cycle (tPC). AC Electrical Characteristics at Ta = 0 to +70°C, VCC = 5 V ± 10% (note 6, 7 and 8) Parameter Random read or write cycle time Read-write/read-modify-write cycle time EDO page mode cycle time EDO page mode read-write/read-modify-write cycle time Symbol LC321667BJ, BM, BT-70 min max LC321667BJ, BM, BT-80 min max Unit tRC 125 135 tRWC 170 180 ns tPC 35 40 ns tPRWC 85 Note ns 90 ns RAS access time tRAC 70 80 ns 9, 14, 15 CAS access time tCAC 25 25 ns 9, 14 Column address access time tAA 40 45 ns 9, 15 CAS precharge access time tCPA 45 50 ns 9 Output low-impedance time from CAS low tCLZ ns 9 Output buffer turn-off delay time from RAS or CAS tOFF 10, 17 Rise and fall time 0 0 0 20 0 20 ns tT 2.5 50 2.5 50 ns RAS precharge time tRP 45 RAS pulse width tRAS 70 10000 80 10000 ns RAS pulse width for EDO page mode cycle only tRASP 70 100000 80 100000 ns RAS hold time tRSH 20 25 CAS hold time tCSH 60 70 CAS pulse width tCAS 20 10000 25 10000 ns RAS to CAS delay time tRCD 20 45 20 55 ns 14 RAS to column address delay time tRAD 15 30 15 35 ns 15 CAS to RAS precharge time tCRP 10 10 CAS precharge time tCP 10 10 ns Row address setup time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address setup time tASC 0 0 ns Column address hold time 45 ns ns ns ns tCAH 15 15 ns Column address hold time referenced to RAS tAR 50 55 ns Column address to RAS lead time tRAL 25 30 ns Read command setup time tRCS 0 0 ns Read command hold time referenced to CAS tRCH 0 0 ns 11 Read command hold time referenced to RAS tRRH 0 0 ns 11 Write command hold time tWCH 15 15 ns Write command hold time referenced to RAS tWCR 50 55 ns tWP 15 15 ns Write command pulse width Continued on next page. No. 5083-4/31 LC321667BJ, BM, BT-70/80 Continued from preceding page. Parameter Symbol LC321667BJ, BM, BT-70 min max LC321667BJ, BM, BT-80 min max Unit Note Write command to RAS lead time tRWL 20 20 Write command to CAS lead time tCWL 20 20 ns Data input setup time tDS 0 0 ns 12 Data input hold time tDH 15 15 ns 12 tDHR 50 55 ns Data input hold time referenced to RAS ns Refresh time tREF Write command setup time tWCS 0 0 ns 13 CAS to UW or LW delay time tCWD 45 45 ns 13 RAS to UW or LW delay time tRWD 90 100 ns 13 Column address to UW or LW delay time tAWD 60 65 ns 13 tCPWD 65 70 ns 13 CAS precharge UW or LW delay time for 70 EDO page mode cycle only 4 4 ms CAS setup time for CAS-before-RAS tCSR 10 10 ns CAS hold time for CAS-before-RAS tCHR 10 10 ns RAS precharge CAS active time tRPC 10 10 ns CAS precharge time for CAS-before-RAS counter test tCPT 40 40 ns RAS hold time referenced to OE tROH 15 15 OE access time tOEA OE delay time tOED ns 25 25 15 OE output buffer turn-off delay time tOEZ 0 OE command hold time tOEH 20 OE setup time to CAS high tOCH OE hold time from CAS high tCHO OE command pulse width tOEP 10 15 15 ns 9 ns 0 15 ns 10 20 ns 5 5 ns 16 10 10 ns 16 10 ns Data output hold time tDOH 5 WE output buffer turn-off delay time tWEZ 0 Data input to CAS delay time tDZC 0 0 ns 16 Data input to OE delay time tDZO 0 0 ns 16 Masked write setup time tMCS 0 0 ns Masked write hold time referenced to RAS tMRH 0 0 ns Masked write hold time referenced to CAS tMCH 0 0 ns 5 15 ns 0 15 ns Input/Output Capacitance at Ta = 25°C, f = 1 MHz, VCC = 5 V ± 10% Parameter Symbol min max Unit Input capacitance (A0 to A7, RAS, CAS, UW, LW, OE) CIN 7 pF Input/Output capacitance (I/O1 to I/O16) CI/O 7 pF Note Note: 6. An initial pause of 200 µs is required after power-up followed by eight RAS-only refresh cycles before proper device operation is achieved. In case of using refresh counter, a minimum of eight CAS-before-RAS refresh cycles instead of eight RAS-only refresh cycles are required. 7. Measured at tT = 2.5 ns. 8. When measuring input signal timing, VIH (min) and VIL (max) are used for reference points. In addition, rise and fall time are defined between VIH and VIL. 9. Measured using an equivalent of 50 pF and one standard TTL loads. 10. tOFF (max) and tOEZ (max) are defined as the time until output voltage can no longer be measured when output switches to a high impedance condition. 11. Operation is guaranteed if either tRRH or tRCH is satisfied. 12. These parameters are measured from the falling edge of CAS for an early-write cycle, and from the falling edge of UW and LW for a readwrite/read-modify-write cycle. 13. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters for memory in that they specify the operating mode. If tWCS ≥ tWCS (min), the cycle switches to an early-write cycle and output pins switch to high impedance throughout the cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD (min), tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min) for fast page mode cycle only, the cycle switches to a read-write/read-modify-write cycle and data output equal information in the selected cells. If neither of the above timings are satisfied, output pins are in an undefined state. 14. tRCD (max) is not a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRCD ≥ tRCD (max), access time is determined according to tCAC. 15. tRAD (max) is not a restrictive operating parameter but instead represents the point at which the access time tRAC (max) is guaranteed. If tRAD ≥ tRAD (max), access time is determined according to tAA. 16. Operation is guaranteed if either tDZC or tDZO is satisfied. 17. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. No. 5083-5/31 LC321667BJ, BM, BT-70/80 Timing Chart Read Cycle No. 5083-6/31 LC321667BJ, BM, BT-70/80 Early Write Cycle No. 5083-7/31 LC321667BJ, BM, BT-70/80 Upper Byte Early Write Cycle No. 5083-8/31 LC321667BJ, BM, BT-70/80 Lower Byte Early Write Cycle No. 5083-9/31 LC321667BJ, BM, BT-70/80 Write Cycle (OE Control) No. 5083-10/31 LC321667BJ, BM, BT-70/80 Upper Byte Write Cycle (OE Control) No. 5083-11/31 LC321667BJ, BM, BT-70/80 Lower Byte Write Cycle (OE Control) No. 5083-12/31 LC321667BJ, BM, BT-70/80 Read-Modify Write Cycle No. 5083-13/31 LC321667BJ, BM, BT-70/80 Read-Modify Upper Byte Write Cycle No. 5083-14/31 LC321667BJ, BM, BT-70/80 Read-Modify Lower Byte Write Cycle No. 5083-15/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read Cycle No. 5083-16/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Early Write Cycle No. 5083-17/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Upper Byte Early Write Cycle No. 5083-18/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Lower Byte Early Write Cycle No. 5083-19/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read-Modify-Write Cycle No. 5083-20/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read-Modify Upper Byte Write Cycle No. 5083-21/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read-Modify Lower Byte Write Cycle No. 5083-22/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read Early Write Cycle No. 5083-23/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read Upper Byte Early Write Cycle No. 5083-24/31 LC321667BJ, BM, BT-70/80 EDO Page Mode Read Lower Byte Early Write Cycle No. 5083-25/31 LC321667BJ, BM, BT-70/80 Hidden Refresh Cycle No. 5083-26/31 LC321667BJ, BM, BT-70/80 RAS-Only Refresh Cycle CAS-Before-RAS Refresh Cycle No. 5083-27/31 LC321667BJ, BM, BT-70/80 CAS-Before-RAS Refresh Counter Test Cycle (Read) No. 5083-28/31 LC321667BJ, BM, BT-70/80 CAS-Before-RAS Refresh Counter Test Cycle (Write) No. 5083-29/31 LC321667BJ, BM, BT-70/80 CAS-Before-RAS Refresh Counter Test Cycle (Read-Modify-Write) No. 5083-30/31 LC321667BJ, BM, BT-70/80 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any and all SANYO products described or contained herein fall under strategic products (including services) controlled under the Foreign Exchange and Foreign Trade Control Law of Japan, such products must not be exported without obtaining export license from the Ministry of International Trade and Industry in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 1998. Specifications and information herein are subject to change without notice. No. 5083-31/31