MP6404 Silicon N&P Channel MOS Type (Six L2-π-MOSV TOSHIBA Power MOS FET Module inOne) MP6404 Industrial Applications High Power High Speed Switching Applications 3-Phase Motor Drive and Stepping Motor Drive Applications • • • • • • • Unit: mm 4-V gate drivability Small package by full molding (SIP 12 pins) High drain power dissipation (6-device operation) : PT = 36 W (Tc = 25°C) Low drain-source ON resistance: RDS (ON) = 120 mΩ (typ.) (Nch) 160 mΩ (typ.) (Pch) High forward transfer admittance: |Yfs| = 5.0 S (typ.) (Nch) 4.0 S (typ.) (Pch) Low leakage current: IGSS = ±10 μA (max) (VGS = ±16 V) IDSS = 100 μA (max) (VDS = 60 V) Enhancement-mode: Vth = 0.8 V to 2.0 V (VDS = 10 V, ID = 1 mA) Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Nch Pch Unit JEDEC ― V JEITA ― V TOSHIBA A Weight: 3.9 g (typ.) Drain-source voltage VDSS 60 −60 V Drain-gate voltage (RGS = 20 kΩ) VDGR 60 −60 Gate-source voltage VGSS ±20 ±20 DC ID 5 −5 Pulse IDP 20 −20 Drain power dissipation (1-device operation, Ta = 25°C) PD Drain power dissipation Ta = 25°C (6-device operation) Tc = 25°C PDT Single pulse avalanche energy (Note 1) EAS 129 273 mJ Avalanche current IAR 5 −5 A Drain current 1 device operation Repetitive avalanche energy (Note 2) 6 device operation 2.2 W 4.4 W 36 EAR 0.22 EART 0.44 2-32C1K mJ Channel temperature Tch 150 °C Storage temperature range Tstg −55 to 150 °C Note 1: Condition for avalanche energy (single pulse) Nch: VDD = 25 V, starting Tch = 25°C, L = 7 mH, RG = 25 Ω, IAR = 5 A Pch: VDD = −25 V, starting Tch = 25°C, L = 14.84 mH, RG = 25 Ω, IAR = −5 A Note 2: Repetitive rating; pulse width limited by maximum channel temperature Note 3: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). This transistor is an electrostatic-sensitive device. Please handle with caution. 1 2006-10-27 MP6404 Array Configuration 5 4 2 12 6 11 3 7 8 9 10 1 Thermal Characteristics Characteristics Thermal resistance of channel to ambient Symbol Max Unit ΣRth (ch-a) 28.4 °C/W ΣRth (ch-c) 3.47 °C/W TL 260 °C (6-device operation, Ta = 25°C) Thermal resistance of channel to case (6-device operation, Tc = 25°C) Maximum lead temperature for soldering purposes (3.2 mm from case for t = 10 s) 2 2006-10-27 MP6404 Electrical Characteristics (Ta = 25°C) (Nch MOS FET) Characteristics Symbol Test Condition Min Typ. Max Unit Gate leakage current IGSS VGS = ±16 V, VDS = 0 V ― ― ±10 μA Drain cut-off current IDSS VDS = 60 V, VGS = 0 V ― ― 100 μA V (BR) DSS ID = 10 mA, VGS = 0 V 60 ― ― V Vth VDS = 10 V, ID = 1 mA 0.8 ― 2.0 V VGS = 4 V, ID = 2.5 A ― 0.21 0.32 VGS = 10 V, ID = 2.5 A ― 0.12 0.16 VDS = 10 V, ID = 2.5 A 3.0 5.0 ― S ― 370 ― pF ― 60 ― pF ― 180 ― pF ― 18 ― ― 25 ― Drain source breakdown voltage Gate threshold voltage Drain-source ON resistance RDS (ON) Forward transfer admittance |Yfs| Input capacitance Ciss Reverse transfer capacitance Crss Output capacitance Coss Rise time VDS = 10 V, VGS = 0 V, f = 1 MHz tr ID = 2.5 A 10 V ton Fall time Turn-off time Total gate charge (gate-source plus gate-drain) 50 Ω Switching time tf toff VOUT RL = 12 Ω Turn-on time VGS 0V Qgs Gate-drain (“miller”) charge Qgd ns ― 55 ― ― 170 ― ― 12 ― nC ― 8 ― nC ― 4 ― nC VDD ≈ 30 V VIN: tr, tf < 5 ns, duty ≤ 1%, tw = 10 μs Qg Gate-source charge Ω VDD ≈ 48 V, VGS = 10 V, ID = 5 A Source-Drain Diode Ratings and Characteristics (Ta = 25°C) Characteristics Symbol Test Condition Min Typ. Max Unit Continuous drain reverse current IDR ― ― ― 5 A Pulse drain reverse current IDRP ― ― ― 20 A Diode forward voltage VDSF IDR = 5 A, VGS = 0 V ― ― −1.7 V Reverse recovery time trr IDR = 5 A, VGS = 0 V ― 70 ― ns Reverse recovery charge Qrr dIDR/dt = 50 A/μs ― 0.1 ― μC 3 2006-10-27 MP6404 Electrical Characteristics (Ta = 25°C) (Pch MOS FET) Characteristics Symbol Test Condition Min Typ. Max Unit Gate leakage current IGSS VGS = ±16 V, VDS = 0 V ― ― ±10 μA Drain cut-off current IDSS VDS = −60 V, VGS = 0 V ― ― −100 μA V (BR) DSS ID = −10 mA, VGS = 0 V −60 ― ― V Vth VDS = −10 V, ID = −1 mA −0.8 ― −2.0 V VGS = −4 V, ID = −2.5 A ― 0.24 0.28 VGS = −10 V, ID = −2.5 A ― 0.16 0.19 VDS = −10 V, ID =−2.5 A 2.0 4.0 ― S ― 630 ― pF ― 95 ― pF ― 290 ― pF ― 25 ― ― 45 ― Gate threshold voltage Drain-source ON resistance RDS (ON) Forward transfer admittance |Yfs| Input capacitance Ciss Reverse transfer capacitance Crss Output capacitance Coss Rise time VDB = −10 V, VGS = 0 V, f = 1 MHz tr ID = −2.5 A 0V Turn-on time ton VGS −10 V Fall time 4.7 Ω Switching time tf Ω VOUT RL = 12 Ω Drain source breakdown voltage ns ― 55 ― ― 200 ― ― 22 ― nC ― 16 ― nC ― 6 ― nC VDD ≈ −30 V Turn-off time toff Total gate charge VIN: tr, tf < 5 ns, duty ≤ 1%, tw = 10 μs Qg (gate-source plus gate-drain) Gate-source charge Qgs Gate-drain (“miller”) charge Qgd VDD ≈ −48 V, VGS = −10 V, ID = −5 A Source-Drain Diode Ratings and Characteristics (Ta = 25°C) Characteristics Symbol Test Condition Min Typ. Max Unit Continuous drain reverse current IDR ― ― ― −5 A Pulse drain reverse current IDRP ― ― ― −20 A Diode forward voltage VDSF IDR = −5 A, VGS = 0 V ― ― 1.7 V Reverse recovery time trr IDR = −5 A, VGS = 0 V ― 80 ― ns Reverse recovery charge Qrr dIDR/dt = 50 A/μs ― 0.1 ― μC Marking MP6404 JAPAN Part No. (or abbreviation code) Lot No. A line indicates lead (Pb)-free package or lead (Pb)-free finish. 4 2006-10-27 MP6404 Nch MOS FET ID – VDS 5 10 3.5 4 10 8 4 16 3.3 Drain current ID (A) Drain current ID (A) 6 ID – VDS 20 3 3 2 Common source Tc = 25°C 1 6 Common source Tc = 25°C 8 12 4.5 4 8 3.5 4 VGS = 2.5 V 3 VGS = 2.5 V 0 0 0.4 0.8 1.2 Drain-source voltage 1.6 0 0 2.0 4 VDS (V) 8 12 16 Drain-source voltage ID – VGS VDS (V) VDS – VGS 2.0 10 Common source Common source VDS (V) VDS = 10 V 8 6 Drain-source voltage Drain current ID (A) 20 4 25 2 Tc = −55°C Tc = 25°C 1.6 1.2 8 0.8 5 0.4 ID = 2.5 A 100 0 0 2 4 6 Gate-source voltage 8 0 0 10 4 VGS (V) 12 16 20 VGS (V) RDS (ON) – ID 0.5 20 Common source 10 VDS = 10 V Drain-source on resistance RDS (ON) (Ω) |Yfs| (S) |Yfs| – ID Forward transfer admittance 8 Gate-source voltage Tc = −55°C 5 25 3 100 1 0.3 VGS = 4 V 10 0.1 0.05 Common source Tc = 25°C 0.5 0.3 0.5 1 3 5 10 0.03 0.3 30 Drain current ID (A) 0.5 1 3 5 10 Drain current ID (A) 5 2006-10-27 MP6404 Nch MOS FET RDS (ON) – Tc IDR – VDS 20 (A) Common source 0.3 Drain reverse current IDR Drain-source on resistance RDS(ON) (Ω) 0.4 2.5 1.3 ID = 4 A 0.2 4 VGS = 4 V 2.5, 1.3 0.1 VGS = 10 V 10 5 10 3 3 1 1 0.5 VGS = 0, −1 V 0.3 Common source Tc = 25°C 0 −80 −40 0 40 80 120 0.1 0 160 Case temperature Tc (°C) −0.4 −0.8 −1.2 Drain-source voltage Capacitance – VDS −1.6 −2.0 −2.4 VDS (V) Vth – Tc 3000 2.5 Vth (V) Common source 500 Ciss 300 Gate threshold voltage Capacitance C (pF) 1000 Coss 100 50 Common source 30 VGS = 0 V f = 1 MHz Tc = 25°C 10 0.3 0.5 0.1 Crss 1 3 5 Drain-source voltage 10 30 50 100 VDS = 10 V 2.0 1.5 1.0 0.5 0 −80 VDS (V) ID = 1 mA −40 0 40 80 120 160 Case temperature Tc (°C) Dynamic Input/Output Characteristics 80 16 12 Tc = 25°C 60 12 24 VDS VDD = 48 V VDD = 48 V 40 8 24 20 4 12 0 0 VGS 20 40 60 VGS (V) ID = 5 mA Gate-source voltage Drain-source voltage VDS (V) Common source 0 80 Total gate charge Qg (nC) 6 2006-10-27 MP6404 Pch MOS FET ID – VDS ID – VDS −5 −10 Common source −6 Tc = 25°C −6 Common source Tc = 25°C −8 −4 −4 −8 −8 −10 Drain current ID (A) Drain current ID (A) −10 −3.5 −4 −3 −3 −2 −6 −3.5 −4 −3 −2.5 −1 −2 −2.5 VGS = −2V 0 0 −0.4 −0.8 −1.2 Drain-source voltage −1.6 VGS = −2V 0 0 −2.0 −2 VDS (V) −4 −8 Drain-source voltage ID – VGS −10 VDS (V) VDS – VGS −2.0 −10 Common source 100 Common source VDS = −10 V VDS (V) Tc = −55°C 25 −8 −6 −4 −2 Tc = 25°C −1.6 −1.2 Drain-source voltage Drain current ID (A) −6 −0.8 ID = −5 A −4 −3 −0.4 −2 ) −1 0 0 −2 −4 −6 Gate-source voltage −8 0 0 −10 −4 −8 VGS (V) −16 −20 VGS (V) RDS (ON) – ID 30 3 Common source Common source VDS = −10 V Drain-source ON resistance RDS (ON) (Ω) |Yfs| (S) |Yfs| – ID Forward transfer admittance −12 Gate-source voltage 10 5 Tc = −55°C 3 25 100 1 Tc = 25°C 1 0.5 0.3 −10 0.1 0.5 0.05 0.3 −0.1 0.03 −0.1 −0.3 −0.5 −1 −3 −5 −10 −30 Drain current ID (A) VGS = −4 V −0.3 −0.5 −1 −3 −5 −10 −30 Drain current ID (A) 7 2006-10-27 MP6404 Pch MOS FET IDR – VDS −30 Common source (A) Common source 0.8 Drain reverse current IDR Drain-source on resistance RDS (ON) (Ω) RDS (ON) – Tc 1.0 0.6 ID = −5 A 0.4 −2.5 −1.2 VGS = −4 V 0.2 ID = −5, −2.5, −1.2 A VGS = −10 V 0 −80 −40 0 40 80 120 −10 −5 −3 −1 −0.5 −10 −3 −1 VGS = 0, 1 V −0.3 −0.1 0 160 Tc = 25°C Case temperature Tc (°C) 0.4 0.8 1.2 Drain-source voltage Capacitance – VDS 1.6 2.0 VDS (V) Vth – Tc 5000 −2.0 Vth (V) 1000 Ciss 500 Gate threshold voltage Capacitance C (pF) 3000 300 Coss Common source 100 50 VGS = 0 V Crss f = 1MHz Tc = 25°C 30 −0.1 −0.3 −1 −3 −10 Drain-source voltage −30 −100 −1.6 −1.2 −0.8 Common source −0.4 VDS = −10 V ID = −1 mA VDS (V) 0 −80 −40 0 40 80 120 160 Case temperature Tc (°C) Dynamic Input/Output Characteristics −40 −20 −16 VDS −30 −12 −24 −20 −10 0 0 VDD = −48 V −8 −4 VGS 8 −12 16 24 32 VGS (V) Common source ID = −5 A Tc = 25°C Gate-source voltage Drain-source voltage VDS (V) −50 0 40 Total gate charge Qg (nC) 8 2006-10-27 MP6404 PDT – Ta 8 Channel temperature increase 6 ΔTch (°C) (1) 1-device operation (2) 2-device operation (3) 3-device operation (4) 6-device operation Attached on a circuit board (W) (4) 4 (3) Circuit board (2) 2 (1) 0 0 40 80 120 160 (1) (3) (4) 80 Circuit board Attached on a circuit board (1) 1-device operation (2) 2-device operation (3) 3-device operation (4) 6-device operation 40 0 0 200 (2) 120 Ambient temperature Ta (°C) 2 4 6 Total power dissipation 8 PDT 10 (W) rth – tw 300 Transient thermal resistance rth (°C/W) PDT Total power dissipation ΔTch – PDT 160 100 Curves should be applied in thermal limited area. (Single nonrepetitive pulse) The figure shows thermal resistance per device versus pulse width. (4) (3) (2) 30 (1) 10 3 1 Nch MOS FET Pch MOS FET -No heat sink/Attached on a circuit board(1) 1-device operation (2) 2-device operation (3) 3-device operation Circuit board (4) 6-device operation 0.3 0.1 0.001 0.01 0.1 1 Pulse width 9 10 100 1000 tw (s) 2006-10-27 MP6404 Safe Operating Area (Applicable to Nch MOS FET) Safe Operating Area (Applicable to Pch MOS FET) 30 −30 ID max 10 μs* 100 μs* 10 10 ms* 100 ms* 1 3 10 30 Drain-source voltage 1 ms* 100 ms* −3 −1 −0.3 *: Single nonrepetitive pulse Tc = 25°C Curves must be derated linearly with increase in temperature. 0.1 1 100 μs* 1 ms* 3 0.3 *: Single nonrepetitive pulse Tc = 25°C Curves must be derated linearly with increase in temperature. −0.1 −1 100 −3 VDS (V) −10 −30 Drain-source voltage EAS – Tch (Applicable to Nch MOS FET) −100 VDS (V) EAS – Tch (Applicable to Pch MOS FET) 500 Avalanche energy EAS (mJ) 200 160 120 80 40 400 300 200 100 ) Avalanche energy EAS (mJ) 10 μs* −10 Drain current ID (A) 10 ms* Drain current ID (A) ID max 0 25 50 75 100 125 Channel temperature Tch 15 V Peak IAR = 5 A, RG = 25 Ω VDD = 25 V, L = 7 mH (°C) 75 15 V IAR VDD 50 100 125 Channel temperature Tch BVDSS −15 V Test Cirdcuit 0 25 150 BVDSS IAR −15 V VDD VDS Test Waveform Test Circuit Peak IAR = −5 A, RG = 25 Ω VDD = −25 V, L = 14.84 mH ⎞ 1 2 ⎛ B VDSS ⎟ Ε AS = ·L·I · ⎜⎜ ⎟ 2 V − DD ⎠ ⎝ B VDSS 10 150 (°C) VDS Test Waveform ⎞ 1 2 ⎛ B VDSS ⎟ Ε AS = ·L·I · ⎜⎜ ⎟ 2 V − DD ⎠ ⎝ B VDSS 2006-10-27 MP6404 RESTRICTIONS ON PRODUCT USE 20070701-EN • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 11 2006-10-27