ONSEMI NTTS2P02R2

NTTS2P02R2
Power MOSFET
−2.4 Amps, −20 Volts
Single P−Channel Micro8t
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Features
•
•
•
•
•
•
•
Ultra Low RDS(on)
Higher Efficiency Extending Battery Life
Logic Level Gate Drive
Miniature Micro−8 Surface Mount Package
Diode Exhibits High Speed, Soft Recovery
Micro8 Mounting Information Provided
Pb−Free Package is Available
−2.4 AMPERES
−20 VOLTS
RDS(on) = 90 mW
Single P−Channel
D
Applications
• Power Management in Portable and Battery−Powered Products,
i.e.: Cellular and Cordless Telephones, and PCMCIA Cards
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−20
V
Gate−to−Source Voltage − Continuous
VGS
±8.0
V
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 3)
RqJA
PD
ID
ID
IDM
160
0.78
−2.4
−1.92
−20
°C/W
W
A
A
A
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 3)
RqJA
PD
ID
ID
IDM
88
1.42
−3.25
−2.6
−30
°C/W
W
A
A
A
TJ, Tstg
−55 to
+150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = −20 Vdc, VGS = −4.5 Vdc,
Peak IL = −5.0 Apk, L = 28 mH,
RG = 25 W)
EAS
350
mJ
Maximum Lead Temperature for Soldering
Purposes for 10 seconds
TL
Operating and Storage
Temperature Range
March, 2006 − Rev. 5
MARKING DIAGRAM &
PIN ASSIGNMENT
D D D D
8
8
WW
ADG
G
1
Micro8
CASE 846A
STYLE 1
1
S S S G
AD
WW
G
= Specific Device Code
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board
(1 IN SQ, 2 oz Cu 0.06″ thick single sided), Steady State.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
© Semiconductor Components Industries, LLC, 2006
S
1
Device
Package
Shipping†
NTTS2P02R2
Micro8
4000/Tape & Reel
Micro8
(Pb−Free)
4000/Tape & Reel
NTTS2P02R2G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTTS2P02R2/D
NTTS2P02R2
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (Note 4)
Characteristic
Symbol
Min
Typ
Max
Unit
−20
−
−
−12.7
−
−
−
−
−
−
−1.0
−25
−
−
−5.0
−
−
−100
−
−
100
−0.5
−
−0.90
2.5
−1.4
−
−
−
−
0.070
0.100
0.110
0.090
0.130
−
gFS
2.0
4.2
−
Mhos
Ciss
−
550
−
pF
Coss
−
200
−
Crss
−
100
−
td(on)
−
10
−
tr
−
31
−
td(off)
−
33
−
tf
−
29
−
td(on)
−
15
−
tr
−
40
−
td(off)
−
35
−
tf
−
35
−
Qtot
−
10
18
Qgs
−
1.5
−
Qgd
−
5.0
−
VSD
−
−
−0.88
−0.75
−1.0
−
Vdc
trr
−
37
−
ns
ta
−
16
−
tb
−
21
−
QRR
−
0.025
−
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = −250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = −16 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = −16 Vdc, TJ = 125°C)
IDSS
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = −20 Vdc, TJ = 25°C)
IDSS
Gate−Body Leakage Current
(VGS = −8 Vdc, VDS = 0 Vdc)
IGSS
Gate−Body Leakage Current
(VGS = +8 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
mAdc
nAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = −250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = −4.5 Vdc, ID = −2.4 Adc)
(VGS = −2.7 Vdc, ID = −1.2 Adc)
(VGS = −2.5 Vdc, ID = −1.2 Adc)
RDS(on)
Forward Transconductance (VDS = −10 Vdc, ID = −1.2 Adc)
Vdc
mV/°C
W
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = −16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 5 & 6)
Turn−On Delay Time
Rise Time
(VDD = −10 Vdc, ID = −2.4 Adc,
VGS = −4.5 Vdc, RG = 6.0 W)
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
(VDD = −10 Vdc, ID = −1.2 Adc,
VGS = −2.7 Vdc, RG = 6.0 W)
Turn−Off Delay Time
Fall Time
Total Gate Charge
(VDS = −16 Vdc,
VGS = −4.5 Vdc,
ID = −2.4 Adc)
Gate−Source Charge
Gate−Drain Charge
ns
ns
nC
BODY−DRAIN DIODE RATINGS (Note 5)
Diode Forward On−Voltage
(IS = −2.4 Adc, VGS = 0 Vdc)
(IS = −2.4 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = −2.4 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
4. Handling precautions to protect against electrostatic discharge are mandatory.
5. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
6. Switching characteristics are independent of operating junction temperature.
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2
mC
NTTS2P02R2
VGS = −10 V
VGS = −4.5 V
VGS = −2.5 V
3
TJ = 25°C
VGS = −1.9 V
2
VGS = −1.7 V
1
VGS = −1.5 V
0
0.2
2
4
6
8
10
4
3
2
TJ = 25°C
1
TJ = 100°C
1
3
2.5
Figure 2. Transfer Characteristics.
0.05
2
4
6
8
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.12
TJ = 25°C
0.1
VGS = −2.7 V
0.08
VGS = −4.5 V
0.06
0.04
1
1.5
1000
ID = −2.4 A
VGS = −4.5 V
VGS = 0 V
−IDSS, LEAKAGE (nA)
100
1.2
1
0.8
0
25
75
50
100
125
TJ, JUNCTION TEMPERATURE (°C)
2.5
3
3.5
4
4.5
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage.
1.6
−25
2
−ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage.
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
Figure 1. On−Region Characteristics.
0.1
0.6
−50
1.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
1.4
TJ = 55°C
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.15
0
VDS > = 10 V
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
5
VGS = −2.1 V
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
4
150
TJ = 125°C
TJ = 100°C
10
TJ = 25°C
1
0.1
0.01
0
Figure 5. On−Resistance Variation with
Temperature.
4
8
12
16
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
vs. Voltage.
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3
20
C, CAPACITANCE (pF)
VDS = 0 V
1200
VGS = 0 V
Ciss
900
TJ = 25°C
Crss
Ciss
600
300
0
Coss
Crss
10
5
0
−VGS −VDS
5
10
15
20
5
20
18
QT
16
4
14
3
10
Q2
2
1
0
12
VGS
Q1
8
VDS
0
2
4
6
ID = −2.4 A
TJ = 25°C
6
8
12
10
4
14
2
0
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1500
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTTS2P02R2
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
Figure 7. Capacitance Variation
100
VDD = −10 V
ID = −1.2 A
VGS = −2.7 V
100
tr
VDD = −10 V
ID = −2.4 A
VGS = −4.5 V
td (on)
10
1.0
tf
td
(on)
10
tf
td (off)
10
td (off)
tr
t, TIME (ns)
t, TIME (ns)
1000
1.0
100
RG, GATE RESISTANCE (OHMS)
1.0
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Resistive Switching Time Variation
versus Gate Resistance
−IS, SOURCE CURRENT (AMPS)
2
1.6
VGS = 0 V
TJ = 25°C
di/dt
IS
trr
1.2
ta
tb
TIME
0.8
0.25 IS
tp
IS
0.4
0
0.4
0.5
0.6
0.7
0.8
0.9
1
Figure 12. Diode Reverse Recovery Waveform
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage
versus Current
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4
NTTS2P02R2
Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
1
D = 0.5
0.2
0.1
Normalized to R∅ja at Steady State (1 inch pad)
0.1
0.0125 W 0.0563 W
0.110 W
0.273 W
0.113 W
0.436 W
2.93 F
152 F
261 F
0.05
0.02
0.01
0.021 F
0.137 F
1.15 F
Single Pulse
0.01
1E−03
1E−02
1E−01
1E+00
1E+03
t, TIME (s)
Figure 13. FET Thermal Response.
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5
1E+02
1E+03
NTTS2P02R2
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
D
HE
PIN 1 ID
−T−
E
e
b 8 PL
0.08 (0.003)
T B
M
S
A
DIM
A
A1
b
c
D
E
e
L
HE
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
S
SEATING
PLANE
A
0.038 (0.0015)
A1
L
c
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Micro8 is a registered trademark of International Rectifier Corporation.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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NTTS2P02R2/D