P4C150 P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Single 5V ± 10% Power Supply Full CMOS, 6T Cell Separate Input and Output Ports High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Three-State Outputs Fully TTL Compatible Inputs and Outputs Chip Clear Function Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK Low Power Operation – 713 mW Active –10 ns (Commercial) – 550 mW Active –25 ns (Commercial) DESCRIPTION Time required to reset is only 20 ns for the 10 ns SRAM. CMOS is used to reduce power consumption to a low level. The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V ± 10% tolerance power supply. The P4C150 is available in 24-pin 300 mil DIP and SOIC packages providing excellent board level densities. The device is also available in a 28-pin LCC package as well as a 24-pin FLATPACK for military applications. Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating speeds. COLUMN I/O COLUMN SELECT CS WE RS O3 O4 A A A A 3 22 A8 A3 4 21 A7 A4 5 20 RS A5 6 A6 7 I1 19 CS 18 WE 8 17 I2 9 16 OE I4 O1 10 15 I3 O2 11 14 O4 GND 12 13 O3 DIP (P4, D4), SOIC (S4) CERPACK (F4) SIMILAR TOP VIEW OE 3 A2 A3 4 A4 A5 A9 A9 A2 V CC V CC 23 NC 24 2 27 26 25 A8 A7 6 24 RS 7 23 CS NC 8 22 NC A6 I1 9 21 WE 10 20 OE I4 I3 I2 O1 2 28 1 5 11 12 13 19 14 15 16 18 17 O4 INPUT DATA CONTROL 1 A1 O3 I3 I4 O1 O2 A0 NC I1 I2 4,096-BIT MEMORY ARRAY ROW SELECT A1 A0 A A A A A A PIN CONFIGURATIONS O2 GND FUNCTIONAL BLOCK DIAGRAM LCC (L5) TOP VIEW Means Quality, Service and Speed 1Q97 25 P4C150 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C Symbol Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) RECOMMENDED OPERATING CONDITIONS (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol Parameter Conditions Typ. Unit Grade(2) Ambient Temp Gnd VCC Commercial 0˚C to 70˚C 0V 5.0V ± 10% CIN Input Capacitance VIN = 0V 5 pF -55˚C to +125˚C 0V 5.0V ± 10% COUT Output Capacitance VOUT= 0V 7 pF Military DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage (2) Symbol P4C147 Test Conditions Parameter VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current ILO Output Leakage Current Unit Max. Min. 2.4 V 0.4 V 2.2 VCC =+0.5 V –0.5(3) 0.8 V VCC = Max., VIN = GND to VCC –5 +5 µA VCC = Max., CS = VIH, VOUT = GND to VCC –5 +5 µA POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current Temperature Range -10 -12 -15 -20 -25 -35 Commercial Military 130 N/A 130 N/A 120 145 115 135 100 125 N/A 120 Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Unit mA mA 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than – 3.0V and – 100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 26 P4C150 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -12 -10 Parameter -20 -15 -25 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max tRC Read Cycle Time tAA Address Access Time 10 12 15 20 25 35 ns tAC Chip Select Access Time 8 10 12 14 15 35 ns tOH Output Hold from Address Change 2 2 2 2 2 2 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 2 2 ns tHZ Chip Disable to Output in High Z 4 6 8 10 13 15 ns tOE Output Enable to Data Valid 7 9 10 14 15 20 ns tOLZ Output Enable to Output in Low Z tOHZ Output Disable to Output in High Z 10 12 2 15 2 5 20 2 25 2 7 35 2 9 ns 2 11 13 ns 16 TIMING WAVEFORM OF READ CYCLE NO. 1(5,6) (8) t RC ADDRESS t AA t OH DATA OUT PREVIOUS DATA VALID DATA VALID CS CONTROLLED)(5, 7) TIMING WAVEFORM OF READ CYCLE NO. 2 (CS tRC CS t HZ t AC (7) (8) (8) t LZ DATA VALID DATA OUT (8) t OLZ t OHZ HIGH IMPEDANCE (8) t OE OE Notes: 5.WE is HIGH for READ cycle. 6.CS and OE are LOW for READ cycle. 7.ADDRESS must be valid prior to, or concident with, CS transition LOW, tAA must still be met. 8. Transition is measured ±200 mV from steady state voltage prior to change, with loading as specified in Figure 1. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. 27 ns P4C150 TIMING WAVEFORM OF READ CYCLE NO. 3 (OE OE Controlled)(5) t RC (9) ADDRESS t AA OE t t OE OH (8) t OLZ CS t t AC (8) t LZ (8) OHZ (8) t HZ DATA OUT AC CHARACTERISTICS—RESET CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter 1521 05 -10 -12 -15 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max Unit tRRC Reset Cycle Time 20 24 30 40 50 70 ns tWER Write Enable High to Beginning of Reset 0 0 0 0 0 0 ns tCR Chip Select Low to Beginning of Reset 0 0 0 0 0 0 ns tRP 10 12 15 20 25 30 ns tHCR Reset Pulse Width Chip Select Hold after End of Reset 0 0 0 0 0 0 ns tHWR Write Enable Hold after End of Reset 10 12 15 20 25 35 ns tRLZ Reset High to Ourput in Low Z 0 0 0 0 0 0 ns tRHZ Reset Low to Output in High Z 0 0 ns 8 0 10 0 12 0 16 0 20 TIMING WAVEFORM OF RESET CYCLE tRRC ADDRESS WE tWER CS tHWR tHCR tCR tRP RS tRHZ tRLZ O1 –O 4 (DATA OUTPUT) HIGH IMPEDANCE 28 OUTPUT VALID ZERO P4C150 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -10 -25 -12 -15 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max Parameter tWC Write Cycle Time 10 12 15 20 25 35 ns tCW Chip Enable Time to End of Write 8 10 11 13 15 20 ns tAW Address Valid to End of Write 8 10 13 16 20 25 ns tAS Address Set-up Time 0 1 1 1 2 2 ns tWP Write Pulse Width 8 10 11 13 15 20 ns tAH 0 1 1 1 2 2 ns tDW Address Hold Time from End of Write Data Valid to End of Write 5 8 11 13 15 20 ns tDH Data Hold Time 0 1 1 1 2 2 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 8 5 2 12 2 15 3 2 25 20 3 3 ns ns WE CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE t WC (12) ADDRESS t CW CS t AW t WR t AH t WP WE t AS t DW DATA IN t DH DATA VALID t OW(8, 11) (8) t WZ DATA OUT DATA UNDEFINED HIGH IMPEDANCE CS CONTROLLED)(10) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS t WC (12) ADDRESS t AS t CW CS t AH t WR t AW t WP WE t DW DATA IN t DH DATA VALID DATA OUT HIGH IMPEDANCE Notes: 10. CS and WE must be LOW for WRITE cycle. 11. If CS goes HIGH simultaneously with WE high, the output remains in a high impedance state. 12. Write Cycle Time is measured from the last valid address to the first transition address. 29 P4C150 AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE Mode GND to 3.0V RS CS OE WE Output Input Rise and Fall Times 3ns Not Selected X H X X High Z Input Timing Reference Level 1.5V RESET L L X H High Z Output Timing Reference Level 1.5V Output Disabled H L H H High Z READ H L L H DOUT WRITE H L X L High Z Output Load See Figures 1 and 2 +5 R DOUT 480Ω TH = 166.5 Ω VTH = 1.73 V D OUT 255Ω 30pF(5pF* for tHZ, tLZ, tOHZ, tOLZ , tWZ and tOW ) 300pF(5pF* for tHZ, tLZ, tOHZ, tOLZ, tWZ and tOW) Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C150, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 30 P4C150 PACKAGE SUFFIX Package Suffix TEMPERATURE RANGE SUFFIX Description Temperature Range Suffix Description Commercial Temperature Range, 0°C to +70°C. Military Temperature Range, –55°C to +125°C. Mil. Temp. with MIL-STD-883 Class B Compliance. P Plastic DIP, 300 mil wide standard C D CERDIP, 300 mil wide M L LCC F CERPACK S SOIC MB ORDERING INFORMATION P4C150 Device Type xx x x Speed Package Processing C 0˚C to +70˚C M –55°C to +125°C MB Mil. Temp. with MIL-STD-883 Class B Compliance P Plastic DIP (300 mil) D CERDIP (300 mil) S Plastic SOIC (300 mil) L Ceramic LCC F CERPACK 10, 12, 15, 20, 25, 35 ns 1K x 4 SRAM The P4C150 is also available to SMD-5962-88588 SELECTION GUIDE The P4C150 is available in the following temperature, speed and package options. Temperature Range Speed (ns) Package 10 12 15 20 25 35 –10PC – 10SC –12PC –12SC –15PC –15SC –20PC –20SC –25PC –25SC N/A N/A Commercial Plastic DIP SOIC Military Temp. CERDIP (300 mil) LCC CERPACK N/A N/A N/A N/A N/A N/A –15DM –15LM –15FM –20DM –20LM –20FM –25DM –25LM –25FM –35DM –35LM –35FM Military Processed* CERDIP (300 mil) LCC CERPACK N/A N/A N/A N/A N/A N/A –15DMB –15LMB –15FMB –20DMB –20LMB –20FMB –25DMB –25LMB –25FMB –35DMB –35LMB –35FMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available 31 P4C150 32