RFP4N100, RF1S4N100SM Data Sheet 4.3A, 1000V, 3.500 Ohm, High Voltage, N-Channel Power MOSFETs August 1999 File Number 2457.4 Features • 4.3A, 1000V The RFP4N100 and RFP4N100SM are N-Channel enhancement mode silicon gate power field effect transistors. They are designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from an integrated circuit. • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA09850. Symbol • rDS(ON) = 3.500Ω • UIS Rating Curve (Single Pulse) • -55oC to 150oC Operating Temperature D Ordering Information PART NUMBER PACKAGE BRAND RFP4N100 TO-220AB RFP4N100 RF1S4N100SM TO-263AB F1S4N100 G S NOTE: When ordering, use the entire part number. Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE DRAIN (FLANGE) 4-528 CAUTION: These devices are sensitive to electrostatic discharge; follow properS ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFP4N100, RF1S4N100SM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP4N100, RF1S4N100SM UNITS Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 1000 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 1000 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 4.3 A A Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 17 Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS (See UIS SOA Curve) (Figures 4, 14, 15) mJ Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 1.2 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 1000 - - V Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2 - 4 V IDSS VDS = 1000V, VGS = 0V - - 25 µA VDS = 800V, VGS = 0V, TC = 150oC - - 100 µA VGS = ±20V - - ±100 nA rDS(ON) ID = 2.5A, VGS = 10V (Figures 8, 9) - - 3.500 Ω td(ON) VDD = 500V, ID ≈ 3.9A, RGS = 9.1Ω, RL = 120Ω) - - 30 ns - - 50 ns td(OFF) - - 170 ns tf - - 50 ns - - 120 nC Zero Gate Voltage Drain Current Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Delay Time IGSS Rise Time tr Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) VGS = 20V, ID = 3.9A, VDS = 800V (Figure 13) Thermal Resistance Junction to Case RθJC - - 0.83 oC/W Thermal Resistance Junction to Ambient RθJA - - 62 oC/W MIN TYP MAX ISD = 4.3A - - 1.8 V ISD = 3.9A, dISD/dt = 100A/µs - - 1000 ns Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage Reverse Recovery Time VSD trr TEST CONDITIONS NOTES: 2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. 4-529 UNITS RFP4N100, RF1S4N100SM Typical Performance Curves TC = 25oC, Unless Otherwise Specified 4.5 1.2 POWER DISSIPATION MULTIPLIER 4.0 1.0 ID, DRAIN CURRENT (A) 3.5 0.8 0.6 0.4 3.0 2.5 2.0 1.5 1.0 0.2 0.5 0 0.0 0 25 125 50 75 100 TA , AMBIENT TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE 25 100 IAS, AVALANCHECURRENT (A) ID, DRAIN CURRENT (A) RFP4N100, RF1S4N100SM 10µs 100µs 1ms 1 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 DC TC = 25oC TJ = MAX RATED SINGLE PULSE 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 0.01 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 6V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 0.10 1 tAV, TIME IN AVALANCHE (ms) 6 VGS = 5V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2 VGS = 10V VGS = 6V 8 6 VGS = 5V 4 2 VGS = 4V 0 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA 8 4 STARTING TJ = 25oC STARTING TJ = 150oC 10 10 VGS = 10V IF R = 0 tav = (L)(Ias) / (1.3 x RATED BVDSS - VDD) Idm 1000 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 10 150 IF R ≠ 0 tav = (L/R) In ((Ias x R) / (1.3 x RATED BVDSS - VDD) + 1) 0.01 1 75 100 125 TC, CASE TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 10 50 0 100 200 300 400 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. OUTPUT CHARACTERISTICS 4-530 VGS = 4V 500 0 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 50 RFP4N100, RF1S4N100SM 6 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS = 15V 4 3 2 150oC 25oC 1 0 0 VGS = 10V PULSE DURATION = 80µs 5 DUTY CYCLE = 0.5% MAX 2 4 6 VGS, GATE TO SOURCE VOLTAGE (V) ON RESISTANCE (Ω) 5 TC = 25oC, Unless Otherwise Specified (Continued) rDS(ON), DRAIN TO SOURCE IDS(ON), DRAIN TO SOURCE CURRENT (A) Typical Performance Curves 2 4 6 8 ID, DRAIN CURRENT (A) 10 12 1.3 ID = 250µA 2.5 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 0 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT VGS = 10V, ID = 4.3A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 1.2 1.1 1.0 0.9 0.8 0.5 -50 0 50 100 TJ , JUNCTION TEMPERATURE (oC) -40 150 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 80 0 40 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 3000 CISS 2000 1500 COSS 1000 CRSS 500 ID, SOURCE TO DRAIN CURRENT (A) 100 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 2500 C, CAPACITANCE (pF) 2 0 3.0 0 3 1 8 FIGURE 7. TRANSFER CHARACTERISTICS 4 TJ = 150oC 10 1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4-531 TJ = 25oC 0 0.3 0.6 0.9 1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) 1.5 FIGURE 12. DRAIN CURRENT vs SOURCE TO DRAIN DIODE VOLTAGE RFP4N100, RF1S4N100SM Typical Performance Curves TC = 25oC, Unless Otherwise Specified (Continued) VGS, GATE TO SOURCE VOLTAGE (V) 16 ID = 3.9A VDS = 100V 12 VDS = 200V VDS = 400V 8 4 0 0 20 40 60 Qg, TOTAL GATE CHARGE (nC) 80 FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 4-532 10% 50% 50% PULSE WIDTH FIGURE 17. RESISTIVE SWITCHING WAVEFORMS RFP4N100, RF1S4N100SM Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V Ig(REF) 0 Qg(TH) Ig(REF) 0 FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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