RFL1N10L 1A, 100V, 1.200 Ohm, Logic Level, N-Channel Power MOSFET September 1998 Features Description • 1A, 100V This is an N-Channel enhancement mode silicon gate power field effect transistor specifically designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, and solenoid drivers. This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. • rDS(ON) = 1.200Ω Ordering Information PART NUMBER RFL1N10L PACKAGE TO-205AF BRAND RFL1N10L NOTE: When ordering, use the entire part number. Formerly developmental type TA09524. Symbol D G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 1510.3 RFL1N10L Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 1MΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . .TL RFL1N10L 100 100 1 5 ±10 8.33 0.0667 -55 to 150 UNITS V V A A V W W/oC oC 260 oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 100 - - V Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0 Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 1 - 2 V VDS = Rated BVDSS - - 1 µA VDS = 0.8 x Rated BVDSS, VDS = 80V, TC = 125oC - - 25 µA VGS = ±10V, VDS = 0 - - ±100 nA Zero Gate Voltage Drain Current Gate to Source Leakage Current IDSS IGSS Drain to Source On Resistance (Note 2) rDS(ON) ID = 1A, VGS = 5V (Figures 6, 7) - - 1.200 Ω Drain to Source On Voltage (Note 2) VDS(ON) ID = 1A, VGS = 5V - - 1.2 V ID ≈ 1A, VDD = 50V, RG = 6.25Ω, VGS = 5V, RL = 50Ω (Figures 10, 11, 12) - 10 25 ns - 15 45 ns td(OFF) - 25 45 ns tf - 30 50 ns - - 200 pF - - 80 pF - - 35 pF Turn-On Delay Time Rise Time td(ON) tr Turn-Off Delay Time Fall Time Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Thermal Resistance Junction to Case VGS = 0V, VDS = 25V, f = 1MHz (Figure 9) - - 15 oC/W MIN TYP MAX UNITS ISD = 1A - - 1.4 V ISD = 2A, dISD/dt = 50A/µs - 100 - ns RθJC Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS NOTES: 2. Pulse test: width ≤ 300µs duty cycle ≤ 2%. 3. Repetitive rating: pulse witdh limited by maximum junction temperature. 2 RFL1N10L Unless Otherwise Specified 1.2 1.2 1.0 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 25 0 0 25 50 75 100 TC, CASE TEMPERATURE (oC) 125 150 10 TC = 25oC OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) 75 100 125 TC, CASE TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE IDS, DRAIN TO SOURCE CURRENT (A) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 50 1 0.1 8 PULSE DURATION = 80µs DUTY CYCLE ≤ 2% TC = 25oC 7 VGS = 10V 6 VGS = 5V 5 4 VGS = 4V 3 2 VGS = 3V 1 VGS = 2V 0.01 0 1 10 100 VDS, DRAIN TO SOURCE (V) 1 0 1000 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 3 4 2 5 -40oC 25oC 4 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) VDS = 10V PULSE DURATION = 80µs DUTY CYCLE ≤ 2% 125oC 3 2 125oC 1 -40oC 0 1 2 5 6 7 9 8 10 FIGURE 4. SATURATION CHARACTERISTICS 6 ID(ON), DRAIN CURRENT (A) 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 1 FIGURE 5. TRANSFER CHARACTERISTICS 25oC -40oC 0.5 0 6 125oC 1.5 VGS = 5V PULSE DURATION = 80µs DUTY CYCLE ≤ 2% 0 1 2 3 4 5 ID, DRAIN CURRENT (A) 6 FIGURE 6. DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENT 3 7 RFL1N10L NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 Unless Otherwise Specified (Continued) 2 ID = 1A NORMALIZED GATE THRESHOLD VOLTAGE 2 1.5 1 0.5 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 1.5 1 0.5 150 -50 FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 150 FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 100 240 VDS, DRAIN TO SOURCE VOLTAGE (V) f = 1MHz 200 C, CAPACITANCE (pF) VGS = VDS ID = 250µA VGS = 5V 160 120 CISS 80 COSS 40 CRSS 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 BVDSS RL = 50 IG(REF) = 0.094mA VGS = 5V 75 8 6 50 VDD = VDSS VDD = VDSS GATE SOURCE VOLTAGE 0.75VDSS 0.75VDSS 0.50VDSS 0.50VDSS 0.25VDSS 0.25VDSS DRAIN SOURCE VOLTAGE 25 4 2 0 0 I 20 G(REF) IG(ACT) 60 VGS, GATE TO SOURCE VOLTAGE (V) Typical Performance Curves t, TIME (µs) I 80 G(REF) IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE Test Circuits and Waveforms tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 11. SWITCHING TIME TEST CIRCUIT 10% 50% 50% PULSE WIDTH FIGURE 12. RESISTIVE SWITCHING WAVEFORMS 4 RFL1N10L All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 5 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029