Revised April 2005 74VHCT573A Octal D-Type Latch with 3-STATE Outputs General Description Features The VHCT573A is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a Latch Enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. ■ High speed: tPD Protection circuits ensure that 0V to 7V can be applied to the input and output (Note 1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 7.7 ns (typ) at TA ■ High Noise Immunity: VIH 2.0V, VIL 25qC 0.8V ■ Power Down Protection is provided on all inputs and outputs ■ Low Noise: VOLP 1.6V (max) ■ Low Power Dissipation: ICC 4 PA (max) @ TA 25qC ■ Pin and function compatible with 74HCT573 Note 1: Outputs in OFF-State. Ordering Code: Order Number Package Number 74VHCT573AM 74VHCT573ASJ 74VHCT573AMTC 74VHCT573AN Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS500028 www.fairchildsemi.com 74VHCT573A Octal D-Type Latch with 3-STATE Outputs January 1998 74VHCT573A Pin Descriptions Pin Names Truth Table Description Inputs Outputs D0–D7 Data Inputs OE LE D On LE Latch Enable Input L H H H OE 3-STATE Output Enable Input L H L L O0–O7 3-STATE Outputs L L X O0 H X X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Functional Description the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches. The VHCT573A contains eight D-type latches with 3STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions (Note 6) 0.5V to 7.0V 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage (VIN) 4.5V to 5.5V Supply Voltage (VCC) DC Output Voltage (VOUT) 0V to 5.5V Input Voltage (VIN) 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Output Voltage (VOUT) 0V to VCC (Note 4) 0V to 5.5V 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Lead Temperature (TL) 260qC (Soldering, 10 seconds) (Note 3) Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. OV. Note 4: When outputs are in OFF-State or when VCC Note 5: VOUT GND, V OUT ! VCC (Outputs Active). Note 6: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL IOZ Parameter VCC (V) TA Min 25qC Typ 40qC to 85qC TA Max Min HIGH Level 4.5 2.0 2.0 Input Voltage 5.5 2.0 2.0 Max 4.5 0.8 0.8 Input Voltage 5.5 0.8 0.8 4.5 4.40 Output Voltage 4.5 3.94 LOW Level 4.5 Output Voltage 4.5 3-STATE Output 4.50 0.0 0 5.5 V 4.40 V 3.80 V 0.1 0.1 V 0.36 0.44 V r0.25 5.5 Off-State Current r2.5 r0.1 IIN Input Leakage Current ICC Quiescent Supply Current 5.5 4.0 ICCT Maximum ICC/Input 5.5 1.35 Conditions V LOW Level HIGH Level Units PA r1.0 VIN VIH IOH 8 mA VIH IOL 50 PA or VIL IOL 8 mA VIN VIN VIH or VIL VOUT VCC or GND PA VIN 5.5V or GND 40.0 PA VIN VCC or GND 1.50 mA VIN 3.4V Other Inputs IOFF Output Leakage Current 0.0 0.5 50 PA or VIL IOH PA 5.0 VOUT VCC or GND 5.5V (Power Down State) Noise Characteristics Symbol VOLP TA 25qC VCC (V) Typ Limits Quiet Output Maximum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF Quiet Output Minimum Dynamic VOL 5.0 1.2 1.6 V CL 50 pF Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL 50 pF Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL 50 pF Parameter Units Conditions (Note 7) VOLV (Note 7) VIHD (Note 7) VILD (Note 7) Note 7: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHCT573A Absolute Maximum Ratings(Note 2) 74VHCT573A AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay Time tPHL (LE to On) tPLH Propagation Delay Time tPHL (D to On) tPZL 3-STATE Output tPZH Enable Time tPLZ 3-STATE Output tPHZ Disable Time tOSLH Output to Output tOSHL Skew VCC (V) TA Min 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 25qC 40qC to 85qC TA Units Conditions Typ Max Min Max 7.7 12.3 1.0 13.5 8.5 13.3 1.0 14.5 5.1 8.5 1.0 9.5 5.9 9.5 1.0 10.5 6.3 10.9 1.0 12.5 7.1 11.9 1.0 13.5 8.8 11.2 1.0 12.0 ns RL 1.0 1.0 ns (Note 8) 10 10 5.0 r 0.5 CL 15 pF CL 50 pF CL 15 pF CL 50 pF 1 k: CL 15 pF CL 50 pF 1 k: CL 50 pF ns ns ns RL CIN Input Capacitance 4 pF VCC Open COUT Output Capacitance 6 pF VCC 5.0V CPD Power Dissipation 25 pF (Note 9) Capacitance Note 8: Parameter guaranteed by design. tOSLH |tPLH max t PLH min|; tOSHL |tPHL max tPHL min| Note 9: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per F/F). The total CPD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) 14 13n. AC Operating Requirements Symbol Parameter TA VCC (V) Min 25qC Typ TA Max 40qC to 85qC Min Max Units tW(H) Minimum Pulse Width (LE) 5.0 r 0.5 6.5 8.5 tS Minimum Setup Time 5.0 r 0.5 1.5 1.5 ns tH Minimum Hold Time 5.0 r 0.5 3.5 3.5 ns www.fairchildsemi.com 4 ns 74VHCT573A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHCT573A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHCT573A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHCT573A Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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