LT1310 1.5A Boost DC/DC Converter with Phase-Locked Loop U FEATURES ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LT®1310 boost DC/DC converter combines a 1.5A current mode PWM switcher with an integrated phaselocked loop, allowing the user to set the switching frequency anywhere from 10kHz to 4.5MHz. Intended for use in applications where switching frequency must be accurately controlled, the LT1310 can generate 12V at up to 400mA from a 5V input. Synchronizable or Constant Frequency Low Noise Output Synchronizable Up to 4.5MHz Wide Input Voltage Range: 2.8V to 18V Low Profile Surface Mount Solution (All Ceramic Capacitors) Low VCESAT Switch: 240mV at 1A Adjustable Output from VIN to 35V Small Thermally Enhanced 10-Lead MSOP Package Switching frequency is set with an external capacitor, and the device can be operated in either free-running or phaselocked mode. A wide capture range of nearly 2:1 allows the free-running frequency to be set using standard ±10% tolerance NP0 dielectric capacitors. U APPLICATIO S ■ ■ ■ ■ ■ Instruments Avionics Data Acquisition Communications Imaging Ultrasound The LT1310 is available in the tiny thermally enhanced 10-lead MSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. U ■ TYPICAL APPLICATIO L1 5.6µH C1 4.7µF CERAMIC VIN SHDN SYNC SYNC 178k VOUT = 12V 85 80 FB 3.3VIN 5VIN 75 20.5k CT GND* VC 1500pF LT1310 Efficiency 90 SW PLL-LPF 3.01k VOUT 12V 400mA LT1310 SHUTDOWN 1.6MHz D1 15k C2 4.7µF CERAMIC 100pF NP0 820pF 1310 F01a C1: 4.7µF, X5R OR X7R, 6.3V C2: 4.7µF, X5R OR X7R, 16V D1: MICROSEMI UPS120 OR EQUIVALENT L1: PANASONIC ELL6SH-5R6M *EXPOSED PAD MUST ALSO BE GROUNDED EFFICIENCY (%) VIN 5V 70 65 60 55 50 45 40 35 0 100 200 300 LOAD CURRENT (mA) 400 1310 F01b Figure 1. 5V to 12V Converter Synchronized at 1.6MHz 1310f 1 LT1310 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) SW Voltage .............................................................. 36V VIN Voltage ............................................................. 18V SHDN Voltage ......................................................... 18V SYNC Voltage ........................................................... 5V FB Voltage ................................................................. 5V CT Voltage ................................................................. 5V VC Voltage ................................................................. 2V PLL-LPF Pin Current ............................................... 1mA Operating Temperature Range (Note 2) .. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW FB SHDN PLL-LPF SYNC GND 1 2 3 4 5 10 9 8 7 6 VC CT VIN SW SW LT1310EMSE MSE EXPOSED PAD PACKAGE 10-LEAD PLASTIC MSOP MSE PART MARKING TJMAX = 125°C, θJA = 40°C/W LTRZ EXPOSED PAD IS GROUND (MUST BE SOLDERED TO PCB) Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, VSHDN = 3.3V, unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Undervoltage Lockout 2.8 V Maximum Input Voltage 18 V 1.268 1.268 V V Feedback Voltage ● 1.242 1.236 FB Pin Bias Current 1.255 60 150 nA Reference Line Regulation VIN = 2.9V to 18V 0.01 0.05 %/V Error Amplifier Transconductance ∆I = 5µA 350 Error Amplifier Voltage Gain µA/V 200 SW Current Limit 1.5 SW Saturation Voltage ISW = 1A SW Maximum Duty Cycle CT = 220pF CT = 47pF SW Minimum On Time ISW = 150mA, VC = 0.25V VCO Frequency CT = 220pF, PLL-LPF = High CT = 220pF, PLL-LPF = High CT = 220pF, PLL-LPF = Low CT = 47pF, PLL-LPF = High 80 78 ● 0.950 0.800 V/V 2.1 2.8 0.240 0.320 A V 84 83 % % 70 ns 1.10 1.25 1.30 630 MHz MHz kHz MHz 1.10 –50 1.25 MHz % 500 3.3 Frequency Foldback CT = 220pF, PLL-LPF = High, FB = 0V PLL Lock Range CT = 220pF, Maximum CT = 220pF, Minimum (Percent Change from Max) Supply Current SHDN = High SHDN = Low 11.5 15 1 mA µA SW Leakage Current Switch Off, SW = 3.3V 0.1 5 µA SHDN Pin Bias Current VSHDN = 2.4V 35 65 µA SHDN Pin High Active Mode SHDN Pin Low Shutdown Mode Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 200 0.950 –40 kHz 2.4 V 0.4 V Note 2: The LT1310E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, chacterization and correlation with statistical process controls. 1310f 2 LT1310 U W TYPICAL PERFOR A CE CHARACTERISTICS Feedback Voltage Feedback Pin Current FEEDBACK CURRENT (nA) FB VOLTAGE (V) 1.26 1.25 1.24 Undervoltage Lockout 140 2.80 120 2.75 UNDERVOLTAGE LOCKOUT (V) 1.27 100 80 60 40 1.23 20 1.22 –50 0 25 50 TEMPERATURE (°C) –25 75 0 –50 100 –25 50 25 0 TEMPERATURE (°C) 75 1310 G01 2.60 2.55 2.50 –50 100 –25 0 25 50 TEMPERATURE (°C) 2000 PLL-LPF = HIGH 75 100 1310 G03 Oscillator Frequency vs CT Capacitor Oscillator Frequency vs Feedback Voltage 1400 PLL-LPF = HIGH 220pF CT CAPACITOR 1200 5000 4000 3000 2000 FREQUENCY (kHz) 1600 FREQUENCY (kHz) FREQUENCY (kHz) 2.65 1310 G02 Oscillator Frequency vs CT Capacitor 6000 2.70 1200 800 1000 800 600 400 400 200 1000 20 40 80 60 CAPACITOR (pF) 0 100 100 0 300 700 500 CAPACITOR (pF) 900 LT1372 • G10 3800 800 600 –25 50 25 0 TEMPERATURE (°C) 75 100 1310 G07 1.2 1.4 100 90 3200 2900 2600 2000 –50 100°C 25°C 80 –50°C 70 60 2300 400 0.6 0.8 1.0 FEEDBACK (V) PLL-LPF = HIGH MAX DUTY CYCLE (%) 1000 0.4 Maximum Duty Cycle vs Oscillator Frequency 3500 FREQUENCY (kHz) FREQUENCY (kHz) 1400 1200 0.2 1310 G06 Oscillator Frequency 47pF Capacitor on CT Pin PLL-LPF = HIGH 200 –50 0 1310 G05 Oscillator Frequency 220pF Capacitor on CT Pin 1600 1100 –25 0 25 50 TEMPERATURE (°C) 75 100 1310 G08 50 500 1000 1500 2000 2500 3000 3500 4000 OSCILLATOR FREQENCY (kHz) 1310 G09 1310f 3 LT1310 U W TYPICAL PERFOR A CE CHARACTERISTICS PLL Lock Range 220pF Capacitor on CT Pin Switch Minimum On Time PLL Lock Range 47pF Capacitor on CT Pin 100 1400 3500 90 1200 3000 80 70 60 MAXIMUM FREQUENCY (kHz) FREQUENCY (kHz) MINIMUM ON TIME (ns) MAXIMUM 1000 800 600 2500 2000 MINIMUM 1500 MINIMUM 50 40 –50 400 –25 0 25 50 TEMPERATURE (°C) 75 1000 200 –50 100 –25 75 0 25 50 TEMPERATURE (°C) 1310 G10 –25 0 25 50 TEMPERATURE (°C) 1310 G11 Supply Current 75 100 1310 G12 Switch VCESAT 12 400 11 300 VCESAT (mV) SUPPLY CURRENT (mA) 500 –50 100 10 9 200 100 8 7 –50 –25 0 25 50 TEMPERATURE (°C) 75 0 100 0 0.5 1.0 SWITCH CURRENT (A) 1310 G13 1310 G15 Start-Up Response PLL Response Transient Response VOUT 100mV/DIV VOUT 50mV/DIV VOUT 5V/DIV IL 500mA/DIV IL 200mA/DIV IL 1A/DIV 200mA ILOAD 100mA fSYNC 1.9MHz 1.2MHz VSHDN fSYNC = 1.5MHz 50µs/DIV LT1310 G16 1.5 50µs/DIV LT1310 G17 NO SYNC SIGNAL 20µs/DIV f = 1.2MHz LT1310 G18 1310f 4 LT1310 U U U PI FU CTIO S FB (Pin 1): Feedback Pin for Error Amplifier. Connect the resistor divider here to set output voltage according to the formula: VOUT R1 VOUT = 1.255(1 + R1/R2) FB R2 SYNC (Pin 4): Frequency Synchronization Pin. Inject the external synchronizing signal here. The phase detector is edge triggered and when locked the rising edge of the sync signal will be aligned with the turn-on of the power transistor. The SYNC signal must have a minimum HIGH amplitude of 1.2V and a maximum LOW amplitude of 0.2V with the signal staying low for at least 100ns. 1.2V (MIN) Minimize trace area at this pin. SHDN (Pin 2): Shutdown Pin. For active mode, tie this pin to a voltage between 2.4V and 18V. To disable the part and go into low current mode, pull this pin below 0.4V. PLL-LPF (Pin 3): Phase Locked-Loop Filter Pin. This is the output of the phase detector and also the input to the voltage controlled oscillator (VCO). Connect an RC filter here. Typically, R = 3k and C = 1500pF. The voltage range at the PLL-LPF pin is approximately 0V to 1.5V with 1.5V corresponding to the maximum switching frequency. For applications not requiring synchronization, use a pull-up resistor at this pin; the pull-up voltage must be above 2.4V. Set the pull-up resistor value according to: RPULLUP = ( VPULLUP – 1.5V) 300µA For a pull-up voltage of 5V: RPULLUP = (5V – 1.5V) ≈ 11.6k 300µA 0.2V (MAX) 100ns (MIN) GND (Pin 5, Exposed Pad): Ground. Tie both Pin 5 and the exposed pad directly to local ground plane. The ground metal to the exposed pad should be wide for better heat dissipation. Multiple vias (local ground plane ↔ ground backplane) placed close to the exposed pad can further aid in reducing thermal resistance. The exposed pad must be soldered to ground for the LT1310 to function properly. SW (Pins 6, 7): Switch Pin. Connect inductor/diode here. Minimize trace area at this pin to keep EMI down. VIN (Pin 8): Supply Pin. Must be bypassed as close as possible to the pin. CT (Pin 9): Timing Capacitor Pin for VCO. Place the timing capacitor from this pin to ground to set the frequency range for the oscillator. Minimize trace at this pin to reduce stray capacitance. VC (Pin 10): Compensation Pin for Error Amplifier. Tie an RC network here to compensate the voltage feedback loop. 1310f 5 LT1310 W BLOCK DIAGRA FB VC CT PLL-LPF 1 10 9 3 SYNC – + RAMP GEN. PHASE DETECTOR VCO 4 A1 Σ + + + – A2 1.255V REF S R Q Q SHDN 2 SW SHUTDOWN 6, 7 GND 5 EXPOSED PAD ×5 0.024Ω 1310 BD U OPERATIO To understand operation, refer to the Block Diagram. The LT1310 contains a boost switching regulator that can be phase locked to an external synchronizing signal. The boost regulator uses current mode control and contains a 1.5A NPN power transistor. This type of control uses two feedback loops. The main control loop sets output voltage and operates as follows: a load step causes VOUT and the FB voltage to be slightly perturbed. The error amplifier A1 responds to this change in FB by driving the VC pin either higher or lower. Because switch current is proportional to the VC pin voltage, this change causes the switch current to be adjusted until VOUT is once again satisfied. Loop compensation is taken care of by an RC network from the VC pin to ground. Inside this main loop is another that sets current limit on a cycle-by-cycle basis. This loop utilizes current comparator A2 to control peak current. The oscillator issues a set pulse to the flip-flop at the beginning of each cycle, turning the switch on. With the switch now in the ON state, the SW pin is effectively connected to ground. Current ramps up in the inductor linearly at a rate of VIN/L. Switch current is set by the VC pin voltage and when the voltage across RSENSE trips the current comparator, a reset pulse will be generated and the switch will be turned off. Since the inductor is now loaded up with current, the SW pin will fly high until it is clamped by the catch diode, D1. Current will flow through the diode decreasing at a rate of (VOUT – VIN)/L until the oscillator issues a new set pulse, causing the cycle to repeat. The LT1310 is phase lockable up to 4.5MHz, giving the user precise control over switching frequency. The phase detector compares the incoming sync signal to the internal oscillator signal. If the switching frequency is lower than the sync signal, or if the phase lags the sync signal, then the phase detector output will source current into the PLL-LPF pin, driving it higher. The PLL-LPF pin is also the input to the voltage controlled oscillator. If the sync signal is slower than the switching frequency, the PLL-LPF pin will sink current until the PLL-LPF pin voltage drops. When locked, the PLL-LPF pin rests at a voltage between 0V and 1.5V. The PLL-LPF pin is capable of sinking or sourcing approximately 140µA. 1310f 6 LT1310 U OPERATIO CT Selection for Operating Frequency To synchronize to an external input signal, the timing capacitor and PLL filter components must be chosen properly. This is a simple process and can be done using the graph in Figure␣ 2a. In Figure 2a, operating frequency is plotted versus timing capacitor (CT) with the upper and lower lines corresponding to the minimum and maximum lock frequency given a specific CT value. To choose the right timing capacitor, find the intersection of the desired operating frequency and the dashed line. Then move to the corresponding CT value. Because the lock range for the PLL is nearly 2:1, the nearest standard value NP0 capacitor can be used. For the application shown in Figure 1, a 1.6MHz switching frequency corresponds to an 100pF timing capacitor. Since the switching frequency affects inductor ripple current, the inductor must also be scaled. Table 1 shows recommended component values for various switching frequencies. Table 1. Recommended Component Values for Various Switching Frequencies (RLP = 3.01k) SWITCHING FREQUENCY CT CC CLP RC 600kHz 330pF 1500pF 2700pF 10k 10µH Alternately, use the following equations as a starting point: 1MHz 180pF 1000pF 2200pF 10k 6.2µH for fLOCK ≥ 2MHz: 1.6MHz 100pF 820pF 1500pF 15k 5.6µH 250 • 10 – 6 CT = 0.75 – 40 • 10 –12 fLOCK L1 2MHz 68pF 820pF 1500pF 15k 4.7µH 2.5MHz 47pF 330pF 1500pF 20k 3.3µH 3MHz 33pF 330pF 1000pF 20k 2.7µH for fLOCK ≤ 2MHz: 310 • 10 –6 CT = 0.75 – 60 • 10 –12 fLOCK 100k VIN 5V CT VALUE (pF) 10k MAXIMUM LOCK FREQUECY 1k L1 C1 4.7µF CERAMIC SHDN SYNC IN SYNC FB VC RLP CLP 1M 100k FREQUENCY (Hz) 178k SW PLL-LPF 100 10 10k LT1310 VIN SHUTDOWN MINIMUM LOCK FREQUECY VOUT 12V 20.5k CT GND RC CT CC C2 4.7µF CERAMIC 10M 1310 F02a 1310 F02a Figure 2a. CT vs Operating Frequency Figure 2b. Circuit Used for CT Selection 1310f 7 LT1310 U W U U APPLICATIO S I FOR ATIO Inductor Selection Capacitor Selection Several inductors that work well with the LT1310 are listed in Table 2. This table is not exclusive; there are many other manufacturers and inductors that can be used. Consult each manufacturer for more detailed information and for their entire selection of related parts, as many different sizes and shapes are available. Ferrite core inductors should be used to obtain the best efficiency, as core losses at high frequency are much lower for ferrite cores than for the cheaper powdered-iron ones. Choose an inductor that can handle at least 1.5A without saturating, and ensure that the inductor has a low DCR (copper wire resistance) to minimize I2R power losses. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor only carries one-half of the total switch current. Switching frequency will also affect inductor requirements with higher frequencies corresponding to lower inductance values. A good starting point is to set the inductor ripple current equal to one-third of the peak switch current. Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have an extremely low ESR and are available in very small packages. X5R dielectrics are preferred, followed by X7R, as these materials retain the capacitance over wide voltage and temperature ranges. A 4.7µF to 20µF output capacitor is sufficient for most applications, but systems with very low output currents may need only a 1µF or 2.2µF output capacitor. Solid tantalum or OS-CON capacitors can be used, but they will occupy more board area than a ceramic and will have a higher ESR. Always use a capacitor with a sufficient voltage rating. The inductors shown in Table 2 were chosen for small size. For better efficiency, use similar valued inductors with a larger volume. Ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as close as possible to the LT1310. A 2.2µF to 4.7µF input capacitor is sufficient for most applications. Table 3 shows a list of several ceramic capacitor manufacturers. Consult the manufacturers for detailed information on their entire selection of ceramic parts. Table 3. Ceramic Capacitor Manufacturers Taiyo Yuden AVX Table 2. Recommended Inductors PART MAX L DCR (µH) (mΩ) SIZE L×W×H (mm) CDRH5D18-4R1 CDRH5D18-5R4 CDRH5D28-5R3 CDRH5D28-6R2 CDRH5D28-8R2 CR43-2R2 CR43-3R3 4.1 5.4 5.3 6.2 8.2 2.2 3.3 57 76 38 45 53 71 86 5.7 × 5.7 × 2 ELL6SH-4R7M ELL6SH-5R6M ELL6SH-6R8M 4.7 5.6 6.8 50 59 62 6.4 × 6 × 3 RLF5018T-4R7M1R4 RLF5018-1R5M2R1 RLF5018-2R7M1R8 RLF5018-4R7M1R4 RLF5018-100MR94 4.7 1.5 2.7 4.7 10 45 25 33 45 67 LPO1704-122MC LPO1704-222MC 1.2 2.2 80 120 5.7 × 5.7 × 3 Murata VENDOR Sumida (847) 956-0666 www.sumida.com 4.5 × 4 × 3.2 Panasonic (408) 945-5660 www.panasonic.com 5.6 × 5.2 × 1.8 TDK 5.2 × 5.6 × 1.8 (847) 803-6100 www.tdk.com 5.5 × 6.6 × 1 Coilcraft (800) 322-2645 www.coilcraft.com (408) 573-4150 www.t-yuden.com (803) 448-9411 www.avxcorp.com (714) 852-2001 www.murata.com Compensation—Adjustment To compensate the feedback loop of the LT1310, a series resistor-capacitor network should be connected from the VC pin to GND. For most applications, a capacitor in the range of 220pF to 1500pF will suffice. With a switching frequency of 1.6MHz, a good starting value for the compensation capacitor, CC, is 820pF. The compensation resistor, RC, is usually in the range of 5k to 30k. A good technique to compensate a new application is to use a 30kΩ potentiometer in place of RC, and use a 820pF capacitor for CC. By adjusting the potentiometer while observing the transient response, the optimum value for RC can be found. Figures 3a to 3c illustrate this process for the circuit of Figure 1 with a load current stepped from 1310f 8 LT1310 U W U U APPLICATIO S I FOR ATIO fast current loop which does not require compensation, and a slower voltage loop which does. Standard Bode plot analysis can be used to understand and adjust the voltage feedback loop. VOUT 100mV/DIV AC COUPLED IL 0.5A/DIV RC = 3k 200µs/DIV 1310 F03a Figure 3a. Transient Response Shows Excessive Ringing VOUT 100mV/DIV AC COUPLED IL 0.5A/DIV As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 4 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by the equivalent transconductance amplifier gmp. gmp acts as a current source where the output current is proportional to the VC voltage. Note that the maximum output current of gmp is finite due to the current limit in the IC. From Figure 4, the DC gain, poles and zeroes can be calculated as follows: RC = 6k 200µs/DIV 1310 F03b Figure 3b. Transient Response is Better 2 2 • π • RL • COUT 1 Error Amp Pole: P2 = 2 • π • RO • CC 1 Error Amp Zero: Z1= 2 • π • RC • CC 1.25 DC Gain: A = • gma • RO • gmp • RL VOUT Output Pole: P1= VOUT 100mV/DIV AC COUPLED IL 0.5A/DIV RC = 15k 200µs/DIV 1310 F03b Figure 3c. Transient Response is Well Damped 100mA to 200mA. Figure 3a shows the transient response with RC equal to 3k. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 3b, the value of R C is increased to 6k, which results in a more damped response. Figure 3c shows the results when RC is increased further to 15k. The transient response is nicely damped and the compensation procedure is complete. Compensation—Theory Like all other current mode switching regulators, the LT1310 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT1310: a In addition to the elements from Figure 4, current mode control aslo results in some other poles and zeroes. These are as follows: RHP Zero: Z2 = VIN2 • RL 2 • π • VOUT2 • L 1 Output Zero: Z3 = 2 • π • ESR • COUT f Current Mode Pole: P3 > S 3 The Current Mode zero is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. 1310f 9 LT1310 U W U U APPLICATIO S I FOR ATIO 100 – gmp VOUT COUT 1.255V REFERENCE + VC gma RC RO RL R1 – 50 GAIN (dB) + FB 0 R2 CC 1310 F04 CC: COMPENSATION CAPACITOR COUT: OUTPUT CAPACITOR gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER RC: COMPENSATION RESISTOR RL: OUTPUT RESISTANCE DEFINED AS VOUT DIVIDED BY ILOAD(MAX) RO: OUTPUT RESISTANCE OF gma R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK –50 100 1k 10k 100k FREQUENCY (Hz) 1M 1310 F05a 0 Using the circuit of Figure 1 as an example, the following table shows the parameters used to generate the Bode plot shown in Figure 5. Table 4. Bode Plot Parameters PHASE (DEG) Figure 4. Boost Converter Equivalent Model –100 60° –180 PARAMETER VALUE UNITS COMMENT RL 30 Ω Application Specific COUT 4.7 µF Application Specific RO 2 MΩ Not Adjustable CC 820 pF Adjustable Adjustable RC 15 kΩ VOUT 12 V Application Specific VIN 5 V Application Specific gma 500 µmho Not Adjustable gmp 1.5 mho Not Adjustable L 5.6 µH fS 1.6 MHz Adjustable ESR 10 mΩ Not Adjustable Application Specific From Figure 5, the phase is 120° when the gain reaches 0dB giving a phase margin of 60°. This is more than adequate. The crossover frequency is 50kHz, which is about three times lower than the frequency of the right half plane zero Z2. It is important that the crossover frequency be at least three times lower than the frequency of the RHP zero to achieve adequate phase margin. –200 100 1k 10k 100k FREQUENCY (Hz) 1M 1946 F05b Figure 5. Bode Plot of Figure 1’s Circuit Diode Selection A Schottky diode is recommended for use with the LT1310. The Microsemi UPS120 is a very good choice. Where the input to output voltage differential exceeds 20V, use the UPS140 (a 40V diode). These diodes are rated to handle an average forward current of 1A. For applications where the average forward current of the diode is less than 0.5A, an ON Semiconductor MBR0520 diode can be used. Setting Output Voltage To set the output voltage, select the values of R1 and R2 (see Figure 1) according to the following equation: V R1 = R2 OUT – 1 1.255V A good range for R2 is from 5k to 30k. 1310f 10 LT1310 U W U U APPLICATIO S I FOR ATIO Layout Hints performance with careless layout. Figure 6 shows the recommended component placement for a boost converter. The high speed operation of the LT1310 demands careful attention to board layout. You will not get advertised CC R2 R1 RC VIN CIN CT LT1310 L1 SHDN SYNC SW RLP COUT MULTIPLE VIAS CLP D1 GND VOUT 1310 F06 Figure 6. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using Wide PC Traces. Minimize Trace Area at Pin 10 (VC), Pin 9 (CT) and Pin 1 (FB). Use Multiple Vias to Tie Pin 5 Copper and the Exposed Pad to Ground Plane. Use Vias at One Location Only to Avoid Introducing Switching Currents Into the Ground Plane U PACKAGE DESCRIPTIO MSE Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1663) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 DETAIL “A” 2.06 ± 0.102 (.081 ± .004) 1.83 ± 0.102 (.072 ± .004) 0° – 6° TYP 1 2 3 4 5 GAUGE PLANE 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 0.18 (.007) 1 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.90 ± 0.15 (1.93 ± .006) 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF BOTTOM VIEW OF EXPOSED PAD OPTION SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 10 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 2.794 ± 0.102 (.110 ± .004) 0.13 ± 0.076 (.005 ± .003) 5.23 (.206) MIN 0.889 ± 0.127 (.035 ± .005) 2.083 ± 0.102 3.2 – 3.45 (.082 ± .004) (.126 – .136) MSOP (MSE) 0802 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 1310f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT1310 U TYPICAL APPLICATIO 3MHz 5V to 12V Converter VIN 5V D1 LT1310 C1 2.2µF VIN SHUTDOWN SHDN SYNC IN SYNC PLL-LPF 3MHz R2 20.5k CT CT 33pF NP0 RC 10k CC 680pF 5VIN 85 80 75 FB GND* VC RLP 3.01k CLP 1000pF R1 178k SW 90 VOUT 12V 400mA EFFICIENCY (%) L1 3.3µH Efficiency 3.3VIN 70 65 60 55 50 C2 2.2µF 45 40 1310 TA01a 35 0 100 200 300 LOAD CURRENT (mA) C1, C2: TAIYO YUDEN LMK212BJ225MG D1: MOTOROLA MBRM120 L1: PANASONIC ELL6RH2R7M *EXPOSED PAD MUST ALSO BE GROUNDED 400 1310 TA01b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1613 550mA (ISW), 1.4MHz High Efficiency Step-Up DC/DC Converter 90% Efficiency, VIN: 0.9V to 10V, VOUT(MAX): 34V, IQ: 3mA, ISD: <1µA, ThinSOTTM Package LT1618 1.5A (ISW), 1.25MHz, High Efficiency Step-Up DC/DC Converter 90% Efficiency, VIN: 1.6V to 18V, VOUT(MAX): 35V, IQ: 1.8mA, ISD: <1µA, 10-Lead MS Package LT1946/LT1946A 1.5A (ISW), 1.2/2.7MHz, High Efficiency Step-Up DC/DC Converters VIN: 2.45V to 16V, VOUT(MAX): 34V, IQ: 3.2mA, ISD: <1µA, MS8 Package LT1961 1.5A (ISW), 1.25MHz, High Efficiency Step-Up DC/DC Converter 90% Efficiency, VIN: 3V to 25V, VOUT(MAX): 35V, IQ: 0.9mA, ISD: 6µA, MS8E Package LTC®3400/LTC3400B 600mA (ISW), 1.2MHz, Synchronous Step-Up DC/DC Converters 92% Efficiency, VIN: 0.85V to 5V, VOUT(MAX): 5V, IQ: 19µA/300µA, ISD: <1µA, ThinSOT Package LTC3401 1A (ISW), 3MHz, Synchronous Step-Up DC/DC Converter 97% Efficiency, VIN: 0.5V to 5V, VOUT(MAX): 6V, IQ: 38µA, ISD: <1µA, 10-Lead MS Package LTC3402 2A (ISW), 3MHz, Synchronous Step-Up DC/DC Converter 97% Efficiency, VIN: 0.5V to 5V, VOUT(MAX): 6V, IQ: 38µA, ISD: <1µA, 10-Lead MS Package ThinSOT is a trademark of Linear Technology Corporation. 1310f 12 Linear Technology Corporation LT/TP 0103 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001