FDS4895C Dual N & P-Channel PowerTrench MOSFET General Description Features These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. • Q1: • Q2: P-Channel –4.4A, –40V RDS(on) = 46mΩ @ VGS = –10V RDS(on) = 63mΩ @ VGS = –4.5V • Motor Control • DC/DC conversion • High power and handling capability in a widely used surface mount package DD2 DD2 D1 D 4 6 Pin 1 SO-8 Drain-Source Voltage Gate-Source Voltage ID Drain Current 2 8 1 S TA = 25°C unless otherwise noted Parameter VDSS VGSS 3 Q1 7 G2 S2 G G1 S S1 S Absolute Maximum Ratings Symbol Q2 5 DD1 SO-8 Q1 - Continuous - Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1a) Q2 Units 40 40 ±20 5.5 20 ±20 –4.4 –20 V V A 2 1.6 1 0.9 –55 to +150 °C (Note 1a) 78 °C/W (Note 1) 40 (Note 1a) (Note 1b) (Note 1c) TJ, TSTG RDS(on) = 39mΩ @ VGS = 10V RDS(on) = 57mΩ @ VGS = 7V Application PD N-Channel 5.5A, 40V Operating and Storage Junction Temperature Range W Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDS4895C FDS4895C 13” 12mm 2500 units 2005 Fairchild Semiconductor Corporation FDS4895C Rev C(W) FDS4895C June 2005 Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units Off Characteristics BVDSS VGS = 0 V, ID = 250 µA VGS = 0 V, ID = –250 µA ID = 250 µA, Referenced to 25°C ID = –250 µA, Referenced to 25°C VDS = 32 V, VGS = 0 V VDS = –32 V, VGS = 0 V VGS = 20 V, VDS = 0 V IGSSF Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage, Forward IGSSR Gate-Body Leakage, Reverse VGS = –20 V, ∆BVDSS ∆TJ IDSS On Characteristics 40 –40 V 42 –40 All mV/°C 1 –1 100 µA –100 nA 5 –3 V nA (Note 2) VGS(th) Gate Threshold Voltage ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance gFS VDS = 0 V Q1 Q2 Q1 Q2 Q1 Q2 All Forward Transconductance VDS = VGS, ID = 250 µA VDS = VGS, ID = –250 µA ID = 250 µA, Referenced to 25°C ID = –250 µA, Referenced to 25°C VGS = 10 V, ID = 5.5 A VGS = 7 V, ID = 4.8 A VGS = 10 V, ID = 5.5 A, TJ = 125°C VGS = –10 V, ID = –4.4 A VGS = –4.5 V, ID = –3.8 A VGS = –10 V, I D = –4.4 A, TJ = 125°C VDS = 10 V, ID = 5.5 A VDS = –10 V, ID =–4.4 A Q1 Q2 Q1 Q2 Q1 Q1 Q2 3.7 –1.7 –8 4 32 42 49 37 50 55 10 12 Q1 VDS = 20 V, VGS = 0 V, f = 1.0 MHz Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 410 1050 97 140 47 70 2 9 Q2 2 –1 mV/°C 39 57 64 46 63 73 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Q2 Reverse Transfer Capacitance VDS = –20 V, VGS = 0 V, f = 1.0 MHz RG Gate Resistance VGS = 15 mV, f = 1.0 MHz pF pF pF Ω FDS4895C Rev C(W) FDS4895C Electrical Characteristics Symbol Parameter Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qg s Gate-Source Charge Qgd (continued) TA = 25°C unless otherwise noted Test Conditions Type Min Typ Max Units (Note 2) Gate-Drain Charge Q1 VDD = 20 V, ID = 1 A, VGS = 10V, RG E N = 6 Ω Q2 VDD = –20 V, ID = –1 A, VGS = –10V, RG E N = 6 Ω Q1 VDS = 20 V, ID = 5.5 A, VGS = 10 V Q2 VDS = –20 V, ID = –4.4 A,VGS =–10 V Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 9 12 4 15 18 45 3 18 7 20 2.4 3 2 4 18 22 8 27 32 72 6 32 10 28 Q1 Q2 Q1 Q2 Q1 Q2 0.7 –0.7 21 24 12 12 1.2 –1.2 ns ns ns ns nC nC nC Drain–Source Diode Characteristics VSD trr Qrr Drain-Source Diode Forward Voltage Diode Reverse Recovery Time Diode Reverse Recovery Charge VGS = 0 V, IS = 1.3 A (Note 2) VGS = 0 V, IS = –1.3 A (Note 2) Q1 IF = 5.5 A, diF/dt = 100 A/µs Q2 IF = –4.4 A, diF/dt = 100 A/µs V nS nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 78°/W when mounted on a 0.5 in2 pad of 2 oz copper b) 125°/W when mounted on a .02 in2 pad of 2 oz copper c) 135°/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDS4895C Rev C(W) FDS4895C Electrical Characteristics FDS4895C Typical Characteristics: Q1 (N-Channel) 2.6 20 7.0V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = 10V ID , DRAIN CURRENT (A) 6.5V 16 12 6.0V 8 5.5V 4 0 0.5 1 1.5 2 V DS, DRAIN TO SOURCE VOLTAGE (V) VGS = 6.0V 2 1.8 1.6 6.5V 1.4 7.0V 1.2 8.0V 10V 1 2.5 0 Figure 1. On-Region Characteristics. 4 8 12 ID , DRAIN CURRENT (A) 16 20 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 0.105 ID = 5.5A VGS = 10V I D = 2.8A RDS(ON), ON-RESISTANCE (OHM) R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 2.2 0.8 0 1.6 1.4 1.2 1 0.8 0.095 0.085 0.075 o TA = 125 C 0.065 0.055 0.045 o T A = 25 C 0.035 0.6 0.025 -50 -25 0 25 50 75 100 o T J, JUNCTION TEMPERATURE ( C) 125 150 5 Figure 3. On-Resistance Variation with Temperature. 6 7 8 9 VGS, GATE TO SOURCE VOLTAGE (V) 10 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 30 100 o o T A = -55 C 25 C 25 I S, REVERSE DRAIN CURRENT (A) VDS = 10V ID , DRAIN CURRENT (A) 2.4 o 125 C 20 15 10 5 VGS = 0V 10 o TA = 125 C 1 o 25 C 0.1 o -55 C 0.01 0.001 0.0001 0 3 4 5 6 7 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 8 0 0.2 0.4 0.6 0.8 1 VSD , BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4895C Rev C(W) FDS4895C Typical Characteristics: Q1 (N-Channel) 600 ID = 5.5A VDS = 10V f = 1 MHz VGS = 0 V 20V 12 500 10 CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 14 30V 8 6 4 C iss 400 300 200 C oss 100 2 Crss 0 0 0 2 4 6 8 10 12 0 5 10 15 20 25 30 V DS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. 40 Figure 8. Capacitance Characteristics. 50 R DS(ON) LIMIT P(pk), PEAK TRANSIENT POWER (W) 100 I D, DRAIN CURRENT (A) 35 100µs 10 1ms 10ms 100ms 1 1s 10s DC VGS = 10.0V SINGLE PULSE o RθJA = 135 C/W 0.1 o TA = 25 C 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. 100 SINGLE PULSE R θJA = 135°C/W TA = 25°C 40 30 20 10 0 0.001 0.01 0.1 1 t1 , TIME (sec) 10 100 1000 Figure 10. Single Pulse Maximum Power Dissipation. FDS4895C Rev C(W) FDS4895C Typical Characteristics: Q2 (P-Channel) 30 2.6 -6.0V -4.5V -ID, DRAIN CURRENT (A) 25 R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS = -10V -4.0V 20 15 -3.5V 10 -3.0V 5 0 2.4 2.2 VGS = - 3.5V 2 1.8 -4.0V 1.6 -4.5V 1.4 -6.0V 1.2 -10V 1 0.8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 11. On-Region Characteristics. 20 25 30 Figure 12. On-Resistance Variation with Drain Current and Gate Voltage. 0.14 1.6 I D = -2.2A I D = -4.4A VGS = - 10V 1.5 RDS(ON), ON-RESISTANCE (OHM) R DS(ON) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE 15 -ID , DRAIN CURRENT (A) 1.4 1.3 1.2 1.1 1 0.9 0.8 0.12 0.1 o T A = 125 C 0.08 0.06 o TA = 25 C 0.04 0.7 0.6 0.02 -50 -25 0 25 50 75 100 125 150 2 4 TJ, JUNCTION TEMPERATURE (oC) Figure 13. On-Resistance Variation with Temperature. 8 10 Figure 14. On-Resistance Variation with Gate-to-Source Voltage. 25 o -IS, REVERSE DRAIN CURRENT (A) 100 VDS = -10V -ID , DRAIN CURRENT (A) 6 -VGS, GATE TO SOURCE VOLTAGE (V) o TA = -55 C 25 C 20 o 125 C 15 10 5 0 VGS = 0V 10 o TA = 125 C 1 o 25 C 0.1 o -55 C 0.01 0.001 0.0001 1.5 2 2.5 3 3.5 4 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 15. Transfer Characteristics. 4.5 0 0.2 0.4 0.6 0.8 1 1.2 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature. FDS4895C Rev C(W) FDS4895C Typical Characteristics: Q2 (P-Channel) 1400 ID = -4.4A VDS = -10V 1200 -20V -30V 6 4 1000 800 600 400 COSS 2 200 CRSS 0 0 0 5 10 15 20 25 0 5 10 Qg, GATE CHARGE (nC) 15 25 30 35 40 Figure 18. Capacitance Characteristics. 50 RDS(ON) LIMIT P(pk), PEAK TRANSIENT POWER (W) 100 100µ 10 1s 10s 1 1ms 10ms 100ms DC VGS = -10V SINGLE PULSE o RθJA = 135 C/W 0.1 o TA = 25 C 0.01 0.1 1 10 100 SINGLE PULSE RθJA = 135°C/W TA = 25°C 40 30 20 10 0 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) -VDS , DRAIN-SOURCE VOLTAGE (V) Figure 19. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 20 -VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 17. Gate Charge Characteristics. -ID , DRAIN CURRENT (A) f = 1 MHz VGS = 0 V CISS 8 CAPACITANCE (pF) -VGS , GATE-SOURCE VOLTAGE (V) 10 Figure 20. Single Pulse Maximum Power Dissipation. 1 D = 0.5 RθJA(t) = r(t) * RθJA 0.2 0.1 o RθJA = 135 C/W 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1, TIME (sec) Figure 21. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. FDS4895C Rev C(W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST® ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DOME™ HiSeC™ EcoSPARK™ I2C™ E2CMOS™ i-Lo™ EnSigna™ ImpliedDisconnect™ FACT™ IntelliMAX™ FACT Quiet Series™ Across the board. Around the world.™ The Power Franchise® Programmable Active Droop™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerEdge™ PowerSaver™ PowerTrench® QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ μSerDes™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic® TINYOPTO™ TruTranslation™ UHC™ UltraFET® UniFET™ VCX™ Wire™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I16