DISCRETE SEMICONDUCTORS DATA SHEET BF1100WR Dual-gate MOS-FET Product specification File under Discrete Semiconductors, SC07 Philips Semiconductors 1995 Apr 25 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR FEATURES PINNING • Specially designed for use at 9 to 12 V supply voltage • Short channel transistor with high forward transfer admittance to input capacitance ratio • Low noise gain controlled amplifier up to 1 GHz • Superior cross-modulation performance during AGC. PIN SYMBOL DESCRIPTION 1 s, b 2 d drain 3 g2 gate 2 4 g1 gate 1 source APPLICATIONS • VHF and UHF applications such as television tuners and professional communications equipment. d handbook, halfpage 3 4 DESCRIPTION g2 Enhancement type field-effect transistor in a plastic microminiature SOT343R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. g1 2 1 Top view s,b MAM192 CAUTION Marking code: MF. The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. Fig.1 Simplified outline (SOT343R) and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage − − 14 V ID drain current − − 30 mA Ptot total power dissipation − − 280 mW Tj operating junction temperature − − 150 °C yfs forward transfer admittance 24 28 33 mS Cig1-s input capacitance at gate 1 − 2.2 2.6 pF Crs reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz − 2 − dB 1995 Apr 25 2 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 14 V ID drain current − 30 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current Ptot total power dissipation Tstg Tj − ±10 mA − 280 mW storage temperature −65 +150 °C operating junction temperature − +150 °C see Fig.2; up to Tamb = 50 °C; note 1 Note 1. Device mounted on a printed-circuit board. MLD156 MLD180 40 300 handbook, halfpage Y fs (mS) Ptot (mW) 30 200 20 100 10 0 0 0 50 100 50 150 200 Tamb ( oC) Fig.3 Fig.2 Power derating curve. 1995 Apr 25 3 0 50 100 150 T j ( oC) Forward transfer admittance as a function of junction temperature; typical values. Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth j-a thermal resistance from junction to ambient note 1 350 K/W Rth j-s thermal resistance from junction to soldering point Ts = 91 °C; note 2 210 K/W Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 1 mA 13.2 20 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 1 mA 13.2 20 V V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 9 V; ID = 20 µA 0.3 1 V VG2-S = 4 V; VDS = 12 V; ID = 20 µA 0.3 1 V VG1-S = 4 V; VDS = 9 V; ID = 20 µA 0.3 1.2 V VG1-S = 4 V; VDS = 12 V; ID = 20 µA 0.3 1.2 V VG2-S = 4 V; VDS = 9 V; RG1 = 180 kΩ; note 1 8 13 mA VG2-S = 4 V; VDS = 12 V; RG1 = 250 kΩ; note 2 8 13 mA VG2-S(th) IDSX gate 2-source threshold voltage drain-source current IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 12 V − 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 12 V − 50 nA Notes 1. RG1 connects gate 1 to VGG = 9 V; see Fig.26. 2. RG1 connects gate 1 to VGG = 12 V; see Fig.26. 1995 Apr 25 4 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL yfs PARAMETER CONDITIONS forward transfer admittance input capacitance at gate 1 Cig1-s input capacitance at gate 2 Cig2-s drain-source capacitance Cos MIN. TYP. MAX. UNIT pulsed; Tj = 25 °C VDS = 9 V 24 28 33 mS VDS = 12 V 24 28 33 mS VDS = 9 V − 2.2 2.6 pF VDS = 12 V − 2.2 2.6 pF VDS = 9 V − 1.6 − pF VDS = 12 V − 1.4 − pF VDS = 9 V − 1.4 1.8 pF VDS = 12 V − 1.1 1.5 pF VDS = 9 V − 25 35 fF VDS = 12 V − 25 35 fF VDS = 9 V − 2 2.8 dB VDS = 12 V − 2 2.8 dB f = 1 MHz f = 1 MHz f = 1 MHz reverse transfer capacitance f = 1 MHz Crs F f = 800 MHz; GS = GSopt; BS = BSopt noise figure MLD157 MLD158 120 0 handbook, halfpage handbook, gain halfpage Vunw (dBµV) reduction (dB) 10 (1) 110 (2) 20 100 30 90 40 80 50 0 1 2 3 4 0 10 20 30 VAGC (V) (1) RG = 250 kΩ to VGG = 12 V. (2) RG = 180 kΩ to VGG = 9 V. fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C. f = 50 MHz. Tj = 25 °C. Fig.5 Fig.4 1995 Apr 25 40 50 gain reduction (dB) Gain reduction as a function of the AGC voltage; typical values. 5 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.26. Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR MLD159 MLD160 20 20 handbook, halfpage handbook, halfpage ID (mA) 16 ID (mA) 16 V G1 S = 1.4 V 1.3 V 1.2 V 12 V G2 S = 4 V 3 V 2.5 V 2V 12 1.1 V 1.5 V 8 8 1.0 V 0.9 V 4 4 1V 0 0 0 4 8 12 0 16 0.4 0.8 1.2 1.6 2.0 V G1 S (V) V DS (V) VG2-S = 4 V. Tj = 25 °C. VDS = 9 to 12 V. Tj = 25 °C. Fig.6 Output characteristics; typical values. Fig.7 Transfer characteristics; typical values. MLD162 MLD161 250 40 handbook, halfpage handbook, halfpage I G1 (µA) V G2 S = 4 V y fs (mS) 200 3.5 V V G2 S = 4 V 3.5 V 30 3V 150 3V 20 100 2.5 V 10 2V 50 2.5 V 2V 0 0 0 1 2 V G1 S (V) 0 3 10 VDS = 9 to 12 V. VDS = 9 to 12 V. Tj = 25 °C. Tj = 25 °C. Fig.8 1995 Apr 25 Gate 1 current as a function of gate 1 voltage; typical values. Fig.9 6 20 I D (mA) 30 Forward transfer admittance as a function of drain current; typical values. Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR MLD164 MLD163 16 20 handbook, halfpage handbook, halfpage ID (mA) R G1 = 100 kΩ ID (mA) 12 147 kΩ 15 180 kΩ 205 kΩ 8 249 kΩ 10 301 kΩ 402 kΩ 511 kΩ 4 5 0 0 0 20 40 60 I G1 (µA) 80 0 4 8 12 V GG = V DS (V) 16 VG2-S = 4 V. RG1 connected to VGG. Tj = 25 °C. VDS = 9 to 12 V. VG2-S = 4 V. Tj = 25 °C. Fig.11 Drain current as a function of gate 1 supply voltage (= VGG) and drain supply voltage; typical values; see Fig.26. Fig.10 Drain current as a function of gate 1 current; typical values. MLD165 12 MLD166 12 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 8 8 4 4 0 0 0 2 4 6 8 10 V GG (V) 0 4 8 V GG (V) 12 VDS = 9 V; VG2-S = 4 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. VDS = 12 V; VG2-S = 4 V. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.12 Drain current as a function of gate 1 voltage (= VGG); typical values; see Fig.26. Fig.13 Drain current as a function of gate 1 voltage (= VGG); typical values; see Fig.26. 1995 Apr 25 7 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR MLD167 50 MLD168 50 handbook, halfpage handbook, halfpage I G1 (µA) 40 I G1 (µA) 40 V GG = 9 V V GG = 12 V 11 V 8V 10 V 7V 30 9V 30 8V 6V 7V 5V 20 20 4V 10 10 0 0 0 2 4 V G2 S (V) 6 0 2 4 V G2 S (V) 6 VDS = 9 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. VDS = 12 V. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.14 Gate 1 current as a function of gate 2 voltage; typical values. Fig.15 Gate 1 current as a function of gate 2 voltage; typical values. MLD169 MLD170 16 16 handbook, halfpage handbook, halfpage ID (mA) ID (mA) V GG = 9 V 12 12 V GG = 12 V 8 11 V 10 V 9V 8V 7V 8V 7V 6V 8 5V 4V 4 4 0 0 0 2 4 V G2 S (V) 6 0 2 4 VDS = 9 V. VDS = 12 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.16 Drain current as a function of the gate 2 voltage; typical values; see Fig.26. 1995 Apr 25 V G2 S (V) 6 Fig.17 Drain current as a function of the gate 2 voltage; typical values; see Fig.26. 8 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR MLD181 10 2 handbook, halfpage MLD182 10 3 y is (mS) 10 3 ϕ rs (deg) y rs (µS) 10 2 10 ϕ rs b is 10 2 y rs 1 10 10 g is 10 1 10 102 f (MHz) 1 1 10 3 10 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. 102 f (MHz) 10 3 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.18 Input admittance as a function of frequency; typical values. MLD183 10 2 y fs MLD184 10 2 10halfpage handbook, yos (mS) ϕ fs (deg) y fs (mS) Fig.19 Reverse transfer admittance and phase as a function of frequency; typical values. bos 1 ϕ fs 10 10 10 1 gos 10 2 10 1 1 10 102 f (MHz) 10 3 VDS = 9 V; VG2 = 4 V. VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. ID = 10 mA; Tamb = 25 °C. Fig.20 Forward transfer admittance and phase as a function of frequency; typical values. 1995 Apr 25 102 f (MHz) 10 3 Fig.21 Output admittance as a function of frequency; typical values. 9 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR MLD185 10 2 handbook, halfpage MLD186 10 3 y is (mS) 10 3 ϕ rs (deg) y rs (µS) 10 2 10 ϕ rs b is 10 2 y rs 1 10 10 g is 10 1 10 102 f (MHz) 1 1 10 3 10 102 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.22 Input admittance as a function of frequency; typical values. MLD187 10 2 y fs MLD188 10 2 10 handbook, halfpage yos (mS) ϕ fs (deg) y fs (mS) Fig.23 Reverse transfer admittance and phase as a function of frequency; typical values. bos 1 ϕ fs 10 10 10 1 gos 10 2 10 1 1 10 102 f (MHz) 10 3 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. ID = 10 mA; Tamb = 25 °C. Fig.24 Forward transfer admittance and phase as a function of frequency; typical values. 1995 Apr 25 102 Fig.25 Output admittance as a function of frequency; typical values. 10 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR VAGC handbook, full pagewidth R1 10 k Ω C1 4.7 nF C2 R GEN 50 Ω R2 50 Ω C3 DUT 4.7 nF 12 pF L1 ≈ 450 nH RL 50 Ω C4 RG 4.7 nF VI VGG V DS For VGG = VDS = 9 V, RG = 180 kΩ. For VGG = VDS = 12 V, RG = 250 kΩ. Fig.26 Cross-modulation test circuit. 1995 Apr 25 11 MGC420 Philips Semiconductors Product specification Dual-gate MOS-FET Table 1 f (MHz) BF1100WR Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 10 mA s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 0.985 −3.9 2.618 175.1 0.001 137.9 1.000 −1.9 50 100 0.981 −7.3 2.602 170.5 0.001 80.4 0.999 −4.0 200 0.975 −14.4 2.577 160.7 0.002 74.0 0.995 −7.6 300 0.965 −21.6 2.555 151.6 0.002 79.3 0.994 −11.3 400 0.947 −28.3 2.513 141.8 0.003 80.5 0.992 −15.0 500 0.927 −34.9 2.449 133.4 0.003 82.8 0.988 −18.5 600 0.913 −41.7 2.339 124.6 0.003 78.9 0.984 −22.0 700 0.890 −47.9 2.361 115.4 0.003 80.6 0.982 −25.3 800 0.869 −54.0 2.302 106.4 0.003 93.9 0.979 −28.8 900 0.845 −59.7 2.228 97.6 0.003 104.8 0.976 −32.1 1000 0.823 −65.4 2.167 89.6 0.003 129.3 0.974 −35.5 Table 2 Table 3 f (MHz) Noise data: VDS = 9 V; VG2-S = 4 V; ID = 10 mA Γopt f (MHz) Fmin (dB) (ratio) (deg) 800 2.00 0.67 43.9 rn 0.89 Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID = 10 mA s21 s11 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) s12 ANGLE (deg) s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.985 −3.7 2.576 175.3 0.000 125.0 1.000 −1.6 100 0.980 −7.4 2.563 170.9 0.001 111.2 1.000 −3.3 200 0.973 −14.6 2.541 161.6 0.002 83.0 0.997 −6.4 300 0.962 −21.5 2.519 152.9 0.002 85.2 0.996 −9.3 400 0.946 −28.5 2.479 143.5 0.003 79.4 0.995 −12.4 500 0.929 −35.0 2.419 135.5 0.003 78.2 0.991 −15.3 600 0.912 −41.6 2.373 127.2 0.003 80.0 0.989 −18.1 700 0.895 −47.8 2.336 118.7 0.003 83.4 0.987 −20.9 800 0.868 −53.8 2.284 110.0 0.003 91.3 0.985 −23.7 900 0.845 −59.8 2.213 101.6 0.003 95.9 0.983 −26.5 1000 0.823 −65.7 2.160 94.1 0.003 112.2 0.981 −29.3 Table 4 Noise data: VDS = 12 V; VG2-S = 4 V; ID = 10 mA Γopt f (MHz) Fmin (dB) (ratio) (deg) 800 2.00 0.66 43.3 1995 Apr 25 12 rn 0.97 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR PACKAGE OUTLINE 1.00 max 0.2 M A 0.1 max 0.4 0.2 0.2 M B 0.2 3 4 A 1.35 1.15 2.2 2.0 2 0.3 0.1 1 0.25 0.10 0.7 0.5 1.4 1.2 2.2 1.8 B Dimensions in mm. Fig.27 SOT343R. 1995 Apr 25 13 MSB367 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Apr 25 14