STV1602A SERIAL INTERFACE TRANSMISSION DECODER BUILT-IN AUTOMATIC EQUALIZER FOR UP TO 30dB ATTENUATION AT 135MHz (TYPICALLY 300m OF HIGH-GRADE COAXIAL CABLE), PLL CIRCUIT FOR RECLOCKING, AND SERIAL-PARALLEL CONVERSION CIRCUIT. THIS SERIAL TRANSMISSION DECODER REQUIRES ONLY FEW EXTERNAL COMPONENTS. OTHER RELATED IC’s INCLUDE : STV1601A, A SERIAL TRANSMISSION ENCODER (PARALLEL-TO-SERIAL CONVERSION) STV1389AQ COAXIAL CABLE DRIVER . . . . . .. . . .. . .. .. PGA37 (Ceramic Package) STRUCTURE Hybrid IC ORDER CODE : STV1602A APPLICATIONS SERIAL DATA TRANSMISSION DECODER 100 to 270 Mb/s PCK SYN EVR RSE V EE GND AIY AIX PIN CONNECTIONS GND APPLICATIONS EXAMPLES Serial data transmission of digital television signals 525-625 lines 4:2:2 component 270Mb/s (10-bit) 4*fsc PAL composite 177Mb/s (10-bit) 4*fsc NTSC Composite 143Mb/s (10-bit) FUNCTIONS 27 26 25 24 23 22 21 20 19 QFS 28 18 D0 CX 29 17 D1 GND 30 16 D2 MON 31 15 D3 ADS 32 14 D4 DIX 33 13 D5 DIY 34 12 D6 DPR 35 11 D7 10 D8 3 4 5 6 7 SX QSW TN1 VEE 8 9 D9 2 VEE 1 SY 36 37 ESI GND FV ESO Cable equalizer (maximum gain : 30dB at 135MHz) PLL for serial clock generation Reclocked repeater output (active loop through) Descrambler : modulo-2 multiplication by G(x) = (x9 + x4 + 1) (x + 1) Parallel-to-serial conversion Sync monitor output Eye pattern monitoring Input signal detector The STV1602A is a Hybrid IC decoder which converts serial data coming from a serial transmission line into parallel data. December 1992 1601A-01.EPS DESCRIPTION 1/22 STV1602A PIN DESCRIPTION Pin Symbol No Equivalent Circuit Description I/O Reclocked serial data output in differential mode. SX and SY are disabled when TN1 is set High. In this case, SX is set High and SY is set Low H L O To be connected to GND I Adjustment of VCO Free running frequency : VEE level gives the lowest frequency. To adjust it, set TN1 High. I Standard Min. Typ. Max. Unit GND SY 30Ω 30Ω 3 4 VR3 4 SX 2kΩ 145Ω 2kΩ VEE 1602A-02.EPS 3 -1.6 -2.4 V V -3.2 V GND 5 QSW (GND) 1kΩ 36 5 10kΩ FV 1602A-03.EPS 36 10kΩ V EE GND 1kΩ Output of phase comparator : must be connected to ESI with the shortest distance 1 ESO 2kΩ V EE 2/22 O 2kΩ 1602A-04.EPS 1 1602A-01.TBL 1kΩ STV1602A PIN DESCRIPTION (continued) Pin Symbol No 9 to 18 D9 to D0 Equivalent Circuit Description GND 600Ω 600Ω 300Ω I/O Parallel data output H L O Parallel clock output (rising edge at data center) H L O Data output reference potential Standard Min. Typ. Max. Unit -0.8 -1.6 V V -0.8 -1.6 V V O -1.2 V Equalizer differential input I -2.0 V To be left open I -4.6 V Equalizer detector output; Input signal : absent present O -2.4 -2.0 V V 21 9 19 PCK VR3 18 210Ω 1602A-05.EPS 210Ω VEE 21 EVR GND 26 AIX 300Ω 26 10kΩ 10kΩ 25 4kΩ AIY 4kΩ VEE 1602A-06.EPS 25 3kΩ GND 2kΩ 28 NC 1kΩ 28 CX 16kΩ 2kΩ 2kΩ VEE 1602A-07.EPS 29 3/22 1602A-02.TBL 29 STV1602A PIN DESCRIPTION (continued) Pin Symbol No Equivalent Circuit Description I/O Standard Min. Typ. Max. Unit GND 1kΩ 31 31 500Ω MON 500Ω O Serial data input selection High : Digital input DIX/DIY Low : Equalizer input H L I Serial data digital differential input I 15 mV (pp) 1602A-08.EPS V R3 Equalizer monitor output. Connect 75Ω resistor between MON-GND. Observe using a 50Ω input oscilloscope at the 75Ω coaxial cable. 500Ω V EE GND 2kΩ 32 32 2kΩ ? VR2 ADS -0.5 -5 V V -1.6 V V 1602A-09.EPS V R3 2kΩ VEE GND 500Ω 33 500Ω DIX VR1 33 V R3 DIY 500Ω VEE 4/22 1602A-10.EPS 34 Selected when ADS is High. H L -1.0 1602A-03.TBL 34 STV1602A PIN DESCRIPTION (continued) Pin Symbol No Equivalent Circuit Description I/O PLL error signal input : must be connected to ESO with the shortest distance i Serial data input activation High : Input disabled (VCO free running condition). Low : Input enabled. During switch-on phase, by temporarily hold High for quick start-up I State changes at each TRS Sync word 3FFH 000H 000H H L O Standard Min. Typ. Max. Unit GND 37 ESI -3.2 V 1602A-11.EPS 37 2kΩ V EE GND 2kΩ 20kΩ 6 TN1 12kΩ 4kΩ VEE GND V -4.0 V -4.0 V V 1602A-12.EPS 6 -1.0 V CC 4kΩ 20 2kΩ VEE 2kΩ -1.0 1602A-04.TBL SYN 1602A-13.EPS 20 5/22 STV1602A PIN DESCRIPTION (continued) Pin Symbol No Equivalent Circuit Description I/O Serial data detection output. When there is an input signal at the input side selected through ADS, this pin goes High. At no signal, it goes Low. H L i.e. - present : High - absent : Low O Selects VCO frequency range H : High range 140 to 270MHz L : Low range 100 to 145MHz H L I Standard Min. Typ. Max. Unit GND 1kΩ 35 1kΩ DPR -1.0 -4.0 V V -4.0 V V 1602A-14.EPS 35 6kΩ V EE GND 2kΩ 10kΩ 22 10kΩ 10kΩ V EE 7 23 VEE 8 VEE -5V supply I/O buffer, PLL equalizer -5V Supply Logic part 2 24 27 30 GND GND 6/22 -0.4 -5.2 -5.0 -4.8 V -5.2 -5.0 -4.8 V 1602A-05.TBL RSE 1602A-15.EPS 22 STV1602A BLOCK DIAGRAM GND EVR SYN PCK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 21 20 19 18 17 16 15 14 13 12 11 10 9 2 GND 24 Parallel clock GND 27 TIMING GENERATOR VE E 7 10-BIT LATCH GND 30 ECL OUT SYNC REFERENCE VOLTAGE 23 V E E 30-BIT SHIFT REGISTER DETECTOR 9 4 X + X + 1 DESCRAMBLER AIX 26 AUTOMATIC AIY 25 CABLE EQUALIZER DATA DETECTOR 8 VE E 4 SX 3 SY NRZI TO NRZ Reclocked serial data QFS 28 Serial clock INPUT DATA RELAY SELECT 33 34 DIX DIY EDGE DETECTOR PHASE DETECTOR 32 6 35 36 ADS TN1 DPR FV 1 VCO 22 RSE Value Unit 1602A-16.EPS CX 29 MON 31 37 ESO ESI Symbol Parameter VEE Supply Voltage VIN Input Voltage IOUT Output Current Toper Operating Temperature Tstg Storage Temperature PD Allowable Power Dissipation -6 V VEE to 0 V -30 mA 0 to 65 o -50 to 125 o C C 2.0 W 1602A-06.TBL ABSOLUTE MAXIMUM RATINGS (TA = 25oC) Symbol Parameter VEE Supply Voltage Toper Operating Temperature Value Unit -4.8 to -5.2 V 0 To 65 oC 7/22 1602A-07.TBL RECOMMENDED OPERATING CONDITIONS STV1602A ELECTRICAL CHARACTERISTICS (VEE = -5V, TA = 25oC unless otherwise specified) Symbol Parameter Test Conditions Test Circuit Min. TYp. Max. Unit DC CHARACTERISTICS IEE VIH VIL VIH VIL VIH VIL IIH IIL VIH VIL VOH VOL VM VOH VOL VOH VOL Supply Current VEE = 5V Figure 4 Pin ADS Input Voltage Pin RSE 185 -0.4 -1.5 Figure 10 -0.4 -4.0 -1.0 Pin DIX, DIY Input Current Pin DIX, DIY Figure 5 Input Voltage Pin TN1 Figure 9 -1.0 -1.0 -4.6 -0.8 -1.6 -1.2 Pin PCX, Dn R P = 1kΩ Pin EVR, RP = 1kΩ Output Voltage Pin DPR, SYN IOH = -10µA, IOL = +10µA -1.6 5.0 +1.0 Figure 7 Figure 8 -1.0 -4.0 -1.6 -2.4 Pin SX, SY R P = 220Ω mA V V V V V V µA µA V V V V V V V V V fMAX1 fMIN1 fMAX2 fMIN2 fHP1 fLP1 fHP2 fLP2 fHP3 fLP3 fOP1 fOP2 VCO VCO VCO VCO Max. Oscillation Frequency 1 Min. Oscillation Frequency 1 Max. Oscillation Frequency 2 Min. Oscillation Frequency 2 PLL Pull in Range PLL Generator Frequency RSE RSE RSE RSE = ”H” = ”H” = ”L” = ”L” 30.0 Figure 6 14.0 15.0 10.0 f signal = 270MHz RSE = ”H” 27.7 f signal = 177MHz RSE = ”H” 18.5 25.5 16.8 Figure 3 f signal = 143MHz RSE = ”H” 15.0 RSE = ”H” RSE = ”L” 14.0 10.0 13.3 27.0 14.5 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 1602A-08.TBL AC CHARACTERISTICS Frequency at 1/10 the value of signal frequency (Tested through Pin PCK) Symbol tr tf tr tf td 8/22 Parameter Rise Time Fall Time Rise Time Fall Time Delay Time Test Conditions Test Circuit Min. Pins PCK, Dn R P = 1kΩ Pins SX, SY R P = 220Ω Pins PCK, Dn Figure 3 -3 Typ. 0.8 1.4 0.7 0.7 Max. +3 Unit nsec nsec nsec nsec nsec 1602A-09.TBL SWITCHING CHARACTERISTICS (VEE = -5V, TA = 25oC unless otherwise specified) STV1602A Symbol VMAX GMAX CIN RIN Parameter Equalizer Max. Input Voltage Equalizer Max. Gain Input Capacity Input Resistance Test Conditions Pins AIX, AIY Test Circuit Min. 0.88 Figure 3 Typ. Max. 30 Pins AIX, freq = 100MHz Pins AIX, freq = 100MHz Unit Vp-p dB pF Ω 1602A-10.TBL EQUALIZER (VEE = -5V, TA = 25oC unless otherwise specified) Figure 1 : tr, tf, tc, td Definition tc t c /2 t c /2 80% 1602A-17.EPS / 1602A-18.EPS Dn 20% 50% PCK tf td SYN pin guaranteed operation range. SYNC pin and serial to parallel conversion operate normally within the frequency and ambient temperature ranges according to the following considerations. Reclocked output. STV1602A may be used as a repeater. The reclocked output, providing characteristics almost identical to the serial output of STV1601A is available from SX (Pin 4) and SY (Pin 3). When the reclocked output is used, it is recommended not to use simultaneously use the parallel outputs (data and clock) in order to avoid possible logic errors caused by an excessively high temperature which may result from additional power dissipation created by the reclocked output circuit under certain environnmental conditions. If, for the sake of a design convenience, both reclocked and parallel outputs are to be used, the ambient temperature has to be kept as low as possible or, at least, the airflow around STV1602A must be carefully considered. In addition, it is recommended to put 220Ω resistors on all parallel outputs including the clock as shown in Figure 2. This reduces the magnitude of the spike current resulting from the parallel output circuit inside the chip and helps reduce the probability of logic errors at high temperature. Power saving in repeater mode Since the parallell output is not always required for tw a reclocked repeater, the chip has been designed such that the uncessary parallel logic circuit can be disabled by disconnecting Pin 8, one of VEEs, from the power supply. With this arrangement the power dissipation is reducible to about 45 percent of that of the fully functional mode. In practice, a test switch should be provided so that some parallel signals may be available during adjustment procedures as shown in Figure 2. Figure 2 : A Suggested Parallel Clock / Data Output Circuit EVR 21 1kΩ 220Ω 1kΩ 220Ω PCK 19 D0 18 ECL line drivers or ECL/TTL translators 1kΩ STV1602A 220Ω V EE D9 9 8 1kΩ 0.1µF Power save SW V EE (-5V) 1602A-19.EPS tr 9/22 10/22 1602A-20.EPS SIGNAL GENERATOR HP8180A 2 5 32 29 V CC -5V B -5V 28 33 SW1 RSE FV 4 3 1 A 150pF 22kΩ -5V 0.22µ H 0.1 220Ω 10µF/10V -5V 220Ω -5V PLL LOCK DETECTOR 1kΩ B LOW RANGE A HIGH RANGE -5V 220Ω 220Ω 0.1 220Ω ON : AF FREQUENCYADJUST SW2 FREQUENCYMONITOR VCO RANGE SELECT TN1 35 TRP 34 SY SX LST PCK 36 N.C. 37 26 V EE 0.1 10/16V V EE -5V 27 STV1601A GND V R1 10kΩ 25 D0Y 24 D0X 23 D1Y 22 D1X 21 D2Y 20 D2X 19 D3Y 18 D3X 17 D4Y 16 D4X 15 D5Y 14 D5X 13 D6Y 12 D6X 11 D7Y 10 D7X 9 D8Y 8 D8X 7 D9Y 6 D9X 31 PCY 30 PCX VCO FREQUENCY ADJUST 0.1 V R - .3V 0.1 0.1 220Ω 0.1 150Ω VCO RANGE SELECT -5V 150Ω STV1389AQ 0.1 0.1 75Ω 75Ω -5V 2 1 SERIAL OUT INPUT SELECT A CABLEINPUT B DIGITAL INPUT 0.1 220Ω B A -5V 0.1 220Ω 220Ω 41pF 41pF 100Ω 10µF SW2 SX SY 2 V R2 10kΩ 27 1 30 V R2 10kΩ 37 VCO FREQUENCY ADJUST 22 -5V 0.1 35 23 0.1 -5V 100kΩ 36 FV 8 -5V 0.1 10/16V 10µF 22kΩ QSW 35 9 -5V 0.1 5 TN1 6 D9 D8 10 D7 11 D6 12 D5 13 D4 14 D3 15 D2 16 D1 17 D0 18 PCK 19 EVR 21 -5V LED 10µF 0.1 -5V 0.1 MONITOR SIGNAL ANALYZER HP8182A 330Ω LED ON : AF FREQUENCY ADJUST SW3 1kΩ x 8 22kΩ -5V 1kΩ x 4 TRS DETECTOR SIGNAL FREQENCY 330Ω SW3 ON : AF FREQUENCY ADJUST 0.1 1kΩ FREQENCY MONITOR TRS DETECTOR SIGNAL SYN 20 7 DPR VEE QSW 5 TN1 6 PCK 19 D.U.T. STV1602A GND 24 -5V 100kΩ 0.1 10/16V SYN 20 7 DPR RSE ESO ESI 34 DIY 33 DIX 25 AIY 26 AIX 28 QFS 31 MON 29 CX 32 ADS 4 3 VCO FREQUENCY ADJUST 220Ω 73Ω SERIAL IN 10kΩ -5V 36 37 1 22 FV 8 V EE STV1602A GND RSE ESO ESI 34 DIY 0.1 24 27 30 23 VCO RANGE SELECT 220Ω 220Ω 33 DIX 32 ADS 2 -5V STV1602A Figure 3 :Test Circuit Diagram Example STV1602A Figure 4 V EE -5V I EE A 10/16V 0.1 0.1 2 24 27 30 23 8 GND 1 7 V EE 1kΩ EVR 21 PCX 19 D0 18 STV1602A ESO 1kΩ 1kΩ 1kΩ D9 9 -5V 37 ESI 0.1µF 220Ω ADS RSE FV 32 22 36 QSW TN1 5 6 10µF SW1 10kΩ SW1 POSITION ON 1602A-21.EPS 10kΩ -5V -5V Figure 5 -5V 10/16V 0.1 V1 V2 A1 A2 -0.8V -1.6V -1.6V -0.8V I IH I IL I IL I IH 0.1 2 24 27 30 23 GND 8 7 V EE 33 DIX 34 DIY 11 12 V1 V2 1 STV1602A TN1 ADS RSE FV QSW 32 22 36 5 6 ESO 37 ESI 1602A-22.EPS 10kΩ -5V 11/22 STV1602A Figure 6 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 GND 7 FREQUENCY MONITOR VEE 1kΩ EVR 21 1 ESO PCX 19 1kΩ D0 18 1kΩ STV1602A 1kΩ D9 9 -5V 37 ESI 0.1µF 22kΩ ADS RSE 32 22 QSW TN1 5 36 FV 6 10µF SW2 SW1 B A SW1 SW2 VCO RANGE 10kΩ -5V POSITION A B ON ON HIGH LOW 1602A-23.EPS 10kΩ -5V Figure 7 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 7 10µF 29 CX Serial IN GND V EE DPR 35 33 DIX 41pF 73Ω V 270Mb/s SIGNAL I IL STV1602A 41pF 34 DIY ESO 37 ESI ADS 32 TN1 RSE FV QSW 22 36 5 10kΩ -5V 12/22 6 V IL V OH 10µA V OL -10µA SERIAL IN INPUT OPEN 1602A-24.EPS 1 STV1602A Figure 8 -5V 10/16V 0.1 0.1 2 24 27 30 23 8 GND 7 V EE 33 DIX ONE - SHOT TRS GENERATOR 34 DIY STV1602A 1 SYN 20 ESO V IL V VOH VOL IL 10µA -10µA 37 ESI FV ADS RSE 32 22 QSW TN1 36 5 10kΩ 6 22kΩ 10µF/16V SW3 1602A-25.EPS 10kΩ -5V -5V -5V Figure 9 -5V 10/16V 0.1 0.1 2 24 27 30 23 GND 6 V1 8 7 V EE TN1 33 DIX 34 DIY -5V 1 D0 18 V ESO 37 ESI ADS RSE FV QSW 32 22 36 5 10kΩ 1602A-26.EPS 10kΩ STV1602A -5V 13/22 STV1602A Figure 10 -5V 10/16V 0.1 0.1 2 24 27 30 23 GND 8 7 V EE FREQUENCY MONITOR 22 RSE V1 33 DIX 1kΩ 34 DIY 1 PCX 19 -5V 0.1 ESO 37 ESI ADS FV QSW TN1 32 36 5 6 22kΩ 10µF/16V SW3 1602A-27.EPS 10kΩ -5V -5V STV1602A GENERAL As shown in the overall block diagram on page 7, STV1602Ais composed of the following functions : (1) Analog input as a primary input with automatic equalizer to meet the loss characteristics of coaxial cable (2) Digital input as a secondary input to receive the encodedsignal from short distances within the same printed circuit board or the same equipment (3) Phase locked loop (PLL) variable oscillator (4) Reclocked serial output (5) Serial descrambler (6) SYNC detector (7) Deserializer (8) Parallel output buffer amplifiers (9) Three diagnostic signals : eye monitor, SYNC monitor and input data presence monitor A brief explanation of each function is given in the following sections. 1. Cable equalizer Transmission of high speed digital data by means of coaxial cable can greatly attenuate high frequency components.According to the cable length, received signals can widely differ from those sent; in such conditions, clock extraction and data identification could be difficult. 14/22 The cable equalizer overcomes this problem. The IC performs up to 30dB (typical) equalization at 135MHz, typically 300m of high-grade coaxial cable. The equalization is automatically performed according to the coaxial cable length. The input signal can be delivered either through a transformer or through a capacitor. When the digital input is selected, the equalizer is disabled. Typical characteristics of the equalization are given in Figure 31. Figure 11 : Equalizer Capacitor Coupling Input Circuit Monitor OUT 31 MON 100Ω 30 GND 29 CX STV1602A 10µF Serial IN 26 AIX 47pF 75Ω 25 AIY 47pF 1602A-28.EPS -5V STV1602A STV1602A Figure 15 : AGC Time Constant 10µF/16V Serial IN 26 AIX 2.2kΩ 25 AIY 1602A-29.EPS 29 CX STV1602A 75Ω In both input circuit configurations, a consideration is required in a practical design to obtain a sufficient return-loss (at least 15dB over a frequency range of 5MHz to the bit rate frequency used). To achieve this, it is effective to add a small inductance in series with the 75Ω termination resistor. Figure 13 shows an implementation example. Figure 13 : An example of technique to improve the return-loss figure for the capacitor coupling input case Printed circuit inductance 1mm Coaxial Cable 47pF AIY Pin 25 47pF AIX Pin 26 75 1602A-30.EPS R = 6mm Terminator ( Through-holeto a ground plane) MON Pin (31) Equalized signals can be observed at this pin by connecting an oscilloscope input (50Ω). Figure 14 : Equalized Waveforms Monitoring 50Ω coaxial cable To 50Ω input oscilloscope MON 35 75Ω GND 30 CX Pin (29) Equalizer AGC time constant Connect a 10µF capacitor in serial with 2.2kΩ resistor between this pin and GND in order to obtain stable operation at all times. According to input signals, voltage changes from -2V to -2.4V can occur. 1602A-31.EPS STV1602A STV1602A 2. Digital input The serial data input can be used without the equalizer. DIX (Pin 33) and DIY (Pin 34) are differential inputs for ECL signals. From these pins, input signals are differentially amplified, therefore with no input signals, the data detectionsignals could go High and erroneousdata would be transferred to the parallel output. To avoid this, a voltage level conforming to ECL specifications must be applied between DIX and DIY pins. Also, while the analog input is in use, digital input must be kept ”quiet” in order to avoid possible errors caused by cross-talk. This cross-talk problem naturally gets most severe when the analog input cable length is close to the limit of the transmission capability. 3. Serial input selection Selection of the serial input is performed by ADS (Pin 32); when High the digital input is enabled; this input can be used for very short transmission lines. When Low, the equalizerinput is enabled;this input must be used for long transmission lines. 4. PLL In order to extract clock signals from the equalized serial data, it is processed to generate edge signals which are sent to the phase comparator. When the PLL is locked, the identifier clock (D flipflop) will be in phase with the incoming clock. The identifier clock rises at the center of the data period for easy identification. The PLL detailed block diagram is shown in Figure 16. ESI is the VCO control input (Pin 37). Normally, the phase comparator output ESO (Pin 1) is connected to ESI. Since the VCO employed has a very high sensitivity, those two nodes must be connected with a shortest distance and a minimum area of conductor 15/22 1602A-32.EPS Figure 12 : Equalizer Transformer Input Circuit STV1602A variable resistor connected between FV and VEE. RSE (Pin 22) selects the VCO frequency range; High : 140 to 270MHz, Low : 100 to 145MHz. When TN1 (Pin 6) is set High, input signals are disabled and the VCO free runs. The capacitor connected between TN1 and GND avoids mislocking problem when the power supply is switched on. on the printed circuit board. Encircling those two nodes by a ground guarding is an efficient method to prevent errors caused by an ”antenna effect”. Through FV (Pin 35) one can adjust the free running frequency; when the FV Voltage is equal to VEE, the free running frequency is the lowest; the voltage adjustment can be performed by using a Figure 16 : Serial Data Input and PLL NZRI to NRZ conversion Descrambler SX F DC E SY D From equalizer A Phase Comparator DL ESO ESI In In 16/22 Data (NRZ) D3 D4 D5 D6 D7 D8 D9 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Out 1602A-34.EPS Clock D D2 Figure 19 : Actual x9 + x4 + 1 Descrambler Figure 17 : NRZI to NRZ conversion Data (NRZI) D1 Out 5. NRZI To NRZ conversion, descrambler Serial data delivered by the identifier is available in differential mode, SX (Pin 4) and SY (Pin 3). At the same time, to recover the original data, NRZI to NRZ conversion and descrambling are performed. PLL FV Figure 18 : x9 + x4 + 1 Descrambler Data detection Serial data edges are detected and go through low pass filter. The processed signal is available at DPR (Pin 35).DPR goes High when an input signal is detected, otherwise it stays Low. The driving capability of this pin is weak. It is recommended to load it with a high impedance CMOS or equivalent. Serial Signal 1602A-33.EPS TN1 1602A-35.EPS ADS RSE C B DIX DIN VCO 6. Serial to parallel conversion After descrambling, serial data is sent to a 30-bit register to detect the sync word (TRS). When the sequence 111111111100000000000000000000is detected, sync word detection signal is output, the counter which divides the clock frequency by 10 is initialized and data is converted to parallel (10-bit word) to be output. 1602A-36.EPS DL STV1602A Each time the sync word is detected, SYN (Pin 20) changes state as shown in Figure 20. When a receiver using STV1602A is properly implemented and adjusted, the health of the implementation can be checked simply by looking at SYN (Pin 20) output while an encoded signal is present at the input. SYN is an output of a flip-flop which togglesat each detection of TRS at the SYNC detector. Since the 4:2:2 signal contains two kinds of TRSs, SAV and EAV, when the output of SYN is observed by an oscilloscope it looks like either case A or case B as shown in Figure 20 depending upon the initial condition of the Flip-Flop. When bit erros are occurring somewhere in the transmission path, SYN output is affected and looks like as shown in case C. Figure 21 illustrates the case for 4 fsc (D2 NTSC and PAL). Differing from the 4:2:2 case, SYN output has an equal mark and space ratio due to the periodic occurence (once per one TV line) of the TRS detection. However, transmission path bit errors will cause the SYN output to appear similar to the 4:2:2 case. If SYN signal is used other than for monitoring purposes, buffering similar to that of DPR is required due to the high impedance nature of SYN output. 7. Phase relation ship between parallel data and parallel clock Parallel data and clock are output so that the rising edge of the parallel clock is located at the center of the parallel data. Both parallel data and clock (nearly identical to that of single ECL) have DC levels depending on the temperature. In order to simplify the driving amplifier, a reference level (EVR) is available at Pin 21. PCX, Dn and EVR use pull down resistors (identical values). A peripheral circuit example is shown in Figure 23. Figure 24 shows a circuit to disable the parallel clock output. Figure 20 : SYNC Output in 4:2:2 Case (not to scale) 1 TV line 4:2:2 Data Stream E A V HBLK S A V Active Video E A V HBLK S A V Active Video E A V HBLK S A V Active Video E A V SYN output (case A) 1602A-37.EPS SYN output (case B) SYN output (case C) Figure 21 : SYNC Output in 4 fsc Case (not to scale) 1 TV line T R S Active Video + H- BLK T R S Active Video + H- BLK T R S Active Video + H- BLK 1602A-38.EPS 4 fsc DataStream SYN output 17/22 STV1602A Figure 22 : Phase Relation of Parallel Clock, Data and EVR Voltage Level Parallel clock Parallel data V OH 1601A-39.EPS EVR output voltage V OL with temperature. FV pin voltage remains almost constant regardless of temperature. Figure 25 shows an example of a temperature compensation circuit using a diode (transistor with C-B diode short-circuited) and a resistor between FV and VEE. PLL pull-in range (signal frequency 270, 177 and 143MHz) are given by Figures 32, 33 and 34. Figure 23 : Parallel Clock Data Output Circuit EVR 21 1kΩ PCK 19 1kΩ D0 18 1kΩ STV1602A D9 9 1602A-40.EPS 1kΩ 0.1µF V EE Figure 24 : A Circuit Example to Disable Parallel Clock CMOS inverter 10kΩ DPR 35 Figure 25 : VCO Temperature Compensation and Free Running Frequency Adjustment 0.1µF EVR 10kΩ 6 9. VCO free running frequency adjustment VCO free running frequency adjustment is performed at room temperature. If TN1 is set High, VCO is free running. Wait for 5 to 10 minutes after turning power supply ON (warm up time). While monitoring PCK (Pin 19) output, adjust the signal frequency (within ±1%) with the variable resistor connected between FV and VEE. 1kΩ PCK 21 0.1µF V EE 8. VCO temperature compensation and oscillation frequency adjustment. VCO oscillation frequency depends on the temperature as shown in Figures 29 and 30 ”Representative characteristics example”. Within the normal range of operation, frequency increases 18/22 10µF TN1 FV PCX 6 36 19 22kΩ Small signal transistor Frequency monitor 1kΩ 10kΩ VEE 1602A-42.EPS STV1602A 1602A-41.EPS STV1602A 1kΩ STV1602A Using particular codes to check overall performance Althrough the scrambling method employed effectively randomizes the incoming data and puts out a signal with a nearly uniform spectrum, there still exist some combinations of codes that give somewhat unfriendly conditions to the transmission path in terms of low frequency component or of a long run without any transitions. As shown in Figure 26, it is known that if the code words 300, 198 (hex, 10-bit) are given alternately to the parallel input of the encoder, the largest amount of DC component (nearly one TV line period) can be produced at some place with a certain probability (such a sequence is, however, destroyed when different data is input to the encoder). Even with such signals, error-free reception is possible with the STV1602Aif a proper implementation is made (refer to section 12 for a recommended circuit). Another particular combination of words, but with a different nature, is 200, 110 (hex, 10-bit) which can generate the sequence which is most vulnerable* to bit slip of nearly one TV line period. Figure 27 illustrates such a situation. Similar to the previous case, the worst sequence stops upon an arrival of a data other than the alternating 200, 110 at the input of the encoder. Figure 26 * Stricly speaking the longest isolated run is 38 clocks for 4:2:2 and 43 clocks for 4 fsc NTSC and PAL. However, the above sequence generally shows the most critical situation for the bit slip problem. Serial output when the worst sequence on DC component is occuring (case A) (case B) 300 (CO) 198 (66) 300 (CO) 1 bit Serial output when the worst sequence on bit slip is occuring 198 (66) 1 bit 19 bits 110 (44) 200 (80) 20 bits 110 (44) 200 (80) 20 bits 1602A-44.EPS Input data : hex, 10-bit (hex, 8-bit) 1602A-43.EPS Input data : hex, 10-bit (hex, 8-bit) Figure 27 : Particular Data words for checking PLL bit slip Note : Actually there exists a family of such particular code as above described. They will, h owe ve r, cre at e an id en tical sequence in the serial domain since the difference amongst the family is merely which bit is regarded as the start bit of a word. 19/22 20/22 1602A-45.EPS -5V -5V 10kΩ ECL Pair Tx line Serial IN Digital IN 2.2kΩ VCO Center freq. adj. Q1 10kΩ Eye monitoring 100Ω 10µF/16V AIX GND 1 37 ESI ESO 36 FV 35 DPR 34 DIY 2 GND ADS (Input select) 33 DIX 32 31 MON 30 GND 29 CX (open) 28 QFS 26 27 3 SY 47pF 75Ω 4 SX AIY 25 GND 24 VEE 23 5 10µF/16V QSW 6 TN1 21 7 VEE Test jumper 22kΩ Test point 8 V EE SYN 20 9 D9 D8 10 D7 11 D6 12 D5 13 D4 14 D3 15 D2 16 D1 17 D0 18 PCK 19 HIGH D1, D2 PAL RSE EVR (Rate select) 22 LOW D2 NTSC 10kΩ (DECODER MODULE) STV1602A 47pF -5V 0.1µ F -5V Parallel CK (-1.3V) Parallel data out (ECL) Serial IN (from cable) 1kΩ STV1602A Figure 28 : Application Circuit Example STV1602A REPRESENTATIVE CHARACTERISTICS EXAMPLE Figure 30 : VCO Oscillation Frequency versus FV Pin Voltage 45°C 45°C 65°C 220 5°C 85°C -15°C 140 0.80 0.90 1.00 1.10 1.20 1.30 FV pin Voltage (V) Figure 31 : An example of equalizer characteristics using 5C - 2V coaxial cable with respect to the gain for 0.5meter 85°C 140 45°C 130 5°C 65°C -15°C 120 85°C 110 100 0.90 1.00 1.10 1.20 1.30 Figure 32 : Pull-in Range and Free Run Frequency (270Mb/s) 30 15 10 5 29 High pull in 28 27 Free run 26 25 24 100 200 Frequency (MHz) 1602A-48.EPS 0 Figure 33 : Pull-in Range and Free Run Frequency (177Mb/s) Low pull in 23 -15 5 25 45 65 85 Ambient temperature (°C) 1602A-49.EPS Frequency (MHz) Gain (dB) RSE : ”L” 150 FV pin Voltage (V) 20 Figure 34 : Pull-in Range and Free Run Frequency (143Mb/s) 21 18 20 Frequency (MHz) High pull in 19 18 Free run 17 16 Low pull in 15 17 High pull in 16 15 14 Free run 13 Low pull in 12 14 -15 5 25 45 Ambient temperature (°C) 65 85 1602A-51.EPS Frequency (MHz) 25°C 11 -15 5 25 45 65 85 Ambient temperature (°C) 21/22 1602A-52.EPS 180 25°C VCO oscillation frequency (MHz) 260 1602A-46.EPS VCO oscillation frequency (MHz) RSE: ”H” 300 1602A-47.EPS Figure 29 : VCO Oscillation Frequency versus FV Pin Voltage STV1602A PACKAGE MECHANICAL DATA 37 PINS - CERAMIC PGA Dimensions in mm 3.8 25.4 0.5 0.2 Seating plane 1.15 0.15 1.2 0.46 0.1 0.05 4.2 2.54 x 9 = 22.86 0.25 Pin 28 Pin 36 Pin 37 2.032 max. 2.54 2.54 Pin 1 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 22/22 PM-PGA37.EPS Pin 10 Bottom View 25.4 2.54 x 9 = 22.86 0.5 0.25 Pin 19