www.fairchildsemi.com FSES0765RG Green Mode Fairchild Power Switch (FPSTM) for CRT Monitors Features • Burst Mode Operation to Reduce the Power Consumption in Standby Mode • External Pin for Synchronization • Wide Operating Frequency Range up to 130kHz • Internal Startup Circuit • Low Operating Current (Max:6mA) • Pulse by Pulse Current Limiting • Over Voltage Protection (Auto Restart Mode) • Over Load Protection (Auto Restart Mode) • Abnormal Over Current Protection (Auto Restart Mode) • Internal Thermal Shutdown (Auto Restart Mode) • Under Voltage Lockout • Internal High Voltage SenseFET (650V) Application OUTPUT POWER TABLE(3) 230VAC ±15%(2) PRODUCT Open FSES0765RG Frame(1) 90 W 85-265VAC Open Frame(1) 70 W Notes: 1. Maximum practical continuous power in an open frame design at 50°C ambient. 2. 230 VAC or 100/115 VAC with doubler. 3. The maximum output power can be limited by the junction temperature Typical Circuit • CRT Monitor Description FSES0765RG is a Fairchild Power Switch (FPS) specially designed for off-line SMPS of CRT monitors with minimal external components. This device combines a current mode PWM controller with a high voltage power SenseFET in a single package. The PWM controller features an integrated oscillator to be synchronized with the external sync signal, under voltage lockout, optimized gate driver and temperature-compensated precise current sources for the loop compensation. This device also includes various fault protection circuits such as over voltage protection, over load protection, abnormal over current protection and over temperature protection. Compared with discrete MOSFET and PWM controller solutions, FPS can reduce total cost, component count, size and weight while simultaneously increasing efficiency, productivity and system reliability. This device is well suited for cost effective CRT-monitor power supplies. Vo AC IN Vstr Drain FSES0765RG PWM VSync GND VFB Vcc External Sync signal Figure 1. Typical Flyback Application Rev.1.0.1 ©2005 Fairchild Semiconductor Corporation FSES0765RG Internal Block Diagram Vcc Vref Vth=8.5/9V Vstr 6 3 Drain 1 + ICH Vcc - Vref 0.8V Vcc good Burst 5V Sync detect 9V/12V (Normal) 50k 7V 5 Internal Bias 7.5V/12V (burst) 6V Vsync Turn-Off Vcc Idelay Turn-On OSC Vref IFB PWM VFB 4 Soft start (15ms) S Q R Q 2.5R R Gate driver LEB VSD Vcc 2 GND S Q R Q Vovp TSD Vcc good AOCP Figure 2. Functional Block Diagram of FSES0765RG 2 Vocp FSES0765RG Pin Definitions Pin Number Pin Name 1 Drain 2 GND This pin is the control ground and the SenseFET source. Vcc This pin is the positive supply input. This pin provides the internal operating current for both start-up and steady-state operation. 4 Vfb This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 7.5V, the over load protection triggers resulting in shutdown of the FPS. 5 Vsync This pin is for synchronized switching. For proper synchronization, a pulse signal should be applied on this pin. The internal MOSFET is turned on being synchronized by the falling edge of this signal. Vstr This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies the internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled. 3 6 Pin Function Description This pin is the high voltage power SenseFET drain connection. Pin Configuration TO-220-6L FSES0765RG 6. Vstr 5. Vsync 4. VFB 3. Vcc 2. GND 1. Drain Figure 3. Pin Configuration (Top View) 3 FSES0765RG Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain Voltage Vstr Voltage (1) Drain Current Pulsed Value Unit VDS 650 V Vstr 650 V IDM 15 A Continuous Drain Current (Tc = 25°C, with infinite heat sink) ID 7 A Continuous Drain Current (Tc=100°C, with infinite heat sink) ID 4.5 A EAS 570 mJ VCC 20 V Vsync -0.3 to 13 V Single pulsed Avalanche Energy (2) Supply Voltage Analog Input Voltage Range VFB -0.3 to 10 V Total Power Dissipation (Tc = 25°C , with infinite heat sink) PD 145 W Operating Junction Temperature TJ +150 °C Operating Ambient Temperature TA -25 to +85 °C TSTG -55 to +150 °C Storage Temperature Range Rthjc 0.86 °C/W BVpkg 3500 V ESD Capability, HBM Model (All pins except Vstr and Vfb) - 2.0 kV ESD Capability, Machine Model (All pins except Vstr and Vfb) - 300 V Thermal Resistance Drain to PKG Breakdown Voltage (3) Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. Lm=21mH, Vdd=50V, Rg=25Ω, starting Tj=25°C 3. 60Hz AC 4 Symbol FSES0765RG Electrical Characteristics (Continued) (Ta=25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SENSEFET SECTION Drain-Source Breakdown Voltage 650 - - V VDS = Max, Rating, VGS = 0V - - 250 μA VDS= 0.8*Max., Rating VGS = 0V, TC = 85°C - - 300 μA RDS(ON) VGS = 10V, ID = 2.3A - 1.4 1.6 Ω Coss VGS = 0V, VDS = 25V, f = 1MHz - 100 130 pF BVDSS Zero Gate Voltage Drain Current IDSS Static Drain-source on Resistance Output Capacitance VGS = 0V, ID = 250μA UVLO SECTION Vcc Start Threshold Voltage VSTART VFB=5V 11 12 13 V Vcc Stop Threshold Voltage (Normal operation) VSTOP VFB=5V 8.5 9 9.5 V Vcc Stop Threshold Voltage (Burst operation) VBSTOP VFB=0V 7 7.5 8 V OSCILLATOR SECTION Initial Frequency FOSC VFB=5 18 20 22 kHz Voltage Stability FSTABLE 11V ≤ Vcc ≤ 18V 0 1 3 % Maximum Duty Cycle DMAX VFB=5 48 55 62 % Minimum Duty Cycle DMIN - - 0 - % FEEDBACK SECTION Feedback Source Current (Normal operation) IFB VFB = 0V, Vcc=15V 0.7 0.9 1.1 mA Feedback Source Current (Burst operation) IBFB VFB = 0V, Vcc=8.7V 70 100 130 uA Feedback Voltage Threshold to Stop Switching VOFF 0V ≤ VFB ≤ 0.4V 0.2 0.3 0.4 V Shutdown Feedback Voltage VSD VFB ≥ 6.9V 7 7.5 8 V Shutdown Delay Current IDELAY VFB = 4V 1.6 2 2.4 μA VOVP Vcc ≥ 17V 18 19 20 V PROTECTION SECTION Over Voltage Protection (1) Over Current Protection Threshold Voltage (2) Thermal Shutdown Temp VAOCP - 0.9 1.0 1.1 V TSD - 140 - - °C Note: 1. These parameters, although guaranteed in design, are tested only in EDS (wafer test) process. 2. These parameters, although guaranteed in design, are not tested in mass production. 5 FSES0765RG Electrical Characteristics (Continued) (Ta=25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Sync SECTION Low Sync Threshold Voltage VSL High Sync Threshold Voltage VSH Sync blanking time TSYB Vcc=15V, VFB=5V 5.6 6 6.4 V 6.5 7 7.5 V 3 5 7 us 0.7 0.8 0.9 V 0.45 0.6 0.75 A 40 50 60 kHz BURST MODE SECTION Burst Mode Enable Feedback Voltage Burst Mode Peak Current Limit (1) VBFB IBPK Vcc=8.5V Vcc=8.8V, VFB=0V Vcc=8.8V, VFB=0V Switching Frequency in Burst Mode FSB Vcc High Threshold Voltage in Burst Mode VccH 8.6 9 9.4 V Vcc Low Threshold Voltage in Burst Mode VccL 8.1 8.5 8.9 V 10 15 20 ms SOFTSTART SECTION Soft start Time (1) TSS VFB=4V CURRENT LIMIT(SELF-PROTECTION)SECTION Peak Current Limit (2) ILIM Vcc=15V, VFB=5V 3.52 4 4.48 A ICH VSTR=650V, Vcc=0V 1.2 1.5 1.8 mA - In normal operation IOP Vcc=15V, VFB=5V - 3.5 6 mA - In burst mode IOB Vcc=8.7V, VFB=0V - 1.5 3 mA TOTAL DEVICE SECTION Startup Charging Current Operating Supply Current (3) Note: 1. These parameters, although guaranteed in design, are tested only in EDS (wafer test) process. 2. These parameters indicate the Inductor current. 3. These parameters apply to the current flowing into the control IC. 6 FSES0765RG Comparison of FS6S0765RC, FS8S0765RC and FSES0765RG Function FS6S0765RC FS8S0765RC FSES0765RG Required Istart=170uA (max) Required Istart=80uA (max) Not Required (Internal startup circuit) 15mA (max) 15mA (max) 6mA (max) : Normal mode 3mA (max) : Burst mode Control Method SSR PSR SSR Vcc OVP Threshold 30V 37V 20V 11/12V 11/12V 8.5/9V With external capacitor With external capacitor 50kHz 40kHz 50kHz 0.6A 0.6A 0.6A Startup Resistor Operating Supply Current Vcc Hysteresis Level in Burst Mode Soft Start Switching Frequency in Burst Mode Current Peak in Burst Mode Internal soft-start (15ms) 7 FSES0765RG Electrical Characteristics 1.4 1.4 1.2 1.2 V START [Normalized] I CH [Normalized] (These characteristic graphs are normalized at Ta= 25°C) 1.0 0.8 0.6 1.0 0.8 0.6 -40 0 40 80 120 160 -40 0 40 Temp[? ] 1.4 1.4 1.2 1.2 1.0 0.8 0.6 160 1.0 0.8 0.6 -40 0 40 80 120 160 -40 0 40 Temp[? ] 80 120 160 Temp[? ] Normal Mode Vcc Stop Voltage vs. Temp. Burst Mode Vcc Stop Voltage vs. Temp. 1.4 1.4 1.2 1.2 D MAX [Normalized] F OSC [Normalized] 120 Vcc Start Voltage vs. Temp. V BSTOP [Normalized] V NSTOP [Normalized] Start Up Charging Current vs. Temp. 1.0 0.8 0.6 1.0 0.8 0.6 -40 0 40 80 Temp[? ] Initial Frequency vs. Temp. 8 80 Temp[? ] 120 160 -40 0 40 80 120 Temp[? ] Maximum Duty Cycle vs. Temp. 160 FSES0765RG Electrical Characteristics 1.4 1.4 1.2 1.2 I NFB [Normalized] V OVP [Normalized] (These characteristic graphs are normalized at Ta= 25°C) 1.0 0.8 0.6 1.0 0.8 0.6 -40 0 40 80 120 160 -40 0 40 Temp[? ] OVP Threshold Voltage vs. Temp. 120 160 Normal Mode Feedback Current vs. Temp. 1.4 1.4 1.2 1.2 I DELAY [Normalized] I BFB [Normalized] 80 Temp[? ] 1.0 0.8 1.0 0.8 0.6 0.6 -40 0 40 80 120 160 -40 0 40 Temp[? ] 80 120 160 Temp[? ] Burst Mode Feedback Current vs. Temp. Feedback Delay Current vs. Temp. 1.4 1.4 I BUPK [Normalized] V SD [Normalized] 1.2 1.0 0.8 0.6 1.2 1.0 0.8 0.6 -40 0 40 80 120 Temp[? ] OLP Threshold Voltage vs. Temp. 160 -40 0 40 80 120 160 Temp[? ] Burst Mode Peak Drain Current vs. Temp. 9 FSES0765RG Electrical Characteristics 1.4 1.4 1.2 1.2 V SH [Normalized] V SL [Normalized] (These characteristic graphs are normalized at Ta= 25°C) 1.0 0.8 0.6 1.0 0.8 0.6 -40 0 40 80 120 160 -40 0 40 Temp[? ] 80 120 160 Temp[? ] Low Sync Threshold Voltage vs. Temp. High Sync Threshold Voltage vs. Temp. 2.0 1.4 I LIM [Normalized] T SY [Normalized] 1.6 1.2 0.8 0 40 80 120 Temp[? ] Sync Blanking Time vs. Temp. 10 1.0 0.8 0.4 0.0 -40 1.2 160 0.6 -40 0 40 80 120 Temp[? ] Pulse-by-Pulse Current Limit vs. Temp. 160 FSES0765RG Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vcc pin had an external start-up resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in figure 4. When Vcc reaches 12V, the FPS begins switching and the internal high voltage current source is disabled. Then, the FPS continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 9V. VDC CVcc Vcc 3 6 2.1 Pulse-by-pulse Current Limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of the PWM comparator (Vfb*) as shown in figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V. Since diode D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the SenseFET current is limited. 2.2 Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vstr Vcc Istart Vref 9V/12V Vref Idelay Vcc good Vfb Vo 4 H11A817A Figure 4. Internal Startup Circuit SenseFET OSC D1 CB Internal Bias IFB D2 2.5R + Vfb* KA431 Gate driver R - VSD OLP Rsense Figure 5. Pulse Width Modulation (PWM) Circuit 2. Feedback Control : FSES0765RG employs current mode control, as shown in figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 3. Protection Circuits : The FSES0765RG has several self protective functions such as over load protection (OLP), abnormal over current protection (AOCP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without requiring external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 9V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FPS resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see figure 6). 11 FSES0765RG Vds Power on Fault occurs VFB Fault removed Over load protection 7.5V 2.5V Vcc T12= Cfb*(7.5-2.5)/Idelay T1 12V T2 t Figure 7. Over Load Protection 9V Fault situation Normal operation Figure 6. Auto restart operation 3.1 Over Load Protection (OLP) : Overload occurs when the load current exceeds a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient or overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the optocoupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 2uA current source (Idelay) starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 7.5V, then the switching operation is terminated as shown in figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 7.5V with 2uA. In general, a 10 ~ 50 ms delay time is typical for most applications. 2.5R OSC PWM R S Q R Q Gate driver LEB Rsense 2 AOCP - Normal operation 3.2 Abnormal Over Current Protection (AOCP) : Even though the FPS has OLP (Over Load Protection) and current mode PWM feedback, these protections are not enough to protect the FPS when a secondary side diode short or a transformer pin short occurs. The FPS has an internal AOCP (Abnormal Over Current Protection) circuit, as shown in figure 8. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the reset signal is applied to the latch, resulting in the shutdown of SMPS. + t Vaocp GND Figure 8. AOCP Block 3.3 Over Voltage Protection (OVP) : If the secondary side feedback circuit malfunctions or a solder defect causes an open in the feedback path, the current through the optocoupler transistor becomes almost zero. Then, Vfb climbs up in a manner similar to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the output voltage may 12 FSES0765RG exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPS uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. 3.4 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 150°C, the thermal shutdown is activated. 4. Synchronization : Since the FSES0765RG is designed for CRT Monitor applications, this device has a synchronization function to minimize the screen noise. The MOSFET is turned on being synchronized to the external synchronization signal as shown in figure 9. In order to reduce voltage stress on the secondary side rectifier, a double pulse prevention function is included as well. The MOSFET’s turn-on is inhibited for 5us after the MOSFET is turned off in order to eliminate a double pulse situation. Sync signal 7.0V 6.0V MOSFET turn-off MOSFET turn-On 5. Soft Start : The FPS has an internal soft start circuit that slowly increases the PWM comparator’s inverting input voltage together with the Sense FET current during startup. The typical soft start time is 15ms. The pulse width to the power switching device progressively increases to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors also progressively increases with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 6. Burst operation : In order to minimize the power consumption in the standby mode, the FSES0765RG employs burst operation. Once FSES0765RG enters into burst mode, effective switching frequency and all output voltages are reduced. Figure 10 shows the typical feedback circuit to force the FSES0765RG to enter burst operation. In normal operation, the picture on signal is applied and the transistor Q1 is turned on, which de-couples R3 and D1 from the feedback network. Therefore, only Vo1 is regulated by the feedback circuit in normal operation and determined by R1 and R2 as V o1 norm R 1 + R 2⎞ = 2.5 ⋅ ⎛⎝ ------------------R2 ⎠ In standby mode, the picture on signal is disabled and the transistor Q1 is turned off, which couples R3 and D1 to the reference pin of KA431. Then, the voltage on the reference pin of KA431 is higher than 2.5V and the current through the opto coupler increases, which increases the current through the opto LED. This pulls down the feedback voltage (VFB) of FPS and forces FPS to stop switching until Vcc drops to 8.5V. When Vcc reaches 8.5V, the FPS starts switching with a switching frequency of 50kHz and a peak drain current of 0.6A until Vcc reaches 9V. When Vcc reaches 9V, the switching operation is terminated again until Vcc reduces to 8.5V. Sync signal VO2 7.0V 6.0V Linear Regulator VO1 (B+) Micom RD Rbias Current limit level determined by feedback voltage R1 CF Drain Current C KA431 A 5us sync detect blanking 5us sync detect blanking Figure 9. Synchronization Operation RF D1 R3 Q1 Picture ON R R2 Figure 10. Typical feedback Circuit for FPS Burst Operation 13 FSES0765RG Typical application Circuit Application Output power Input voltage Output voltage (Max current) 80V (0.15A) CRT-Monitor 64W Universal input 50V (0.70A) (85-265Vac) 14V (0.8A) -14V (0.3A) 6.5V (0.3A) Features • • • • • • High efficiency (>80% at 85Vac input) Synchronized switching Low standby mode power consumption (<1W) Low component count Enhanced system reliability through various protection functions Internal soft-start (15ms) 1. Schematic L201 13uH T1 EER4044 1 R101 68kΩ 2W BD101 KBU6G 16 C107 47nF 630V RT101 10D-9 R209 33kΩ 0.25W L202 13uH D202 SUF15J 180V R201 300kΩ 0.25W R202 4.2kΩ 0.25W 80V 14 4 C204 47uF 160V C203 47uF 160V 13 C105 47nF LF101 1.2mH IC101 FSES0765 5 C103 4.7nF C104 4.7nF External Sync C108 1uF 50V R104 470Ω 0.25W C102 47nF VAR101 10D471K 6 Vsync 4 Vfb C109 47nF 10 C110 47uF 50V R102 6 D102 15Ω UF4004 0.25W 7 C209 1000uF 16V L204 13uH L205 13uH C206 1000uF 35V 15V -15V C208 1000uF 35V 6.5V C210 1000uF 16V 9 C301 4.7nF F101 FUSE 250V 3.0A C207 1000uF 35V D205 UG4D 1 Vcc 3 GND 2 C205 1000uF 35V D204 UG4D 11 Drain L203 13uH D203 UG4D 12 C302 4.7nF IC301 HC11A817A R203 1kΩ 0.25W R204 1kΩ 0.25W IC201 KA431 14 C202 22uF 400V C201 22uF 400V 15 2 3 D101 UF 4007 C106 220uF 400V D201 RG4C IC202 KA7805 1 R205 C211 33kΩ 47nF 0.25W D206 UF4004 Q201 KSC945 R206 2.7kΩ 0.25W R207 4.7kΩ 0.25W SW 201 Switch R208 4.7kΩ 0.25W Input Output 3 GND 2 C212 100uF 16V 5V, 0.13A R210 39Ω 0.25W FSES0765RG 2. Transformer Schematic Diagram EER3540 N p1 1 16 2 15 N p2 3 14 4 13 5 12 Na 6 11 7 10 8 9 Np1 N 80V Na N50V N 50V N14V N-14V N 14V N6.5V N -14V N80V Np2 N 6.5V 3.Winding Specification No Np2 N80V Pin (s→f) 2-1 16 - 15 Wire Turns Winding Method 0.3 × 2 20 Center Winding 0.3φ ×1 10 Center Winding φ φ N6.5V 10 - 9 0.3 × 2 3 Center Winding N-14V 9 - 11 0.3φ × 1 5 Center Winding 12 - 9 0.3φ ×2 6 Center Winding 0.3 × 3 22 Center Winding N14V N50V Na Np1 14 - 13 φ φ 6-8 0.2 × 1 8 Center Winding 4-3 0.3φ 20 Center Winding ×2 4.Electrical Characteristics Inductance Leakage Inductance Pin Specification 1-4 420uH ± 5% 1-4 5uH Max Remarks 1kHz, 1V 2 nd all short 5. Core & Bobbin Core : EER 3540 Bobbin : EER3540 Ae : 107 mm2 15 FSES0765RG Package Dimensions Dimensions in Millimeters TO-220-6L(Forming) 4.70 4.30 10.10 9.70 1.40 1.25 2.90 2.70 15.90 15.50 9.40 9.00 20.00 19.00 (13.55) 23.80 23.20 (0.65) R0.55 (0.75) R0.55 8.30 MAX1.10 7.30 2.60 2.20 (7.15) MAX0.80 0.70 0.50 2.19 1.75 1.27 3.81 10.20 9.80 16 0.60 0.45 3.48 2.88 FSES0765RG Ordering Information Product Number Package Marking Code BVdss Rds(ON) Max. FSES0765RGWDTU TO-220-6L(Forming) ES0765R 650V 1.6 Ω 17 FSES0765RG DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 10/4/05 0.0m 001 © 2005 Fairchild Semiconductor Corporation