a GSM Power Management System ADP3408 FEATURES Handles all GSM Baseband Power Management Six LDOs Optimized for Specific GSM Subsystems Li-Ion and NiMH Battery Charge Function Optimized for the AD20msp430 Baseband Chipset FUNCTIONAL BLOCK DIAGRAM VBAT VBAT2 VRTCIN SIM LDO APPLICATIONS GSM/DCS/PCS/CDMA Handsets DIGITAL CORE LDO PWRONKEY ANALOG LDO ROWX VSIM VCORE VAN PWRONIN TCXOEN POWER-UP SEQUENCING AND PROTECTION LOGIC TCXO LDO VTCXO MEMORY LDO VMEM RTC LDO VRTC REF BUFFER 26 REFOUT SIMEN GENERAL DESCRIPTION The ADP3408 is a multifunction power system chip optimized for GSM handsets, especially those based on the Analog Devices AD20msp430 system solution. It contains six LDOs, one to power each of the critical GSM sub-blocks. Sophisticated controls are available for power-up during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end-of-charge signal when a Li-Ion battery is being charged. The ADP3408 is specified over the temperature range of –20°C to +85°C and is available in narrow body TSSOP-28 pin package. RESCAP RESET CHRDET BATTERY CHARGE DIVIDER EOC MVBAT CHGEN GATEIN BATSNS ISENSE BATTERY CHARGE CONTROLLER DGND ADP3408 27 AGND GATEDR CHRIN REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 (–20ⴗC ≤ T ≤ +85ⴗC, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN = ADP3408–SPECIFICATIONS CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on all outputs, unless otherwise noted.) A Parameter Symbol SHUTDOWN SUPPLY CURRENT VBAT ≤ 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT ≤ 3.2 V (UVLO Active) VBAT > 3.2 V ICC OPERATING GROUND CURRENT VSIM, VCORE, VMEM, VRTC On All LDOs On IGND UVLO ON THRESHOLD UVLO HYSTERESIS Condition Min Typ Max Unit VBAT = VBAT2 = 2.3 V 7 20 µA VBAT = VBAT2 = 3.0 V 30 55 µA VBAT = VBAT2 = 4.0 V 45 80 µA VBAT = 3.6 V Minimum Loads Minimum Loads Maximum Loads 225 345 1.0 300 450 3.0 µA µA % of max load current VBAT 3.2 3.3 V VBAT 200 DEEP DISCHARGED LOCKOUT ON THRESHOLD VBAT 2.4 DEEP DISCHARGED LOCKOUT HYSTERESIS VBAT 100 INPUT HIGH VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) VIH INPUT LOW VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) VIL 0.4 V INPUT HIGH BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) IIH 1.0 µA INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, GATEIN) IIL –1.0 µA PWRONKEY INPUT HIGH VOLTAGE VIH 0.7 × VBAT V PWRONKEY INPUT LOW VOLTAGE VIL mV 2.75 mV 2.0 PWRONKEY INPUT PULL-UP RESISTANCE TO VBAT 70 V V 100 0.3 × VBAT V 130 kΩ THERMAL SHUTDOWN THRESHOLD2 160 ºC THERMAL SHUTDOWN HYSTERESIS 45 ºC ROWX CHARACTERISTICS ROWX Output Low Voltage ROWX Output High Leakage Current SIM CARD LDO (VSIM) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Dropout Voltage DIGITAL CORE LDO (VCORE) Output Voltage ADP3408ARU-2.5 ADP3408ARU-1.8 Line Regulation Load Regulation Output Capacitor Required for Stability VOL IIH VSIM ∆VSIM ∆VSIM CO VDO VCORE VCORE ∆VCORE ∆VCORE PWRONKEY = Low IOL = 200 µA PWRONKEY = High V(ROWX) = 5 V Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 20 mA, VBAT = 3.6 V 2.80 2.85 2 1 0.4 V 1 µA 2.92 V mV mV µF 2.2 VO = VINITIAL – 100 mV, ILOAD = 20 mA Line, Load, Temp Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 100 mA, VBAT = 3.6 V CO 2.40 1.75 2.2 –2– 35 100 mV 2.45 1.80 2 7 2.50 1.85 V V mV mV µF REV. 0 ADP3408 Parameter Symbol Condition Min Typ Max Unit RTC LDO REAL-TIME CLOCK LDO/ COIN CELL CHARGER (VRTC) Maximum Output Voltage ADP3408ARU-2.5 ADP3408ARU-1.8 Off Reverse Input Current Output Capacitor Required for Stability VRTC VRTC IL CO 1 µA ≤ ILOAD ≤ 10 µA 1 µA ≤ ILOAD ≤ 10 µA VBAT = 2.15 V, TA = 25°C 2.39 1.80 2.45 1.95 2.51 2.1 0.5 V V µA µF ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation VAN ∆VAN ∆VAN Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 130 mA, VBAT = 3.6 V 2.45 2 8 2.50 V mV mV Output Capacitor Required for Stability Ripple Rejection Output Noise Voltage TCXO LDO (VTCXO) Output Voltage Line Regulation Load Regulation CO ∆VBAT/ ∆VAN3 VNOISE VTCXO ∆VTCXO ∆VTCXO Output Capacitor Required for Stability Dropout Voltage CO VDO Ripple Rejection Output Noise Voltage ∆VBAT/ ∆VTCXO VNOISE MEMORY LDO (VMEM) Output Voltage Line Regulation Load Regulation VMEM ∆VMEM ∆VMEM Output Capacitor Required for Stability Dropout Voltage REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance REV. 0 0.1 f = 217 Hz VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 130 mA VBAT = 3.6 V Line, Load, Temp Min Load 50 µA ≤ ILOAD ≤ 20 mA, VBAT = 3.6 V ∆VBAT/ ∆VREFOUT CO VNOISE VOH VOL IOL/IOH Line, Load, Temp Min Load 50 µA < ILOAD < 60 mA, VBAT = 3.6 V µV rms 80 2.66 2.715 2 1 2.77 160 310 65 Line, Load, Temp Min Load 0 µA < ILOAD < 50 µA VBAT = 3.6 V f = 217 Hz VBAT = 3.6 V, ILOAD = 50 µA 2.80 2 3 2.856 80 180 1.19 1.210 0.2 0.5 1.23 65 75 dB 40 pF µV rms 100 f = 10 Hz to 100 kHz, VBAT = 3.6 V IOH = 500 µA IOL = –500 µA VOL = 0.25 V, VOH = VMEM – 0.25 V TCXOEN = High TCXOEN = Low TCXOEN = High –3– µF mV µV rms 80 2.744 V mV mV dB 2.2 TD BATSNS/MVBAT ZO µF dB 2.2 65 0.22 VO = VINITIAL – 100 mV ILOAD = 20 mA f = 217 Hz VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 20 mA, VBAT = 3.6 V CO VREFOUT ∆VREFOUT ∆VREFOUT 2.40 VMEM – 0.25 V mV mV mV µF mV V mV mV 0.25 V V mA 1 0.6 1.2 2.4 ms/nF 2.32 59.5 2.35 85 215 300 2.37 110 1 385 kΩ kΩ µA kΩ ADP3408 Parameter Symbol Condition Min Typ Max Unit BATTERY CHARGER Charger Output Voltage BATSNS 4.35 V ≤ CHRIN ≤ 10 V3 CHGEN = Low, No Load CHRIN = 5 V 0 ≤ CHRIN – ISENSE < Current Limit Threshold CHGEN = Low 4.150 4.200 4.250 V 15 mV Load Regulation ∆BATSNS CHRDET On Threshold CHRDET Off Threshold CHRDET Off Delay4 CHRIN Supply Current CHRIN – BATSNS CHRIN – BATSNS BATTERY CHARGER Current Limit Threshold High Current Limit (UVLO Not Active) 30 15 90 45 6 0.6 150 100 mV mV ms/nF mA 142 160 190 mV 20 35 mV CHRIN < VBAT CHRIN = 5 V CHRIN – ISENSE CHRIN = 5 V dc VBAT = 3.6 V CHGEN = Low VBAT = 2 V CHGEN = Low CHRIN = 5 V Low Current Limit (UVLO Active) ISENSE Bias Current µA 200 End-of-Charge Signal Threshold CHRIN – ISENSE CHRIN = 5 V VBAT > 4.0 V CHGEN = Low EOC Reset Threshold VBAT CHGEN = Low 3.82 GATEDR Transition Time tR, tF CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF 0.1 GATEDR High Voltage VOH 4.5 GATEDR Low Voltage VOL Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) Battery Overvoltage Protection Threshold (GATEDR → High) Battery Overvoltage Protection Hysteresis VOH CHRIN = 5 V VBAT = 3.6 V CHGEN = High, GATEIN = High IOH = –1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = 1 mA IOH = –250 µA VOL IOL = +250 µA BATSNS CHRIN = 7.5 V CHGEN = High GATEIN = Low CHRIN = 7.5 V CHGEN = High GATEIN = Low BATSNS 14 35 mV 3.96 4.10 V 1 µs V 0.5 2.4 5.30 V V 5.50 200 0.25 V 5.70 V mV NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC could cause permanent damage to the device. 3 No isolation diode present between charger input and battery. 4 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice. –4– REV. 0 ADP3408 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS* Voltage on any pin with respect to any GND Pin . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V Voltage on any pin may not exceed VBAT, with the following exceptions: CHRIN, GATEDR, ISENSE Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Operating Ambient Temperature Range . . . . . –20°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C θJA, Thermal Impedance (TSSOP-28) 4-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W 1-Layer PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300°C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ORDERING GUIDE Model Core LDO Output Temperature Voltage Range ADP3408ARU-2.5 2.5 V ADP3408ARU-1.8 1.8 V –20°C to +85°C –20°C to +85°C Package Option* RU-28 RU-28 Pin Mnemonic Function 1 PWRONIN 2 3 4 5 6 PWRONKEY ROWX SIMEN VRTCIN VRTC 7 8 9 10 11 BATSNS MVBAT CHRDET CHRIN GATEIN 12 13 14 15 16 GATEDR DGND ISENSE EOC CHGEN 17 18 19 20 21 22 23 24 25 26 27 28 RESCAP RESET VSIM VBAT2 VMEM VCORE VBAT VAN VTCXO REFOUT AGND TCXOEN Power On/Off Signal from Microprocessor Power-On/-Off Key Power Key Interface Output SIM LDO Enable RTC LDO Input Voltage Real-Time Clock Supply/ Coin Cell Battery Charger Battery Voltage Sense Input Divided Battery Voltage Output Charge Detect Output Charger Input Voltage Microprocessor Gate Input Signal Gate Drive Output Digital Ground Charge Current Sense Input End of Charge Signal Charger Enable for GATEIN, NiMH Pulse Charging Reset Delay Time Main Reset SIM LDO Output Battery Input Voltage 2 Memory LDO Output Digital Core LDO Output Battery Input Voltage Analog LDO Output TCXO LDO Output Output Reference Analog Ground TCXO LDO Enable and MVBAT Enable *RU = Thin Shrink Small Outline PIN CONFIGURATION PWRONIN 1 28 TCXOEN PWRONKEY 2 27 AGND ROWX 3 26 REFOUT SIMEN 4 25 VTCXO VRTCIN 5 VRTC 6 24 VAN ADP3408 23 VBAT BATSNS 7 TOP VIEW 22 VCORE (Not to Scale) 21 VMEM MVBAT 8 CHRDET 9 CHRIN 10 GATEIN 11 GATEDR 12 DGND 13 ISENSE 14 20 VBAT2 19 VSIM 18 RESET 17 RESCAP 16 CHGEN 15 EOC CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3408 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE ADP3408 SIMEN X L X OFF OFF OFF OFF OFF OFF OFF State #2 Phone Off H L X X X L X OFF OFF OFF OFF OFF ON OFF State #3 Phone Off, Turn-On Allowed H H L H L L X OFF OFF OFF OFF OFF ON OFF State #4 Charger Applied H H H X X L L OFF ON ON ON ON ON OFF State #5 Phone Turned On by User Key H H X L X L L OFF ON ON ON ON ON OFF State #6 Phone Turned On by BB H H L H H L L OFF ON OFF OFF ON ON OFF State #7 Enable SIM Card H H L H H L H ON ON OFF OFF ON ON OFF State #8 Phone and TCXO LDO Kept On by BB H H L H H H H ON ON ON ON ON ON ON MVBAT TCXOEN X VRTC PWRONIN X VMEM PWRONKEY X VTCXO CHRDET L VCORE UVLO* State #1 Battery Deep Discharged VSIM PHONE STATUS DDLO VAN and REFOUT Table I. LDO Control Logic *UVLO is active only when phone is turned off. UVLO is ignored once the phone is turned on. –6– REV. 0 Typical Performance Characteristics– ADP3408 450 1.8 400 REVERSE LEAKAGE CURRENT – A 10000 ALL LDO, MVBAT, REFOUT, ON_MIN_LOAD (SIMEN = H, TCXOEN = H) –20ⴗC +85ⴗC 350 I VRTC – A IGND – A 1000 VSIM, VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = H, TCXOEN = L) 300 250 +25ⴗC 100 200 VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = L, TCXOEN = L) 150 10 100 3.0 3.5 4.0 4.5 VBAT – V 5.0 0 5.5 TPC 1. Ground Current vs. Battery Voltage 0.5 1.0 1.5 VRTC – V 2.0 2.5 TPC 2. RTC I/V Characteristic 1.6 1.4 RTC REVERSE LEAKAGE (VBAT = FLOAT) 1.2 1.0 0.8 RTC REVERSE LEAKAGE (VBAT = 2.3V) 0.6 0.4 0.2 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE – ⴗC TPC 3. VRTC Reverse Leakage Current vs. Temperature 180 DROPOUT VOLTAGE – mA 160 3.2 3.2 VTCXO 140 VBAT 120 VBAT 3.0 3.0 100 80 VTCXO 10mV/DIV VTCXO 10mV/DIV 60 VMEM 10mV/DIV VMEM 10mV/DIV VSIM VMEM 40 20 0 0 20 40 60 LOAD CURRENT – mA TIME – 100s/DIV 80 TPC 4. Dropout Voltage vs. Load Current TPC 5. Line Transient Response, Minimum Loads TIME – 100s/DIV TPC 6. Line Transient Response, Maximum Loads 3.2 3.2 20mA LOAD VBAT VBAT 3.0 3.0 3mA VAN 10mV/DIV VCORE 10mV/DIV VTCXO 10mV/DIV 10mV/DIV VMEM 10mV/DIV VSIM TIME – 100s/DIV TPC 7. Line Transient Response, Minimum Loads REV. 0 TIME – 100s/DIV TPC 8. Line Transient Response, Maximum Loads –7– VTCXO 10mV/DIV TIME – 200s/DIV TPC 9. VTCXO Load Step ADP3408 100mA 60mA 20mA LOAD VSIM 3mA LOAD LOAD 5mA VMEM 5mV/DIV 10mA VCORE 10mV/DIV 10mV/DIV TIME – 200s/DIV TIME – 200s/DIV TIME – 200s/DIV TPC 10. VSIM Load Step TPC 11. VMEM Load Step TPC 12. VCORE Load Step PWRONIN (2V/DIV) PWRONIN (2V/DIV) 130mA VAN (100mV/DIV) LOAD REFOUT (100mV/DIV) 10mA VSIM (100mV/DIV) VAN VMEM (100mV/DIV) 10mV/DIV VCORE (100mV/DIV) VTCXO (100mV/DIV) TIME – 200s/DIV TPC 13. VAN Load Step TIME – 100s/DIV TIME – 400s/DIV TPC 14. Turn On Transient by PWRONIN, Minimum Load (Part 1) TPC 15. Turn On Transient by PWRONIN, Minimum Load (Part 2) 80 PWRONIN (2V/DIV) PWRONIN (2V/DIV) VTCXO 70 REFOUT (100mV/DIV) VAN (100mV/DIV) VSIM (100mV/DIV) VCORE (100mV/DIV) VMEM (100mV/DIV) VTCXO (100mV/DIV) RIPPLE REJECTION – dB VAN 60 VCORE 50 REFOUT 40 MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS 30 20 10 0 TIME – 20s/DIV TIME – 20s/DIV TPC 16. Turn On Transient by PWRONIN, Maximum Load (Part 1) TPC 17. Turn On Transient by PWRONIN, Maximum Load (Part 2) –8– 4 10 100 1k 10k FREQUENCY – Hz 100k TPC 18. Ripple Rejection vs. Frequency REV. 0 REFOUT RIPPLE REJECTION – dB 70 60 VSIM VCORE VAN 50 40 VTCXO VMEM 30 20 10 FREQUENCY = 217Hz MAX LOADS 0 2.5 2.6 2.7 2.8 2.9 3.0 VBAT – V 3.1 3.2 3.3 TPC 19. Ripple Rejection vs. Battery Voltage 4.25 600 FULL LOAD MLCC CAPS 500 4.23 VAN 400 TCXO 300 200 10 100 1k 10k FREQUENCY – Hz 100k OUTPUT VOLTAGE – V 4.20 0 200 400 ILOAD – mA 600 800 TPC 22. Charger V OUT vs. I LOAD (VIN = 5.0 V) REV. 0 4.19 4.18 ILOAD = 500mA ILOAD = 10mA 4.21 4.20 5 6 7 8 INPUT VOLTAGE – V 9 TPC 23. Charger VOUT vs. VIN –9– –20 0 20 40 60 80 100 120 TPC 21. Charger V OUT vs. Temperature, VIN = 5.0 V, ILOAD = 10 mA 4.23 4.22 4.15 –40 TEMPERATURE – ⴗC RSENSE = 250m⍀ 4.21 4.20 4.16 0 4.24 4.22 4.21 4.17 VIN = 5.0V RSENSE = 250m⍀ 4.23 4.22 REF 100 TPC 20. Output Noise Density 4.24 OUTPUT VOLTAGE – V 4.24 CHARGER VOUT – V 80 VOLTAGE SPECTRAL NOISE DENSITY – nV/ Hz ADP3408 10 ADP3408 VBAT VRTCIN VBAT2 SIM LDO VBAT 100k⍀ Q PWRONKEY UVLO S OUT VREF DEEP DISCHARGED UVLO EN R VSIM DGND DIGITAL CORE LDO ROWX VBAT OVER- TEMP SHUTDOWN OUT VREF EN VCORE PG DGND PWRONIN ANALOG LDO VBAT SIMEN OUT VREF EN CHARGER DETECT VAN AGND TCXOEN RESET GENERATOR RESCAP RESET TCXO LDO CHRDET VBAT OUT VTCXO VREF EN AGND EOC CHGEN GATEIN BATSNS ISENSE LI-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE MEMORY LDO VBAT VREF EN GATEDR OUT VMEM DGND RTC LDO CHRIN VBAT OUT VRTC VREF EN DGND EN REF BUFFER MVBAT ADP3408 1.21V REFOUT + – AGND AGND DGND Figure 1. Functional Block Diagram EOC CHGEN GATEIN ADP3408 D1 BATSNS Q1 SI3441DY GATEDR BATTERY CHARGE CONTROLLER ISENSE R1 0.2⍀ C1 10nF CHRIN (10V MAX) CHRDET Figure 2. Battery Charger Typical Application –10– REV. 0 ADP3408 PWRON TCXOEN PWRONIN PWRONKEY PWRONKEY AGND KEYPADROW ROWX REFOUT GPIO SIMEN VTCXO VRTCIN VRTC CAPACITOR TYPE BACKUP COIN CELL C1 0.1F AUXADC GPIO CHARGER IN VRTC U1 ADP3408 VTCXO BATSNS VCORE MVBAT VMEM CHRDET VBAT2 C9 0.22F C10 0.1F VMEM C6 2.2F VSIM VSIM RESET RESET C5 2.2F RESCAP DGND Q1 SI3441DY C8 2.2F VCORE C2, 10nF GATEDR VAN C3, 10F VBAT GATEIN R1 0.33⍀ REF VAN CHRIN GPIO CLKON R2 10⍀ C7 2.2F GPIO CHGEN ISENSE EOC GPIO C4 0.1F D1 LI OR NIMH BATTERY Figure 3. Typical Application Circuit THEORY OF OPERATION The ADP3408 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3408. The ADP3408 contains several blocks: • Six Low Dropout Regulators (SIM, Core, Analog, Crystal Oscillator, Memory, Real-Time Clock) 1.2 Reset Generator Buffered Precision Reference Lithium Ion Charge Controller and Processor Interface Power-On/-Off Logic Undervoltage Lockout Deep Discharge Lockout 1.0 POWER DISSIPATION – W • • • • • • However, high battery voltages normally occur only when the battery is being charged and the handset is not in conversation mode. In this mode there is a relatively light load on the LDOs. A fully charged Li-Ion battery is 4.25 V, where the ADP3408 can deliver the maximum power (0.56W) up to 85°C ambient temperature. These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3408 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a GSM environment while maintaining a cost competitive solution. 0.4 0.0 –20 Input Voltage REV. 0 0.6 0.2 Figure 3 shows the external circuitry associated with the ADP3408. Only a minimal number of support components are required. The input voltage range of the ADP3408 is 3 V to 5.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The thermal impedance of the ADP3408 is 68°C/W for four-layer boards. The end-of-charge voltage for high capacity NiMH cells can be as high as 5.5 V. Power dissipation should be calculated at maximum ambient temperatures and battery voltage in order not to exceed the 125°C maximum allowable junction temperature. Figure 4 shows the maximum power dissipation as a function of ambient temperature. 0.8 0 20 40 60 AMBIENT TEMPERATURE – ⴗC 80 100 Figure 4. Power Dissipation vs. Temperature Low Dropout Regulators (LDOs) The ADP3408 high-performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 µF tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, SIM, and analog LDOs. A 0.22 µF capacitor is recommended for the TCXO LDO. –11– ADP3408 ripple coming from the RF power amplifier. VAN is rated to 130 mA load, which is sufficient to supply the complete analog section of the baseband converter such as the AD652l. NON-CHARGING MODE TCXO LDO (VTCXO) CHARGER DETECTER CHRIN > BATSNS The TCXO LDO is intended as a supply for a temperaturecompensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 5 mA of output current and is turned on along with the analog LDO when TCXOEN is asserted. NO YES RTC LDO (VRTC) The RTC LDO charges up a capacitor-type backup coin cell to run the real-time clock module. It has been designed to charge electric double layer capacitors such as the PAS621 from Kanebo. The PAS621 has a small physical size (6.8 mm diameter) and a nominal capacity of 0.3 F, giving many hours of backup time. YES VBAT > UVLO NO NIMH LOW CURRENT CHARGE MODE VSENSE = 20mV BATTERY TYPE The ADP3408 supplies current both for charging the coin cell and for the RTC module when the digital supply is off. The nominal charging voltage is 2.45 V, which ensures long cell life while obtaining in excess of 90% of the nominal capacity. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module. LI+ CHGEN = LOW HIGH CURRENT CHARGE MODE VSENSE = 160mV CHGEN = HIGH NIMH CHARGING MODE GATEIN = PULSED SIM LDO (VSIM) NO The SIM LDO generates the voltage needed for 3 V SIMs. It is rated for 20 mA of supply current and can be controlled completely independently of the other LDOs. VBAT > 4.2V YES NO Reference Output (REFOUT) VBAT > 5.5V YES NIMH CHARGER OFF GATEIN = HIGH VBAT < 5.5V The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% over temperature. The reference can be used with the baseband converter, if the converter’s own reference is not accurate. This will significantly reduce calibration time needed for the baseband converter during production. Note that the reference in the AD6521 has an initial accuracy of 10%, but can be calibrated to within 1%. CONSTANT VOLTAGE MODE NO NO ICHARGE < I END OF CHARGE Power ON/OFF YES The ADP3408 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3408 in three different ways: • Pulling the PWRONKEY Low • Pulling PWRONIN High • CHRIN exceeds CHRDET Threshold EOC = HIGH YES TERMINATE CHARGE CHREN = HIGH GATEIN = HIGH Figure 5. Battery Charger Flow Chart Digital Core LDO (VCORE) The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on at all times. Memory LDO (VMEM) The memory LDO supplies the peripheral subsystems of the baseband processor including GPIO, display, and SIM interfaces as well as memory. The LDO has also been optimized for low quiescent current and will power up at the same time as the core LDO. Analog LDO (VAN) This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn all the LDOs on, except the SIM LDO, as long as the PWRONKEY is held low. When the VCORE LDO comes into regulation the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3408 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/ OFF control. Pulling the PWRONIN pin high is how the alarm in the Real-Time Clock module will turn the handset on. Asserting PWRONIN will turn the core and memory LDOs on, starting up the baseband processor. –12– REV. 0 ADP3408 This ensures that the handset will always power-off before the ADP3408 exceeds its absolute maximum thermal ratings. Applying an external charger can also turn the handset on. This will turn on all the LDOs, except the SIM LDO, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs. Battery Charging Deep Discharge Lockout (DDLO) The DDLO block in the ADP3408 has two functions: • To shut off the VRTC LDO in the event that the main battery discharges to below the RTC LDO’s output voltage. This will force the real-time clock to run off the backup coin cell or double layer capacitor. • To shut down the handset in the event that the software fails to turn off the phone when the battery drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the cells. Undervoltage Lockout (UVLO) The UVLO function in the ADP3408 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than 3.2 V, such as inserting a fresh battery, the UVLO comparator trips, and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. Note that the DDLO has enabled the RTC LDO under this condition. Once the system is started, and the core and memory LDOs are up and running, the UVLO function is disabled. The ADP3408 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor and usually shuts off the phone at around 3.0 V. If the handset is off, and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3408 into UVLO shutdown mode. In this mode the ADP3408 draws very low quiescent current, typically 30 µA. The RTC LDO is still running until the DDLO disables it. In this mode the ADP3408 draws 5 µA of quiescent current. NiMH batteries can reverse polarity if the three-cell battery voltage drops below 3.0 V which will degrade the batteries’ performance. Lithium ion batteries will lose their capacity if repeatedly overdischarged, so minimizing the quiescent currents helps prevent battery damage. RESET The ADP3408 contains a reset circuit that is active at both power-up and power-down. The RESET pin is held low at initial power-up. An internal power good signal is generated by the core LDO when its output is up, which starts the reset delay timer. The delay is set by an external capacitor on RESCAP: t RESET = 1.2 ms × CRESCAP nF (1) At power-off, RESET will be kept low to prevent any baseband processor starts. Over-Temperature Protection The ADP3408 battery charger can be used with Lithium Ion (Li+) and Nickel Metal Hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. The charger block works in three different modes: • Low Current (Trickle) Charging • Lithium Ion Charging • Nickel Metal Hydride Charging Charge Detection The ADP3408 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 90 mV, the CHRDET output will go high. If the adapter is then removed and the voltage at the CHRIN pin drops to only 45 mV above the BATSNS pin, CHRDET goes low. Trickle Charging When the battery voltage is below the UVLO threshold, the charge current is set to the Low Current Limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by: I CHR (TRICKLE ) = (2) Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. Once the UVLO threshold has been exceeded the charger will switch to the high current limit, the LDOs will start up, and the baseband processor will start to run. The processor must then poll the battery to determine which chemistry is present and set the charger to the proper mode. Lithium Ion Charging For lithium ion charging, the CHGEN input must be low. This allows the ADP3408 to continue charging the battery at the full current. The full charge current can be calculated by using: I CHR ( FULL ) = 160 mV RSENSE (3) If the voltage at BATSNS is below the charger’s output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 14 mV, an Endof-Charge signal is generated and the EOC output goes high. See Figure 6. The maximum die temperature for the ADP3408 is 125°C. If the die temperature exceeds 160°C, the ADP3408 will disable all the LDOs except the RTC LDO. The LDOs will not be REV. 0 20 mV RSENSE –13– ADP3408 Separate inputs for the SIM LDO and the RTC LDO are supplied for additional bypassing or filtering. The SIM LDO has VBAT2 as its input and the RTC LDO has VRTCIN. VBAT ICHG LDO Capacitor Selection The performance of any LDO is a function of the output capacitor. The core, memory, SIM, and analog LDOs require a 2.2 µF capacitor and the TCXO LDO requires a 0.22 µF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. EOC TIME Figure 6. End of Charge The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN and CHGEN pins high. NiMH Charging For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the processor can charge a NiMH battery. Note that when charging NiMH cells, a current-limited adapter is required. During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached, at which time the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected. Battery Voltage Monitoring The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider can be connected to BATSNS when both the digital and analog baseband sections are powered up. To enable MVBAT both PWRONIN and TCXOEN must be high. All the LDOs are stable with a wide range of capacitor types and ESR (anyCAP® technology). The ADP3408 is stable with extremely low ESR capacitors (ESR ~ 0), such as Multilayer Ceramic Capacitors (MLCC), but care should be taken in their selection. Note that the capacitance of some capacitor types show wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, capacitor is recommended. The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 µF ceramic capacitor is recommended for stability and best performance. RESET Capacitor Selection RESET is held low at power-up. An internal power-good signal starts the reset delay when the core LDO is up. The delay is set by an external capacitor on RESCAP: ms × CRESCAP (4) nF A 100 nF capacitor will produce a 120 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VCORE is off to minimize power consumption. When VCORE is on, RESET is capable of driving 500 µA. t RESET = 1.2 Setting the Charge Current The ADP3408 is capable of charging both Lithium Ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For Lithium Ion batteries, the charge current is programmed by selecting the sense resistor, R1. The Lithium Ion charge current is calculated using: I CHR = The ratio of the voltage divider is selected so that the 2.4 V maximum input of the AD6521’s auxiliary ADC will correspond with the maximum battery voltage of 5.5 V. The divider will be disconnected from the battery when the baseband sections are powered down. (5) Where VSENSE is the high current limit threshold voltage. Or if the charge current is known, R1 can be found. R1 = VSENSE 160 mV = I CHR I CHR (6) Similarly the trickle charge current and the end of charge current can be calculated: APPLICATION INFORMATION Input Capacitor Selection For the input (VBAT, VBAT2, and VRTCIN) of the ADP3408, a local bypass capacitor is recommended. Use a 10 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel. VSENSE 160 mV = R1 R1 ITRICKLE = I EOC = VSENSE 20 mV = R1 R1 (7) Example: Assume an 800mA-H capacity Lithium Ion battery and an 1C charge rate. R1 = 200 mΩ, ITRICKLE = 100 mA, and IEOC = 100 mA. anyCAP is a registered trademark of Analog Devices Inc. –14– REV. 0 ADP3408 VDS = VADAPT ( MIN ) – VDIODE – VSENSE – VBAT = Appropriate sense resistors are available from the following vendors: 5 V – 0.5 V – 0.160 V – 4.2 V = 140 mV Vishay Dale IRC Panasonic RDS (ON ) = The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and the charge current. The selected PMOS must satisfy the physical, electrical and thermal design requirements. PDISS Appropriate PMOS FETs are available from the following vendors: To ensure proper operation, the minimum VGS the ADP3408 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following: VGS = VADAPTER ( MIN ) − VGATEDR − VSENSE Siliconix IR Fairchild (8) VADAPTER(MIN) is the minimum adapter voltage, VGATEDR is the gate drive “low” voltage, 0.5 V, and VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the ON resistance of the FET at maximum charge current, where: VDS = VADAPTER( MIN ) − VDIODE − VSENSE − VBAT Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: (9) 1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3408. Locate the input capacitor as close to the pins as possible. (10) 2. VAN and VTCXO capacitors should be returned to AGND. The RDS(ON) of the FET can then be calculated. VDS I CHR ( MAX ) 3. VCORE, VMEM and VSIM capacitors should be returned to DGND. The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using: ) PDISS = VADAPTER (MAX ) − VDIODE − VSENSE − UVLO × I CHR 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. (11) It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 800 mA VSENSE = 160 mV VGATEDR = 0.5 V VGS = 5 V – 0.5 V – 160 V = 4.34 V Charger Diode Selection The diode, D1, shown in Figure 2, is used to prevent the battery from discharging through the PMOS’ body diode into the charger’s internal bias circuits. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types. where: ( 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin-connect the charger’s sense resistor by running separate traces to the CHRIN and ISENSE pins. Make sure that the traces are terminated as close to the resistor’s body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3408 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance. Therefore, choose a low threshold voltage FET. REV. 0 ( ) = (6.5 V – 0.5 V – 0.160 V – 3.2) × 0.8 A = 2.11W PDISS = VADAPT ( MAX ) – VDIODE – VSENSE – UVLO × I CHR Charger FET Selection RDS (ON ) = VDS 140 mV = = 175 mΩ I CHR( MAX ) 800 mA –15– ADP3408 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Thin Shrink Small Outline (TSSOP) (RU-28) ß 28 C02623–1–9/01(0) 0.386 (9.80) 0.378 (9.60) 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. SEATING PLANE 0.0433 (1.10) MAX –16– REV. 0