GSM Power Management System ADP3522 FEATURES Handles all GSM Baseband Power Management 6 LDOs Optimized for Specific GSM Subsystems Li-Ion Battery Charge Function Optimized for the AD20msp430 Baseband Chipset Reduced Package Size: 5 mm 5 mm LFCSP-32 APPLICATIONS GSM/GPRS Handsets FUNCTIONAL BLOCK DIAGRAM VBAT VBAT2 VRTCIN POWER-UP PWRONKEY ROWX GENERAL DESCRIPTION The ADP3522 is a multifunction power system chip optimized for GSM/GPRS handsets, especially those based on the Analog Devices AD20msp430 system solution with 1.8 V digital baseband processors, such as the AD6525, AD6526, and AD6528. It contains six LDOs, one to power each of the critical GSM subblocks. Sophisticated controls are available for powerup during battery charging, keypad interface, and RTC alarm. The charge circuit maintains low current charging during the initial charge phase and provides an end of charge (EOC) signal when a Li-Ion battery is being charged. This product also meets the market trend of reduced size with a new LFCSP package. Its footprint is only 5 mm 5 mm and yet offers excellent thermal performance due to the exposed die attached paddle. The ADP3522 is specified over the temperature range of –20°C to +85°C. SEQUENCING AND PROTECTION LOGIC SIM LDO VSIM SIMVSEL DIGITAL CORE LDO VCORE PWRONIN ANALOG LDO TCXOEN VAN TCXO LDO VTCXO MEMORY LDO VMEM RTC LDO VRTC SIMEN RESCAP REF BUFFER REFOUT RESET CHRDET EOC CHGEN BATSNS BATTERY CHARGE CONTROLLER BATTERY VOLTAGE DIVIDER MVBAT DGND ISENSE GATEIN CHRIN ADP3522 AGND GATEDR REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADP3522–SPECIFICATIONS (–20C < T < +85C, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN = A 1 ELECTRICAL CHARACTERISTICS Parameter Symbol SHUTDOWN SUPPLY CURRENT VBAT ≤ 2.5 V (Deep Discharged Lockout Active) 2.5 V < VBAT ≤ 3.2 V (UVLO Active) VBAT > 3.2 V ICC OPERATING GROUND CURRENT VSIM, VCORE, VMEM, VRTC On All LDOs On All LDOs On IGND UVLO ON THRESHOLD VUVLO CVMEM = 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on all outputs, unless otherwise noted.) Conditions Min Typ Max Unit VBAT = VBAT2 = 2.3 V 15 40 µA VBAT = VBAT2 = 3.0 V 30 55 µA VBAT = VBAT2 = 4.0 V 45 80 µA VBAT = 3.6 V Minimum Loads Minimum Loads Maximum Loads 225 345 1.0 300 450 3.0 µA µA % of Max Load Rising Edge 3.2 3.3 V UVLO HYSTERESIS DEEP DISCHARGED LOCKOUT ON THRESHOLD 200 VDDLO Falling Edge mV 2.4 DEEP DISCHARGED LOCKOUT HYSTERESIS 2.75 100 V mV INPUT HIGH VOLTAGE PWRONIN TCXOEN, SIMEN, CHGEN, GATEIN, SIMVSEL VIH INPUT LOW VOLTAGE (PWRONIN, TCXOEN, SIMEN, CHGEN, SIMVSEL) VIL PWRONIN Pin Pull-Down Resistor RPD INPUT HIGH BIAS CURRENT (TCXOEN, SIMEN, CHGEN, SIMVSEL ) IIH INPUT LOW BIAS CURRENT (PWRONIN, TCXOEN, SIMEN, CHGEN, SIMVSEL) IIL –1.0 µA PWRONKEY INPUT HIGH VOLTAGE VIH 0.7 VBAT V PWRONKEY INPUT LOW VOLTAGE VIL 1.0 1.5 200 PWRONKEY INPUT PULL-UP RESISTANCE TO VBAT 70 V V 1000 100 0.3 V 5000 k 1.0 µA 0.3 VBAT V 130 k THERMAL SHUTDOWN THRESHOLD2 160 ºC THERMAL SHUTDOWN HYSTERESIS 45 ºC –2– REV. 0 ADP3522 Parameter Symbol Conditions ROWX CHARACTERISTICS ROWX Output Low Voltage VOL PWRONKEY = Low IOL = 200 µA PWRONKEY = High V(ROWX) = 5 V ROWX Output High Leakage Current SIM CARD LDO (VSIM) Output Voltage IIH VSIM Output Voltage VSIM Line Regulation Load Regulation VSIM VSIM Output Capacitor Required for Stability Dropout Voltage CO DIGITAL CORE LDO (VCORE) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability RTC LDO REAL-TIME CLOCK LDO/ COIN CELL CHARGER (VRTC) Maximum Output Voltage Maximum Output Current Off Reverse Input Current Output Capacitor Required for Stability ANALOG LDO (VAN) Output Voltage Line Regulation Load Regulation Output Capacitor Required for Stability Ripple Rejection Output Noise Voltage Dropout Voltage REV. 0 VDO Line, Load, Temperature SIMVSEL = Low Line, Load, Temperature SIMVSEL = High IL Unit 0.4 V 1 µA 1.80 1.90 V 2.80 2.85 2.92 V 2 2 VO = VINITIAL – 100 mV, ILOAD = 20 mA, VSIM = 2.85 V 1 µA ≤ ILOAD ≤ 10 µA VRTC = 0.5 V VRTC = 1.90 V, VBAT = 1.70 V, TA = 25°C mV mV µF 1.75 35 100 mV 1.80 2 8 1.85 V mV mV µF 2.2 1.86 1.95 4.0 2.0 V mA 0.5 µA µF 2.60 V mV mV 0.1 Line, Load, Temperature 2.50 50 µA ≤ ILOAD ≤ 180 mA, VBAT = 3.6 V CO VBAT/ VAN3 VNOISE Max 2.2 CO VAN VAN VAN Typ 1.70 50 µA ≤ ILOAD ≤ 20 mA VBAT = 3.6 V VCORE Line, Load, Temperature VCORE VCORE 50 µA ≤ ILOAD ≤ 100 mA VBAT = 3.6 V CO VRTC Min f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 180 mA VBAT = 3.6 V VO = VINITIAL – 100 mV, ILOAD = 180 mA –3– 2.55 2 11 2.2 µF 65 dB µV rms 80 160 400 mV ADP3522 (–20C < TA < +85C, VBAT = VBAT2 = 3 V–5.5 V, CVSIM = CVCORE = CVAN = CVMEM = 1 2.2 F, VTCXO = 0.22 F, CVRTC = 0.1 F, CVBAT = 10 F, minimum loads applied on ELECTRICAL CHARACTERISTICS all outputs, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit TCXO LDO (VTCXO) Output Voltage Line Regulation Load Regulation VTCXO VTCXO VTCXO Line, Load, Temperature 2.711 2.75 2 2 2.789 V mV mV Output Capacitor Required for Stability Dropout Voltage VDO Output Noise Voltage MEMORY LDO (VMEM) Output Voltage-3 Output Voltage-1.8 Line Regulation Load Regulation VMEM VMEM VMEM VMEM Output Capacitor Required for Stability Dropout Voltage-3 REFOUT Output Voltage Line Regulation Load Regulation Ripple Rejection Maximum Capacitive Load Output Noise Voltage RESET GENERATOR (RESET) Output High Voltage Output Low Voltage Output Current Delay Time per Unit Capacitance Applied to RESCAP Pin BATTERY VOLTAGE DIVIDER Divider Ratio Divider Impedance at MVBAT Divider Leakage Current Divider Resistance VO = VINITIAL – 100 mV ILOAD = 20 mA f = 217 Hz (t = 4.6 ms) VBAT = 3.6 V f = 10 Hz to 100 kHz ILOAD = 20 mA, VBAT = 3.6 V Line, Load, Temperature Line, Load, Temperature 160 2.740 1.80 VOH VOL IOL/IOH 2.80 1.85 2 12 2.850 1.90 µF 360 mV 1.19 1.21 0.2 0.5 1.23 V mV mV 65 75 dB 40 pF µV rms 100 IOH = +500 µA IOL = –500 µA VOL= 0.25 V, VOH = VMEM – 0.25 V TCXOEN = High MVBAT ZO TCXOEN = Low TCXOEN = High –4– V V mV mV 160 f = 10 Hz to 100 kHz tD BATSNS/ µV rms 2.2 Line, Load, Temperature Min Load 0 µA < ILOAD < 50 µA VBAT = 3.6 V f = 217 Hz (t = 4.6 ms) mV dB 80 VO = VINITIAL – 100 mV ILOAD = 150 mA VBAT/ VREFOUT CO VNOISE 300 65 50 µA < ILOAD < 150 mA VBAT = 3.6 V CO VREFOUT VREFOUT VREFOUT µF 0.22 CO VBAT/ VTCXO VNOISE Ripple Rejection 50 µA ≤ ILOAD ≤ 20 mA, VBAT = 3.6 V VMEM – 0.25 0.25 V V mA ms/nF 1 0.6 1.2 2.4 2.32 2.35 2.37 59.5 85 215 300 110 1 385 k µA k REV. 0 ADP3522 Parameter Symbol Conditions Min Typ Max Unit BATTERY CHARGER Charger Output Voltage BATSNS 4.35 V ≤ CHRIN ≤ 10 V3 4.150 4.200 4.250 V 4.250 V 15 mV Load Regulation BATSNS CHGEN = Low, No Load CHRIN = 10 V CHGEN = Low, No Load 0°C < TA < 50°C CHRIN = 5 V 4.155 0 ≤ CHRIN – ISENSE < Current Limit Threshold CHGEN = Low CHRDET On Threshold CHRDET Hysteresis CHRDET Off Delay4 CHRIN Supply Current Current Limit Threshold CHRIN – VBAT 90 40 6 0.6 150 mV mV ms/nF mA 142 160 190 mV 149 160 180 mV 20 35 mV CHRIN < VBAT CHRIN = 5 V CHRIN – ISENSE High Current Limit (UVLO Not Active) CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low CHRIN = 5 V DC VBAT = 3.6 V CHGEN = Low 0°C < TA < 50°C VBAT = 2 V CHGEN = Low CHRIN = 5 V – 10 V Low Current Limit (UVLO Active) ISENSE Bias Current EOC Signal Threshold 30 µA 200 CHRIN – ISENSE EOC Reset Threshold GATEDR Transition Time VBAT t R , tF GATEDR High Voltage VOH GATEDR Low Voltage VOL Output High Voltage (EOC, CHRDET) Output Low Voltage (EOC, CHRDET) VOH CHRIN = 5 V DC VBAT > 4.0 V CHGEN = Low CHGEN = Low CHRIN = 5 V VBAT > 3.6 V CHGEN = High, CL = 2 nF CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = High IOH = –1 mA CHRIN = 5 V VBAT = 3.6 V CHGEN = High GATEIN = Low IOL = 1 mA IOH = –250 µA VOL IOL = 250 µA 3.82 0.1 14 35 mV 3.96 4.10 1 V µs 4.5 V 0.5 VMEM – 0.25 V V 0.25 V NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 This feature is intended to protect against catastrophic failure of the device. Maximum allowed operating junction temperature is 125ºC. Operation beyond 125ºC could cause permanent damage to the device. 3 No isolation diode is present between the charger input and the battery. 4 Delay set by external capacitor on the RESCAP pin. Specifications subject to change without notice. REV. 0 –5– ADP3522 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Voltage on Any Pin with Respect to Any GND Pin . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V Voltage on Any Pin May Not Exceed VBAT, with the Following Exceptions: CHRIN, BASE, ISENSE Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C Operating Ambient Temperature Range . . . . . –20∞C to +85∞C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C JA, Thermal Impedance (LFCSP 5 mm ⫻ 5 mm) 4-Layer JEDEC PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 32∞C/W 2-Layer SEMI PCB . . . . . . . . . . . . . . . . . . . . . . . . . . 108∞C/W Lead Temperature Range (Soldering, 60 sec.) . . . . . . . . 300∞C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND. ORDERING GUIDE Model Memory LDO Output Temperature Range Package Option ADP3522ACP-3 ADP3522ACP-1.8 2.80 V 1.80 V –20∞C to +85∞C –20∞C to +85∞C CP-32 CP-32 SIMEN 1 26 REFOUT 25 VTCXO 28 TCXOEN 27 AGND 29 PWRONIN 32 NC 31 ROWX 30 PWRONKEY PIN CONFIGURATION 24 NC 23 VAN 22 VBAT PIN 1 INDICATOR VRTCIN 2 VRTC 3 BATSNS 4 21 VCORE ADP3522 MVBAT 5 20 VMEM 19 VBAT2 18 VSIM 17 NC TOP VIEW RESET 16 RESCAP 15 EOC 13 CHGEN 14 GATEDR 9 CHRDET 6 CHRIN 7 SIMVSEL 8 GATEIN 10 DGND 11 ISENSE 12 (Not Scale) TOPtoVIEW Pin Mnemonic Description 1 SIMEN SIM LDO Enable 2 VRTCIN RTC LDO Input Voltage 3 VRTC Real-Time Clock Supply/ Coin Cell Battery Charger 4 BATSNS Battery Voltage Sense Input 5 MVBAT Divided Battery Voltage Output 6 CHRDET Charge Detect Output 7 CHRIN Charger Input Voltage 8 SIMVSEL Programs VSIM Output; Low: 1.8 V 9 GATEDR Charger Drive Output 10 GATEIN Microprocessor Charger Gate Control Input 11 DGND Digital Ground 12 ISENSE Charge Current Sense Input 13 EOC End of Charge Output 14 CHGEN Charge Enable Control Input 15 RESCAP Reset Delay Time 16 RESET Main Reset, Open Drain 17, 24, 32 NC No Connection 18 VSIM SIM LDO Output 19 VBAT2 Battery Input Voltage 2 20 VMEM Memory LDO Output 21 VCORE Digital Core LDO Output 22 VBAT Battery Input Voltage 23 VAN Analog LDO Output 25 VTCXO TCXO LDO Output 26 REFOUT Output Reference 27 AGND Analog Ground 28 TCXOEN TCXO LDO Enable and MVBAT Enable 29 PWRONIN Power On/Off Signal from Microprocessor 30 PWRONKEY Power On/Off Key 31 ROWX Power Key Interface Output CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3522 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. 0 Typical Performance Characteristics–ADP3522 450 1.8 10000 400 350 +85ⴗC 200 150 +25ⴗC 100 VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = L, TCXOEN = L) 100 –20ⴗC 1000 VSIM, VCORE, VMEM, VRTC, ON_MIN_LOAD (SIMEN = H, TCXOEN = L) 250 IRTC – A IGND – A 300 REVERSE LEAKAGE CURRENT – A ALL LDO, MVBAT, REFOUT, ON_MIN_LOAD (SIMEN = H, TCXOEN = H) 50 0 3.0 10 3.5 4.0 4.5 VBAT – V 5.0 0 5.5 TPC 1. Ground Current vs. Battery Voltage 0.5 1.0 VRTC – V 1.5 TPC 2. RTC I/V Characteristic 2.0 1.6 1.4 RTC REVERSE LEAKAGE (VBAT = FLOAT) 1.2 1.0 0.8 RTC REVERSE LEAKAGE (VBAT = 2.3V) 0.6 0.4 0.2 0 25 30 35 40 45 50 55 60 65 70 75 80 85 TEMPERATURE – ⴗC TPC 3. VRTC Reverse Leakage Current vs. Temperature 180 160 3.2 DROPOUT VOLTAGE – mV VTCXO VMEM 140 3.2 VAN VBAT 120 VBAT 3.0 3.0 100 80 60 VSIM VTCXO 10mV/DIV VTCXO 10mV/DIV VMEM 10mV/DIV VMEM 10mV/DIV 40 20 0 0 50 100 150 LOAD CURRENT – mA TPC 4. Dropout Voltage vs. Load Current TIME – 100s/DIV 200 TPC 5. Line Transient Response, Minimum Loads TIME – 100s/DIV TPC 6. Line Transient Response, Maximum Loads 3.2 3.2 20mA LOAD VBAT VBAT 3.0 3.0 2mA VAN 10mV/DIV VAN 10mV/DIV VCORE 10mV/DIV VCORE 10mV/DIV VSIM 10mV/DIV VSIM 10mV/DIV TIME – 100s/DIV TPC 7. Line Transient Response, Minimum Loads REV. 0 TIME – 100s/DIV TPC 8. Line Transient Response, Maximum Loads –7– VTCXO 10mV/DIV TIME – 200s/DIV TPC 9. VTCXO Load Step ADP3522 100mA 150mA 15mA LOAD VSIM LOAD LOAD 20mA 10mA 2mA VCORE VMEM 10mV/DIV 20mV/DIV 10mV/DIV TIME – 200s/DIV TIME – 200s/DIV TPC 10. VSIM Load Step TPC 11. VMEM Load Step 180mA PWRONIN (2V/DIV) LOAD TIME – 200s/DIV TPC 12. VCORE Load Setup PWRONIN (2V/DIV) 18mA VAN (100mV/DIV) VSIM = 2.8 (100mV/DIV) VMEM = 1.8 (100mV/DIV) 20mV/DIV VCORE (100mV/DIV) TIME – 200s/DIV TIME – 400s/DIV TIME – 200s/DIV TPC 13. VAN Load Step TPC 14. Turn On Transient by PWRONIN, Minimum Load (Part 1) TPC 15. Turn On Transient by PWRONIN, Minimum Load (Part 2) PWRONIN (2V/DIV) PWRONIN (2V/DIV) PWRONIN (2V/DIV) REFOUT (100mV/DIV) VAN (100mV/DIV) VSIM = 1.8 (100V/DIV) VMEM = 2.8 (100mV/DIV) VSIM = 2.8 (100mV/DIV) VTCXO (100mV/DIV) VCORE (100mV/DIV) TIME – 100s/DIV TIME – 1ms/DIV TIME – 20s/DIV TPC 16. Turn On Transient by PWRONIN, Minimum Load (Part 3) TPC 17. Turn On Transient by PWRONIN, Minimum Load (Part 4) TPC 18. Turn On Transient by PWRONIN, Maximum Load (Part 1) –8– REV. 0 ADP3522 PWRONIN (2V/DIV) PWRONIN (2V/DIV) PWRONIN (2V/DIV) REFOUT (100mV/DIV) VSIM = 1.8 (100mV/DIV) VMEM = 2.8(100mV/DIV) VMEM = 1.8 (100mV/DIV) VTCXO (100mV/DIV) TIME – 100s/DIV TIME – 20s/DIV TPC 21. Turn On Transient by PWRONIN, Maximum Load (Part 4) 80 80 REFOUT VTCXO 70 VAN 60 VCORE 50 REFOUT 40 MLCC OUTPUT CAPS VBAT = 3.2V, FULL LOADS 30 20 RIPPLE REJECTION – dB 70 60 50 VSIM 40 VAN 30 20 VTCXO 10 10 VMEM 0 2.5 0 4 10 100 1k 10k FREQUENCY – Hz 100k 2.6 2.7 VSIM = 2.8V FREQ = 217Hz, MAX LOADS 2.8 2.9 3.0 VBAT – V 3.1 3.2 3.3 VOLTAGE SPECTRAL NOISE DENSITY – nV/ Hz TPC 20. Turn On Transient by PWRONIN, Maximum Load (Part 3) TPC 19. Turn On Transient by PWRONIN, Maximum Load (Part 2) RIPPLE REJECTION – dB TIME – 20s/DIV TPC 23. Ripple Rejection vs. Battery Voltage TPC 22. Ripple Rejection vs. Frequency FULL LOAD MLCC CAPS 500 VAN 400 TCXO 300 200 REF 100 0 10 100 1k 10k FREQUENCY – Hz 100k TPC 24. Output Noise Density 4.24 4.24 4.25 600 VIN = 5.0V RSENSE = 250m 4.24 RSENSE = 250m 4.22 4.21 4.20 4.19 4.18 4.23 OUTPUT VOLTAGE – V OUTPUT VOLTAGE – V CHARGER VOUT – V 4.23 4.22 4.21 4.23 ILOAD = 500mA 4.22 ILOAD = 10mA 4.21 4.17 4.16 4.15 –40 4.20 –20 0 20 40 60 80 100 120 TEMPERATURE – C TPC 25. Charger VOUT vs. Temperature, VIN = 5.0 V, ILOAD = 10 mA REV. 0 0 200 400 ILOAD – mA 600 TPC 26. Charger VOUT vs. ILOAD (VIN = 5.0 V) –9– 800 4.20 5 6 7 8 INPUT VOLTAGE – V 9 TPC 27. Charger VOUT vs. VIN 10 ADP3522 X OFF OFF OFF OFF OFF OFF OFF OFF State No. 2 Phone Off H L X X X X X OFF OFF OFF ON OFF OFF OFF OFF State No. 3 Phone Off, Turn-On Allowed H H L H L X X OFF OFF OFF ON OFF OFF OFF OFF State No. 4 Charger Applied H H H X X X L OFF ON ON ON ON ON ON ON* State No. 5 Phone Turned On by User Key H H X L X X L OFF ON ON ON ON ON ON ON* State No. 6 Deep Sleep H H L H H L H ON ON ON ON OFF OFF OFF OFF State No. 7 Active H H L H H H H ON ON ON ON ON ON ON ON State No. 8 Reset SIM Card H H L H H H L OFF ON ON ON ON ON ON ON MVBAT X REFOUT SIMEN X VTCXO TCXOEN X VAN PWRONIN X VRTC PWRONKEY X VMEM CHRDET L VCORE UVLO State No. 1 Battery Deep Discharged VSIM STATE NO. PHONE STATUS DDLO Table I. LDO Control Logic *The state of MVBAT is determined by TCXOEN. When TCXOEN is high, MVBAT is ON. –10– REV. 0 ADP3522 VBAT VRTCIN SIMVSEL VBAT2 SIM LDO VBAT DEEP DISCHARGED UVLO 110k⍀ EN UVLO Q S PWRONKEY VREF VSEL OUT VSIM DGND R DIGITAL CORE LDO ROWX OVERTEMP SHUTDOWN VBAT VREF PWRONIN EN OUT VCORE PG DGND 1M⍀ ANALOG LDO VBAT SIMEN CHARGER DETECT VREF EN AGND OUT VAN TCXOEN TCXO LDO RESCAP RESET GENERATOR CHRDET VREF EOC CHGEN GATEIN BATSNS RESET VBAT OUT VTCXO EN AGND Li-ION BATTERY CHARGE CONTROLLER AND PROCESSOR CHARGE INTERFACE MEMORY LDO VBAT VREF OUT VMEM OUT VRTC EN DGND ISENSE RTC LDO VBAT GATEDR VREF CHRIN EN DGND EN REF BUFFER 1.21V MVBAT REFOUT AGND DGND AGND Figure 1. Functional Block Diagram REV. 0 –11– ADP3522 PWRON POWERKEY ROWX CLKON R8 10 REFOUT VTCXO VRTCIN MVBAT CHRDET VCORE VCORE VMEM VMEM CHRDET VBAT2 ADP3522 VSIM RESCAP EOC CHGEN DGND GATEDR ISENSE C2 1nF GATEIN R1 0.25 VAN C10 2.2F MVBAT BATSNS SIMVSEL SIMSEL VTCXO AGND VAN VBAT CHRIN CHRIN C9 0.22F NC RESET C1 0.1F COIN CELL REFOUT VRTC TCXOEN VRTC PWRONIN SIMEN PWRONKEY NC SIMEN ROWX C8 0.1F VSIM NC Q1 SI3441 RESET CHGEN EOC D1 BAT1000 Li OR NiMH BATTERY C3 10F C4 0.1F C5 2.2F C6 2.2F C7 2.2F GATEIN Figure 2. Typical Application Circuit ADP3522 needs to dissipate. The thermal impedance of the CSP package is 32°C/W for a JEDEC standard 4-layer board. THEORY OF OPERATION The ADP3522 is a power management chip optimized for use with GSM baseband chipsets in handset applications. Figure 1 shows a block diagram of the ADP3522. The ADP3522 contains several blocks, such as: The end of charge voltage for high capacity NiMH cells can be as high as 5.5 V. This results in a worst-case power dissipation for the ADP3522-1.8 to be as high as 1.6 W for NiMH cells. The power dissipation for the ADP3522-3 is slightly lower at 1.45 W. • Six low dropout regulators (SIM, core, analog, crystal oscillator, memory, real-time clock) A fully charged Li-Ion battery is 4.25 V, where the ADP3522-3 can dissipate a maximum power of 0.85 W. However, the ADP3522-1.8 can have a maximum dissipation of 1.0 W. • Reset generator • Buffered precision reference High battery voltages normally occur when the battery is being charged and the handset is not in conversation mode. In this mode, there is a relatively light load on the LDOs. The worstcase power dissipation should be calculated based on the actual load currents and voltages used. • Lithium ion charge controller and processor interface • Power on/off logic • Undervoltage lockout • Deep discharge lockout These functions have traditionally been done either as a discrete implementation or as a custom ASIC design. The ADP3522 combines the benefits of both worlds by providing an integrated standard product where every block is optimized to operate in a GSM environment while maintaining a cost competitive solution. Figure 2 shows the external circuitry associated with the ADP3522. Only a minimal number of support components are required. Input Voltage Figure 3 shows the maximum power dissipation as a function of the input voltage. Figure 4 shows the maximum allowable power dissipation as a function of the ambient temperature. Low Dropout Regulators (LDOs) The ADP3522 high performance LDOs are optimized for their given functions by balancing quiescent current, dropout voltage, regulation, ripple rejection, and output noise. 2.2 µF tantalum or MLCC ceramic capacitors are recommended for use with the core, memory, SIM, and analog LDOs. A 0.22 µF capacitor is recommended for the TCXO LDO. The input voltage range of the ADP3522 is 3 V to 5.5 V and is optimized for a single Li-Ion cell or three NiMH cells. The type of battery, the SIM LDO output voltage, and the memory LDO output voltage will all affect the amount of power that the –12– REV. 0 ADP3522 Applying a low to SIMEN shuts down the SIM LDO. A discharge circuit is active when SIMEN is low. This pulls the SIM LDO’s output down when the LDO is disabled. Digital Core LDO (VCORE) The digital core LDO supplies the baseband circuitry in the handset (baseband processor and baseband converter). The LDO has been optimized for very low quiescent current at light loads as this LDO is on whenever the handset is switched on. SIMVSEL allows the SIM LDO to be programmed for either 1.8 V or 2.8 V. Asserting a high on SIMVSEL sets the output for 2.8 V. Memory LDO (VMEM) The memory LDO supplies the system memory as well as the subsystems of the baseband processor including memory IO, display, and melody interfaces. It is capable of delivering up to 150 mA of current and is available for either 1.8 V or 3 V based systems. The LDO has also been optimized for low quiescent current and will power up at the same time as the core LDO. SIMEN and SIMVSEL allow the baseband processor to properly sequence the SIM supply when determining which type of SIM module is present. Reference Output (REFOUT) Analog LDO (VAN) This LDO has the same features as the core LDO. It has furthermore been optimized for good low frequency ripple rejection for use with the baseband converter sections in order to reject the ripple coming from the RF power amplifier. VAN is rated to 180 mA, which is sufficient to supply the analog section of the baseband converter, such as the AD6521, as well as the microphone and speaker. TCXO LDO (VTCXO) RTC LDO (VRTC) The RTC LDO is capable of charging rechargeable Lithium or capacitor-type backup coin cells to run the real-time clock module. The RTC LDO supplies current both for charging the coin cell and for the RTC module. In addition, it features a very low quiescent current since this LDO is running all the time, even when the handset is switched off. It also has reverse current protection with low leakage, which is needed when the main battery is removed and the coin cell supplies the RTC module. The ADP3522 handles all issues regarding the powering ON and OFF of the handset. It is possible to turn on the ADP3522 in three different ways: • Pulling the PWRONKEY low • Pulling the PWRONIN high Pulling the PWRONKEY low is the normal way of turning on the handset. This will turn on all the LDOs, except the SIM LDO, as long as the PWRONKEY is held low. When the VCORE LDO comes into regulation, the RESET timer is started. After timing out, the RESET pin goes high, allowing the baseband processor to start up. With the baseband processor running, it can poll the ROWX pin of the ADP3522 to determine if the PWRONKEY has been depressed and pull PWRONIN high. Once the PWRONIN is taken high, the PWRONKEY can be released. Note that by monitoring the ROWX pin, the baseband processor can detect a second PWRONKEY and press and turn the LDOs off in an orderly manner. In this way, the PWRONKEY can be used for ON/OFF control. Pulling the PWRONIN pin high is how the alarm in the realtime clock module will turn the handset on. Asserting PWRONIN will turn the core and memory LDOs on, starting up the baseband processor. 1.8 1.8 1.6 1.6 1.4 ADP3522-1.8 POWER DISSIPATION – W POWER DISSIPATION – W The SIM LDO generates the voltage needed for 1.8 V or 3 V SIMs. It is rated for 20 mA of supply current and can be controlled completely independently of the other LDOs. Power ON/OFF • CHRIN exceeds CHRDET threshold The TCXO LDO is intended as a supply for a temperature compensated crystal oscillator, which needs its own ultralow noise supply. VTCXO is rated for 20 mA of output current and is turned on along with the analog LDO when TCXOEN is asserted. Note that the ADP3522 has been optimized for use with the AD6534 (Othello One™). SIM LDO (VSIM) The reference output is a low noise, high precision reference with a guaranteed accuracy of 1.5% overtemperature. The maximum output current of the REFOUT supply is limited to 50 µA. 1.2 ADP3522-2.8 1.0 0.8 0.6 1.0 0.8 0.6 0.4 0.2 0.2 3.5 4.0 4.5 5.0 5.5 0 –20 6.0 0 20 40 60 80 AMBIENT TEMPERATURE – C INPUT VOLTAGE – V Figure 3. Power Dissipation vs. Input Voltage REV. 0 1.2 0.4 0 3.0 LFCSP 32C/W 1.4 Figure 4. Allowable Package Power Dissipation vs. Temperature –13– ADP3522 NONCHARGING MODE CHARGER DETECTED CHRIN > BATSNS NO YES VBAT > UVLO YES NO BATTERY TYPE NiMH LOW CURRENT CHARGE MODE Li+ VSENSE = 20mV CHGEN = LOW CHGEN = HIGH HIGH CURRENT CHARGE MODE NiMH CHARGING MODE VSENSE = 160mV GATEIN = PULSED NO NO VBAT > 4.2V YES CONSTANT VOLTAGE MODE YES VBAT > 5.5V YES NiMH CHARGER OFF GATEIN = HIGH NO END OF CHARGE VSENSE < 14mV YES NO VBAT > 5.5V YES EOC = HIGH TERMINATE CHARGE CHGEN = HIGH GATEIN = HIGH Figure 5. Battery Charger Flow Chart –14– REV. 0 ADP3522 Applying an external charger can also turn the handset on. This will turn on all the LDOs, except the SIM LDO, again starting up the baseband processor. Note that if the battery voltage is below the undervoltage lockout threshold, applying the adapter will not start up the LDOs. Overtemperature Protection The maximum die temperature for the ADP3522 is 125°C. If the die temperature exceeds 160°C, the ADP3522 will disable all the LDOs except the RTC LDO. The LDOs will not be re-enabled before the die temperature is below 125°C, regardless of the state of PWRONKEY, PWRONIN, and CHRDET. This ensures that the handset will always power off before the ADP3522 exceeds its absolute maximum thermal ratings. Deep Discharge Lockout (DDLO) The DDLO block in the ADP3522 shuts down the handset in the event that the software fails to turn off the phone when the battery voltage drops below 2.9 V to 3.0 V. The DDLO will shut down the handset when the battery falls below 2.4 V to prevent further discharge and damage to the battery. Battery Charging The DDLO will also shut down the RTC LDO when the main battery is removed. This will prevent reverse current from discharging the backup coin cell. The ADP3522 battery charger can be used with lithium ion (Li+) and nickel metal hydride (NiMH) batteries. The charger initialization, trickle charging, and Li+ charging are implemented in hardware. Battery type determination and NiMH charging must be implemented in software. Undervoltage Lockout (UVLO) The charger block works in three different modes: The UVLO function in the ADP3522 prevents startup when the initial voltage of the battery is below the 3.2 V threshold. If the battery voltage is this low with no load, there is insufficient capacity left to run the handset. When the battery is greater than 3.2 V, such as inserting a fresh battery, the UVLO comparator trips, and the threshold is reduced to 3.0 V. This allows the handset to start normally until the battery decays to below 3.0 V. 1. Low current (trickle) charging Once the system is started and the core and memory LDOs are up and running, the UVLO function is entirely disabled. The ADP3522 is then allowed to run until the battery voltage reaches the DDLO threshold, typically 2.4 V. Normally, the battery voltage is monitored by the baseband processor, which usually shuts the phone off at a battery voltage of around 3.0 V. 2. Lithium ion charging 3. Nickel metal hydride charging See Figure 5 for the charger flow chart. Charge Detection The ADP3522 charger block has a detection circuit that determines if an adapter has been applied to the CHRIN pin. If the adapter voltage exceeds the battery voltage by 100 mV, the CHRDET output will go high. If the adapter is then removed and the voltage at the CHRIN pin drops to only 50 mV above the BATSNS pin, CHRDET goes low. The CHRDET signal is not asserted if the battery voltage is below the UVLO threshold. If the handset is off and the battery voltage drops below 3.0 V, the UVLO circuit disables startup and puts the ADP3522 into UVLO shutdown mode. In this mode, the ADP3522 draws very low quiescent current, typically 30 µA. In DDLO mode, the ADP3522 draws 15 µA of quiescent current. NiMH batteries can reverse polarity if the 3-cell battery voltage drops below 3.0 V, which will degrade the batteries’ performance. Lithium ion batteries will lose their capacity if overdischarged repeatedly, so minimizing the quiescent currents helps prevent battery damage. Trickle Charging RESET Trickle charging is performed for deeply discharged batteries to prevent undue stress on either the battery or the charger. Trickle charging will continue until the battery voltage exceeds the UVLO threshold. When the battery voltage is below the UVLO threshold, the charge current is set to the low current limit, or about 10% of the full charge current. The low current limit is determined by the voltage developed across the current sense resistor. Therefore, the trickle charge current can be calculated by ICHR(TRICKLE ) = The ADP3522 contains a reset circuit that is active both at power-up and power-down. The RESET pin is held low at initial power-up. An internal power good signal is generated by the core LDO when its output is up, starting the reset delay timer. The delay is set by an external capacitor on RESCAP: tRESET = 1.2 ms × CRESCAP nF (1) At power-off, RESET will be kept low to prevent any baseband processor starts. REV. 0 20 mV RSENSE (2) Once the UVLO threshold has been exceeded, the charger will switch to the default charge mode, the LDOs will start up, and the baseband processor will start to run. The processor must then poll the battery to determine which chemistry is present and set the charger to the proper mode. Control of the charge mode, Li+ or NiMH, is determined by the CHGEN input. –15– ADP3522 processor can charge a NiMH battery. Note that when charging NiMH cells, a current limited adapter is required. 4.2V VBAT During the PMOS off periods, the battery voltage needs to be monitored through the MVBAT pin. The battery voltage is continually polled until the final battery voltage is reached. Then the charge can either be terminated or the frequency of the pulsing reduced. An alternative method of determining the end of charge is to monitor the temperature of the cells and terminate the charging when a rapid rise in temperature is detected. 3.2V Battery Voltage Monitoring HIGH CURRENT The battery voltage can be monitored at MVBAT during charging and discharging to determine the condition of the battery. An internal resistor divider can be connected to BATSNS when both the digital and analog baseband sections are powered up. To enable MVBAT, both PWRONIN and TCXOEN must be high. ICHARGE LOW CURRENT EOC CURRENT 0 The ratio of the voltage divider is selected so that the 2.4 V maximum input of the AD6521’s auxiliary ADC will correspond with the maximum battery voltage of 5.5 V. The divider will be disconnected from the battery when the baseband sections are powered down. EOC INDICATOR APPLICATION INFORMATION Input Capacitor Selection Figure 6. Lithium Ion Charging Diagram Lithium Ion Charging For lithium ion charging, the CHGEN input must be low. This allows the ADP3522 to continue charging the battery at the full current. The full charge current can be calculated by using ICHR( FULL ) = 160 mV RSENSE (3) If the voltage at BATSNS is below the charger’s output voltage of 4.2 V, the battery will continue to charge in the constant current mode. If the battery has reached the final charge voltage, a constant voltage is applied to the battery until the charge current has reduced to the charge termination threshold. The charge termination threshold is determined by the voltage across the sense resistor. If the battery voltage is above 4.0 V and the voltage across the sense resistor has dropped to 14 mV, then an end of charge signal is generated—the EOC output goes high (see Figure 6). The baseband processor can either let the charger continue to charge the battery for an additional amount of time or terminate the charging. To terminate the charging, the processor must pull the GATEIN pin high and the CHGEN pin high. NiMH Charging For NiMH charging, the processor must pull the CHGEN pin high. This disables the internal Li+ mode control of the gate drive pin. The gate drive must now be controlled by the baseband processor. By pulling GATEIN high, the GATEDR pin is driven high, turning the PMOS off. By pulling the GATEIN pin low, the GATEDR pin is driven low, and the PMOS is turned on. So, by pulsing the GATEIN input, the For the input (VBAT, VBAT2, and VRTCIN) of the ADP3522, a local bypass capacitor is recommended; use a 10 µF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size but may not be cost effective. A lower cost alternative may be to use a 10 µF tantalum capacitor with a small (1 µF to 2 µF) ceramic in parallel. Separate inputs for the SIM LDO and the RTC LDO are supplied for additional bypassing or filtering. The SIM LDO has VBAT2 as its input and the RTC LDO has VRTCIN. LDO Capacitor Selection The performance of any LDO is a function of the output capacitor. The core, memory, SIM, and analog LDOs require a 2.2 µF capacitor and the TCXO LDO requires a 0.22 µF capacitor. Larger values may be used, but the overshoot at startup will increase slightly. If a larger output capacitor is desired, be sure to check that the overshoot and settling time are acceptable for the application. All the LDOs are stable with a wide range of capacitor types and ESR (anyCAP® technology). The ADP3522 is stable with extremely low ESR capacitors (ESR ~ 0) such as multilayer ceramic capacitors (MLCC), but care should be taken in their selection. Note that the capacitance of some capacitor types shows wide variations over temperature or with dc voltage. A good quality dielectric, X7R or better, capacitor is recommended. The RTC LDO can have a rechargeable coin cell or an electric double-layer capacitor as a load, but an additional 0.1 µF ceramic capacitor is recommended for stability and best performance. –16– REV. 0 ADP3522 CHARGER CHARACTERISTIC CHARGE CHARACTERISTIC 2.0 2.00 1.9 1.75 1.8 1.50 1.7 1.6 VBAT – V VBAT – V 1.25 1.00 0.75 1.5 1.4 1.3 1.2 0.50 1.1 0.25 1.0 0.9 0 0 20 40 60 80 100 0 120 5 10 15 Figure 7. Kanebo PAS621 Charge Characteristic CHARGER CHARACTERISTIC 1.50 VBAT – V 1.25 1.00 0.75 0.50 0.25 0 40 60 30 35 40 80 Figure 10. Seiko TS621 Charge Characteristic The choice of the backup cell is based upon size, cost, and capacity. It must be able to support the RTC module’s current requirement and voltage range, as well as handle the charge current supplied by the ADP3522 (see TPC 2). Check with the coin cell vendor if the ADP3522’s charge current profile is acceptable. 1.75 20 25 RTC Backup Coin Cell Selection 2.00 0 20 TIME – Hours TIME – Minutes 100 120 TIME – Minutes Figure 8. Panasonic EECEM0E204A Charge Characteristic Some suitable coin cells are the electric double layer capacitors available from Kanebo (PAS621), Seiko (XC621), or Panasonic (EECEM0E204A). They have a small physical size (6.8 mm diameter) and a nominal capacity of 0.2 F to 0.3 F, giving hours of backup time. Rechargeable lithium coin cells, such as the TC614 from Maxell or the TS621 from Seiko, are also small in size but have higher capacity than the double layer capacitors, resulting in longer backup times. Typical charge curves for each cell type are shown in Figures 7 through 10. Note that the rechargeable lithium type coin cells generally come precharged from the vendor. RESET Capacitor Selection CHARGE CHARACTERISTIC RESET is held low at power up. An internal power-good signal starts the reset delay when the core LDO is up. The delay is set by an external capacitor on RESCAP: 2.0 1.9 1.8 tRESET = 1.2 1.7 ms × CRESCAP nF VBAT – V 1.6 A 100 nF capacitor will produce a 120 ms reset delay. The current capability of RESET is minimal (a few hundred nA) when VCORE is off to minimize power consumption. When VCORE is on, RESET is capable of driving 500 µA. 1.5 1.4 1.3 1.2 Setting the Charge Current 1.1 The ADP3522 is capable of charging both lithium ion and NiMH batteries. For NiMH batteries, the charge current is limited by the adapter. For lithium ion batteries, the charge 1.0 0.9 0 5 10 15 20 25 30 TIME – Hours Figure 9. Maxell TC614 Charge Characteristic REV. 0 –17– (4) ADP3522 current is programmed by selecting the sense resistor, R1 (see Figure 2). The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using: PDISS = VADAPTER( MAX ) − VDIODE − VSENSE The lithium ion charge current is calculated using ICHR = VSENSE 160 mV = R1 R1 where VSENSE is the high current limit threshold voltage. Or if the charge current is known, R1 can be found: R1 = VSENSE 160 mV = ICHR ICHR (6) Similarly the trickle charge current and the end of charge current can be calculated: ITRICKLE = IEOC = VSENSE 20 mV = R1 R1 VSENSE 14 mV = R1 R1 (7) (12) − UVLO × ICHR (5) It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case, the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an overspecified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V (8) VADAPTER(MAX) = 6.5 V Example: Assume an 800 mA-H capacity lithium ion battery and a 1 C charge rate. R1 = 200 m. Then ITRICKLE = 100 mA and IEOC = 70 mA. VDIODE = 0.5 V at 800 mA VGATEDR = 0.5 V VSENSE = 160 mV Appropriate sense resistors are available from the following vendors: VGS = 5 V – 0.5 V – 0.160 V = 4.3 V. So choose a low • Vishay Dale threshold voltage FET. • IRC VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT • Panasonic (13) Charger FET Selection VDS = 5 V - 0.5 V - 0.160 V - 4.2 V = 140 mV The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and charge current. The selected PMOS must satisfy the physical, electrical, and thermal design requirements. RDS ( ON ) = To ensure proper operation, the minimum VGS the ADP3522 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following: VGS = VADAPTER( MIN ) - VGATEDR - VSENSE VDS ICHR( MAX ) = 140 mV = 175 mΩ 800 mA (14) PDISS = (VADAPTER( MAX ) − VDIODE − VSENSE (9) − UVLO) × ICHR (15) where VADAPTER(MIN) is the minimum adapter voltage. PDISS = (6.5V − 0.5V − 0.160 V − 3.2V ) VGATEDR is the gate drive “low” voltage, 0.5 V. × 0.8 A = 2.1W VSENSE is the maximum high current limit threshold voltage. Appropriate PMOS FETs are available from the following vendors: The difference between the adapter voltage (VADAPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the on resistance of the FET at maximum charge current. VDS = VADAPTER - VDIODE - VSENSE - VBAT (10) Then the RDS(ON) of the FET can be calculated: RDS ( ON ) = VDS ICHR( MAX ) (11) • Siliconix • IR • Fairchild Charger Diode Selection The diode, D1, shown in Figure 2 is used to prevent the battery from discharging through the PMOS’ body diode into the charger’s internal bias circuits. A Schottky diode is recommended to minimize the voltage difference from the charger to the battery and the power dissipation. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types. –18– REV. 0 ADP3522 path to the inner or bottom layers. See Figure 12 for the recommended via pattern. Note that the via diameter is small. This is to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3522. Locate the input capacitor as close to the pins as possible. Note that the thermal pad is attached to the die substrate; the thermal planes that the vias attach the package to must be electrically isolated or connected to VBAT. Do NOT connect the thermal pad to ground. 2. VAN and VTCXO output capacitors should be returned to AGND. 3. VCORE, VMEM, and VSIM output capacitors should be returned to DGND. 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 3. The solder mask opening should be about 120 microns (4.7 mils) larger than the pad size resulting in a minimum 60 microns (2.4 mils) clearance between the pad and the solder mask. 4. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the large size of the thermal pad, eliminating voids may not be possible. Also, if the solder paste coverage is too large, solder joint defects may occur. Therefore, it is recommended to use multiple small openings over a single big opening in designing the paste mask. The recommended paste mask pattern is given in Figure 13. This pattern will result in about 80% coverage, which should not degrade the thermal performance of the package significantly. 6. Kelvin connect the charger’s sense resistor by running separate traces to the CHRIN pin and ISENSE pin. Make sure the traces are terminated as close to the resistor’s body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3522 and charger components. Careful use of copper area, weight, and multilayer construction all contribute to improved thermal performance. LFCSP Layout Considerations The CSP package has an exposed die paddle on the bottom that efficiently conducts heat to the PCB. In order to achieve the optimum performance from the CSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the CSP package: 1. The pad pattern is given in Figure 11. The pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging. 2. The thermal pad of the CSP package provides a low thermal impedance path (approximately 15°C/W) to the PCB. Therefore, the PCB must be properly designed to effectively conduct the heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal REV. 0 5. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A “No Clean,” Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. 6. The package manufacturer recommends that the reflow temperature should not exceed 220°C and the time above liquids is less than 75 seconds. The preheat ramp should be 3°C/second or lower. The actual temperature profile depends on the board’s density and must be determined by the assembly house as to what works best. –19– ADP3522 0.08 CREATE SOLDER PASTE WEB FOR APPROX 80% COVERAGE 125 MICRONS WIDE TO SEPARATE SOLDER PASTE AREA 3.80 5.36 3.96 3.56 THERMAL PAD AREA 0.70 0.20 Dimensions shown in millimeters Figure 13. 5 mm ⫻ 5 mm LFSCP Solder Paste Mask Pattern Figure 11. 5 mm ⫻ 5 mm LFCSP Pad Pattern ARRAY OF 9 VIAS 0.25mm DIAMETER 0.35m PLATING C03535–0–2/03(0) 0.30 0.50 0.60 1.18 THERMAL PAD AREA 1.18 0.60 Dimensions shown in millimeters Figure 12. 5 mm ⫻ 5 mm LFSCP Via Pattern OUTLINE DIMENSIONS 32-Lead Frame Chip Scale Package [LFCSP] 5 mm 5 mm Body Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.60 MAX 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 3.25 3.10 SQ 2.95 BOTTOM VIEW 0.50 0.40 0.30 12 MAX 32 1 17 16 9 8 3.50 REF 1.00 MAX 0.65 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF PRINTED IN U.S.A. 0.05 MAX 0.02 NOM 1.00 0.90 0.80 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 –20– REV. 0